drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG(off, _mask, s) \
  24                 {.offset = off, \
  25                  .mask = _mask, \
  26                  .shift = s, \
  27                  .write_mask = false,}
  28
  29 #define VOP_REG_MASK(off, _mask, s) \
  30                 {.offset = off, \
  31                  .mask = _mask, \
  32                  .shift = s, \
  33                  .write_mask = true,}
  34
  35 static const uint32_t formats_win_full[] = {
  36         DRM_FORMAT_XRGB8888,
  37         DRM_FORMAT_ARGB8888,
  38         DRM_FORMAT_XBGR8888,
  39         DRM_FORMAT_ABGR8888,
  40         DRM_FORMAT_RGB888,
  41         DRM_FORMAT_BGR888,
  42         DRM_FORMAT_RGB565,
  43         DRM_FORMAT_BGR565,
  44         DRM_FORMAT_NV12,
  45         DRM_FORMAT_NV16,
  46         DRM_FORMAT_NV24,
  47 };
  48
  49 static const uint32_t formats_win_lite[] = {
  50         DRM_FORMAT_XRGB8888,
  51         DRM_FORMAT_ARGB8888,
  52         DRM_FORMAT_XBGR8888,
  53         DRM_FORMAT_ABGR8888,
  54         DRM_FORMAT_RGB888,
  55         DRM_FORMAT_BGR888,
  56         DRM_FORMAT_RGB565,
  57         DRM_FORMAT_BGR565,
  58 };
  59
  60 static const struct vop_scl_regs rk3036_win_scl = {
  61         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  62         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
  63         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
  64         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
  65 };
  66
  67 static const struct vop_win_phy rk3036_win0_data = {
  68         .scl = &rk3036_win_scl,
  69         .data_formats = formats_win_full,
  70         .nformats = ARRAY_SIZE(formats_win_full),
  71         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
  72         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
  73         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
  74         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
  75         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
  76         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
  77         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
  78         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
  79         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
  80         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
  81 };
  82
  83 static const struct vop_win_phy rk3036_win1_data = {
  84         .data_formats = formats_win_lite,
  85         .nformats = ARRAY_SIZE(formats_win_lite),
  86         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
  87         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
  88         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
  89         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
  90         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
  91         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
  92         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
  93         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
  94 };
  95
  96 static const struct vop_win_data rk3036_vop_win_data[] = {
  97         { .base = 0x00, .phy = &rk3036_win0_data,
  98           .type = DRM_PLANE_TYPE_PRIMARY },
  99         { .base = 0x00, .phy = &rk3036_win1_data,
 100           .type = DRM_PLANE_TYPE_CURSOR },
 101 };
 102
 103 static const int rk3036_vop_intrs[] = {
 104         DSP_HOLD_VALID_INTR,
 105         FS_INTR,
 106         LINE_FLAG_INTR,
 107         BUS_ERROR_INTR,
 108 };
 109
 110 static const struct vop_intr rk3036_intr = {
 111         .intrs = rk3036_vop_intrs,
 112         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 113         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 114         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 115         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 116 };
 117
 118 static const struct vop_ctrl rk3036_ctrl_data = {
 119         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 120         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 121         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 122         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 123         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 124         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 125         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 126         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 127 };
 128
 129 static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
 130         {RK3036_DSP_CTRL1, 0x00000000},
 131 };
 132
 133 static const struct vop_data rk3036_vop = {
 134         .init_table = rk3036_vop_init_reg_table,
 135         .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
 136         .ctrl = &rk3036_ctrl_data,
 137         .intr = &rk3036_intr,
 138         .win = rk3036_vop_win_data,
 139         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 140 };
 141
 142 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
 143         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
 144         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
 145         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
 146         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
 147         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
 148         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
 149         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
 150         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
 151         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
 152         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
 153         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
 154         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
 155         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
 156         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
 157         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
 158         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
 159         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
 160         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
 161         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
 162         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
 163         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
 164 };
 165
 166 static const struct vop_scl_regs rk3288_win_full_scl = {
 167         .ext = &rk3288_win_full_scl_ext,
 168         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 169         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 170         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 171         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 172 };
 173
 174 static const struct vop_win_phy rk3288_win01_data = {
 175         .scl = &rk3288_win_full_scl,
 176         .data_formats = formats_win_full,
 177         .nformats = ARRAY_SIZE(formats_win_full),
 178         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 179         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 180         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 181         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 182         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 183         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 184         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 185         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 186         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 187         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 188         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 189         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
 190 };
 191
 192 static const struct vop_win_phy rk3288_win23_data = {
 193         .data_formats = formats_win_lite,
 194         .nformats = ARRAY_SIZE(formats_win_lite),
 195         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 196         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 197         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 198         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 199         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 200         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 201         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 202         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 203         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 204 };
 205
 206 static const struct vop_ctrl rk3288_ctrl_data = {
 207         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 208         .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 209         .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
 210         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 211         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 212         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 213         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 214         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 215         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 216         .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
 217         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 218         .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
 219         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 220         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 221         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 222         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 223         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 224         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 225         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 226 };
 227
 228 static const struct vop_reg_data rk3288_init_reg_table[] = {
 229         {RK3288_SYS_CTRL, 0x00c00000},
 230         {RK3288_DSP_CTRL0, 0x00000000},
 231         {RK3288_WIN0_CTRL0, 0x00000080},
 232         {RK3288_WIN1_CTRL0, 0x00000080},
 233         /* TODO: Win2/3 support multiple area function, but we haven't found
 234          * a suitable way to use it yet, so let's just use them as other windows
 235          * with only area 0 enabled.
 236          */
 237         {RK3288_WIN2_CTRL0, 0x00000010},
 238         {RK3288_WIN3_CTRL0, 0x00000010},
 239 };
 240
 241 /*
 242  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 243  * special support to get alpha blending working.  For now, just use overlay
 244  * window 3 for the drm cursor.
 245  *
 246  */
 247 static const struct vop_win_data rk3288_vop_win_data[] = {
 248         { .base = 0x00, .phy = &rk3288_win01_data,
 249           .type = DRM_PLANE_TYPE_PRIMARY },
 250         { .base = 0x40, .phy = &rk3288_win01_data,
 251           .type = DRM_PLANE_TYPE_OVERLAY },
 252         { .base = 0x00, .phy = &rk3288_win23_data,
 253           .type = DRM_PLANE_TYPE_OVERLAY },
 254         { .base = 0x50, .phy = &rk3288_win23_data,
 255           .type = DRM_PLANE_TYPE_CURSOR },
 256 };
 257
 258 static const int rk3288_vop_intrs[] = {
 259         DSP_HOLD_VALID_INTR,
 260         FS_INTR,
 261         LINE_FLAG_INTR,
 262         BUS_ERROR_INTR,
 263 };
 264
 265 static const struct vop_intr rk3288_vop_intr = {
 266         .intrs = rk3288_vop_intrs,
 267         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 268         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 269         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 270         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 271 };
 272
 273 static const struct vop_data rk3288_vop = {
 274         .init_table = rk3288_init_reg_table,
 275         .table_size = ARRAY_SIZE(rk3288_init_reg_table),
 276         .intr = &rk3288_vop_intr,
 277         .ctrl = &rk3288_ctrl_data,
 278         .win = rk3288_vop_win_data,
 279         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 280 };
 281
 282 static const struct of_device_id vop_driver_dt_match[] = {
 283         { .compatible = "rockchip,rk3036-vop",
 284           .data = &rk3036_vop },
 285         { .compatible = "rockchip,rk3288-vop",
 286           .data = &rk3288_vop },
 287         {},
 288 };
 289 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 290
 291 static int vop_probe(struct platform_device *pdev)
 292 {
 293         struct device *dev = &pdev->dev;
 294
 295         if (!dev->of_node) {
 296                 dev_err(dev, "can't find vop devices\n");
 297                 return -ENODEV;
 298         }
 299
 300         return component_add(dev, &vop_component_ops);
 301 }
 302
 303 static int vop_remove(struct platform_device *pdev)
 304 {
 305         component_del(&pdev->dev, &vop_component_ops);
 306
 307         return 0;
 308 }
 309
 310 static struct platform_driver vop_platform_driver = {
 311         .probe = vop_probe,
 312         .remove = vop_remove,
 313         .driver = {
 314                 .name = "rockchip-vop",
 315                 .owner = THIS_MODULE,
 316                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 317         },
 318 };
 319
 320 module_platform_driver(vop_platform_driver);
 321
 322 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 323 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 324 MODULE_LICENSE("GPL v2");