2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Fabien Dessenne <fabien.dessenne@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
9 #include <drm/drm_atomic.h>
10 #include <drm/drm_fb_cma_helper.h>
11 #include <drm/drm_gem_cma_helper.h>
13 #include "sti_compositor.h"
15 #include "sti_plane.h"
18 #define ALPHASWITCH BIT(6)
19 #define ENA_COLOR_FILL BIT(8)
20 #define BIGNOTLITTLE BIT(23)
21 #define WAIT_NEXT_VSYNC BIT(31)
23 /* GDP color formats */
24 #define GDP_RGB565 0x00
25 #define GDP_RGB888 0x01
26 #define GDP_RGB888_32 0x02
27 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
28 #define GDP_ARGB8565 0x04
29 #define GDP_ARGB8888 0x05
30 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
31 #define GDP_ARGB1555 0x06
32 #define GDP_ARGB4444 0x07
34 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
36 static struct gdp_format_to_str
{
39 } gdp_format_to_str
[] = {
51 #define GAM_GDP_CTL_OFFSET 0x00
52 #define GAM_GDP_AGC_OFFSET 0x04
53 #define GAM_GDP_VPO_OFFSET 0x0C
54 #define GAM_GDP_VPS_OFFSET 0x10
55 #define GAM_GDP_PML_OFFSET 0x14
56 #define GAM_GDP_PMP_OFFSET 0x18
57 #define GAM_GDP_SIZE_OFFSET 0x1C
58 #define GAM_GDP_NVN_OFFSET 0x24
59 #define GAM_GDP_KEY1_OFFSET 0x28
60 #define GAM_GDP_KEY2_OFFSET 0x2C
61 #define GAM_GDP_PPT_OFFSET 0x34
62 #define GAM_GDP_CML_OFFSET 0x3C
63 #define GAM_GDP_MST_OFFSET 0x68
65 #define GAM_GDP_ALPHARANGE_255 BIT(5)
66 #define GAM_GDP_AGC_FULL_RANGE 0x00808080
67 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
68 #define GAM_GDP_SIZE_MAX 0x7FF
70 #define GDP_NODE_NB_BANK 2
71 #define GDP_NODE_PER_FIELD 2
92 struct sti_gdp_node_list
{
93 struct sti_gdp_node
*top_field
;
94 dma_addr_t top_field_paddr
;
95 struct sti_gdp_node
*btm_field
;
96 dma_addr_t btm_field_paddr
;
102 * @sti_plane: sti_plane structure
103 * @dev: driver device
104 * @regs: gdp registers
105 * @clk_pix: pixel clock for the current gdp
106 * @clk_main_parent: gdp parent clock if main path used
107 * @clk_aux_parent: gdp parent clock if aux path used
108 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
109 * @is_curr_top: true if the current node processed is the top field
110 * @node_list: array of node list
111 * @vtg: registered vtg
114 struct sti_plane plane
;
118 struct clk
*clk_main_parent
;
119 struct clk
*clk_aux_parent
;
120 struct notifier_block vtg_field_nb
;
122 struct sti_gdp_node_list node_list
[GDP_NODE_NB_BANK
];
126 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
128 static const uint32_t gdp_supported_formats
[] = {
139 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
140 readl(gdp->regs + reg ## _OFFSET))
142 static void gdp_dbg_ctl(struct seq_file
*s
, int val
)
146 seq_puts(s
, "\tColor:");
147 for (i
= 0; i
< ARRAY_SIZE(gdp_format_to_str
); i
++) {
148 if (gdp_format_to_str
[i
].format
== (val
& 0x1F)) {
149 seq_printf(s
, gdp_format_to_str
[i
].name
);
153 if (i
== ARRAY_SIZE(gdp_format_to_str
))
154 seq_puts(s
, "<UNKNOWN>");
156 seq_printf(s
, "\tWaitNextVsync:%d", val
& WAIT_NEXT_VSYNC
? 1 : 0);
159 static void gdp_dbg_vpo(struct seq_file
*s
, int val
)
161 seq_printf(s
, "\txdo:%4d\tydo:%4d", val
& 0xFFFF, (val
>> 16) & 0xFFFF);
164 static void gdp_dbg_vps(struct seq_file
*s
, int val
)
166 seq_printf(s
, "\txds:%4d\tyds:%4d", val
& 0xFFFF, (val
>> 16) & 0xFFFF);
169 static void gdp_dbg_size(struct seq_file
*s
, int val
)
171 seq_printf(s
, "\t%d x %d", val
& 0xFFFF, (val
>> 16) & 0xFFFF);
174 static void gdp_dbg_nvn(struct seq_file
*s
, struct sti_gdp
*gdp
, int val
)
179 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++) {
180 if (gdp
->node_list
[i
].top_field_paddr
== val
) {
181 base
= gdp
->node_list
[i
].top_field
;
184 if (gdp
->node_list
[i
].btm_field_paddr
== val
) {
185 base
= gdp
->node_list
[i
].btm_field
;
191 seq_printf(s
, "\tVirt @: %p", base
);
194 static void gdp_dbg_ppt(struct seq_file
*s
, int val
)
196 if (val
& GAM_GDP_PPT_IGNORE
)
197 seq_puts(s
, "\tNot displayed on mixer!");
200 static void gdp_dbg_mst(struct seq_file
*s
, int val
)
203 seq_puts(s
, "\tBUFFER UNDERFLOW!");
206 static int gdp_dbg_show(struct seq_file
*s
, void *data
)
208 struct drm_info_node
*node
= s
->private;
209 struct sti_gdp
*gdp
= (struct sti_gdp
*)node
->info_ent
->data
;
210 struct drm_device
*dev
= node
->minor
->dev
;
211 struct drm_plane
*drm_plane
= &gdp
->plane
.drm_plane
;
212 struct drm_crtc
*crtc
= drm_plane
->crtc
;
215 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
219 seq_printf(s
, "%s: (vaddr = 0x%p)",
220 sti_plane_to_str(&gdp
->plane
), gdp
->regs
);
222 DBGFS_DUMP(GAM_GDP_CTL
);
223 gdp_dbg_ctl(s
, readl(gdp
->regs
+ GAM_GDP_CTL_OFFSET
));
224 DBGFS_DUMP(GAM_GDP_AGC
);
225 DBGFS_DUMP(GAM_GDP_VPO
);
226 gdp_dbg_vpo(s
, readl(gdp
->regs
+ GAM_GDP_VPO_OFFSET
));
227 DBGFS_DUMP(GAM_GDP_VPS
);
228 gdp_dbg_vps(s
, readl(gdp
->regs
+ GAM_GDP_VPS_OFFSET
));
229 DBGFS_DUMP(GAM_GDP_PML
);
230 DBGFS_DUMP(GAM_GDP_PMP
);
231 DBGFS_DUMP(GAM_GDP_SIZE
);
232 gdp_dbg_size(s
, readl(gdp
->regs
+ GAM_GDP_SIZE_OFFSET
));
233 DBGFS_DUMP(GAM_GDP_NVN
);
234 gdp_dbg_nvn(s
, gdp
, readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
));
235 DBGFS_DUMP(GAM_GDP_KEY1
);
236 DBGFS_DUMP(GAM_GDP_KEY2
);
237 DBGFS_DUMP(GAM_GDP_PPT
);
238 gdp_dbg_ppt(s
, readl(gdp
->regs
+ GAM_GDP_PPT_OFFSET
));
239 DBGFS_DUMP(GAM_GDP_CML
);
240 DBGFS_DUMP(GAM_GDP_MST
);
241 gdp_dbg_mst(s
, readl(gdp
->regs
+ GAM_GDP_MST_OFFSET
));
245 seq_puts(s
, " Not connected to any DRM CRTC\n");
247 seq_printf(s
, " Connected to DRM CRTC #%d (%s)\n",
248 crtc
->base
.id
, sti_mixer_to_str(to_sti_mixer(crtc
)));
250 mutex_unlock(&dev
->struct_mutex
);
254 static void gdp_node_dump_node(struct seq_file
*s
, struct sti_gdp_node
*node
)
256 seq_printf(s
, "\t@:0x%p", node
);
257 seq_printf(s
, "\n\tCTL 0x%08X", node
->gam_gdp_ctl
);
258 gdp_dbg_ctl(s
, node
->gam_gdp_ctl
);
259 seq_printf(s
, "\n\tAGC 0x%08X", node
->gam_gdp_agc
);
260 seq_printf(s
, "\n\tVPO 0x%08X", node
->gam_gdp_vpo
);
261 gdp_dbg_vpo(s
, node
->gam_gdp_vpo
);
262 seq_printf(s
, "\n\tVPS 0x%08X", node
->gam_gdp_vps
);
263 gdp_dbg_vps(s
, node
->gam_gdp_vps
);
264 seq_printf(s
, "\n\tPML 0x%08X", node
->gam_gdp_pml
);
265 seq_printf(s
, "\n\tPMP 0x%08X", node
->gam_gdp_pmp
);
266 seq_printf(s
, "\n\tSIZE 0x%08X", node
->gam_gdp_size
);
267 gdp_dbg_size(s
, node
->gam_gdp_size
);
268 seq_printf(s
, "\n\tNVN 0x%08X", node
->gam_gdp_nvn
);
269 seq_printf(s
, "\n\tKEY1 0x%08X", node
->gam_gdp_key1
);
270 seq_printf(s
, "\n\tKEY2 0x%08X", node
->gam_gdp_key2
);
271 seq_printf(s
, "\n\tPPT 0x%08X", node
->gam_gdp_ppt
);
272 gdp_dbg_ppt(s
, node
->gam_gdp_ppt
);
273 seq_printf(s
, "\n\tCML 0x%08X", node
->gam_gdp_cml
);
277 static int gdp_node_dbg_show(struct seq_file
*s
, void *arg
)
279 struct drm_info_node
*node
= s
->private;
280 struct sti_gdp
*gdp
= (struct sti_gdp
*)node
->info_ent
->data
;
281 struct drm_device
*dev
= node
->minor
->dev
;
285 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
289 for (b
= 0; b
< GDP_NODE_NB_BANK
; b
++) {
290 seq_printf(s
, "\n%s[%d].top", sti_plane_to_str(&gdp
->plane
), b
);
291 gdp_node_dump_node(s
, gdp
->node_list
[b
].top_field
);
292 seq_printf(s
, "\n%s[%d].btm", sti_plane_to_str(&gdp
->plane
), b
);
293 gdp_node_dump_node(s
, gdp
->node_list
[b
].btm_field
);
296 mutex_unlock(&dev
->struct_mutex
);
300 static struct drm_info_list gdp0_debugfs_files
[] = {
301 { "gdp0", gdp_dbg_show
, 0, NULL
},
302 { "gdp0_node", gdp_node_dbg_show
, 0, NULL
},
305 static struct drm_info_list gdp1_debugfs_files
[] = {
306 { "gdp1", gdp_dbg_show
, 0, NULL
},
307 { "gdp1_node", gdp_node_dbg_show
, 0, NULL
},
310 static struct drm_info_list gdp2_debugfs_files
[] = {
311 { "gdp2", gdp_dbg_show
, 0, NULL
},
312 { "gdp2_node", gdp_node_dbg_show
, 0, NULL
},
315 static struct drm_info_list gdp3_debugfs_files
[] = {
316 { "gdp3", gdp_dbg_show
, 0, NULL
},
317 { "gdp3_node", gdp_node_dbg_show
, 0, NULL
},
320 static int gdp_debugfs_init(struct sti_gdp
*gdp
, struct drm_minor
*minor
)
323 struct drm_info_list
*gdp_debugfs_files
;
326 switch (gdp
->plane
.desc
) {
328 gdp_debugfs_files
= gdp0_debugfs_files
;
329 nb_files
= ARRAY_SIZE(gdp0_debugfs_files
);
332 gdp_debugfs_files
= gdp1_debugfs_files
;
333 nb_files
= ARRAY_SIZE(gdp1_debugfs_files
);
336 gdp_debugfs_files
= gdp2_debugfs_files
;
337 nb_files
= ARRAY_SIZE(gdp2_debugfs_files
);
340 gdp_debugfs_files
= gdp3_debugfs_files
;
341 nb_files
= ARRAY_SIZE(gdp3_debugfs_files
);
347 for (i
= 0; i
< nb_files
; i
++)
348 gdp_debugfs_files
[i
].data
= gdp
;
350 return drm_debugfs_create_files(gdp_debugfs_files
,
352 minor
->debugfs_root
, minor
);
355 static int sti_gdp_fourcc2format(int fourcc
)
358 case DRM_FORMAT_XRGB8888
:
359 return GDP_RGB888_32
;
360 case DRM_FORMAT_XBGR8888
:
362 case DRM_FORMAT_ARGB8888
:
364 case DRM_FORMAT_ABGR8888
:
366 case DRM_FORMAT_ARGB4444
:
368 case DRM_FORMAT_ARGB1555
:
370 case DRM_FORMAT_RGB565
:
372 case DRM_FORMAT_RGB888
:
378 static int sti_gdp_get_alpharange(int format
)
384 return GAM_GDP_ALPHARANGE_255
;
390 * sti_gdp_get_free_nodes
393 * Look for a GDP node list that is not currently read by the HW.
396 * Pointer to the free GDP node list
398 static struct sti_gdp_node_list
*sti_gdp_get_free_nodes(struct sti_gdp
*gdp
)
403 hw_nvn
= readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
407 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++)
408 if ((hw_nvn
!= gdp
->node_list
[i
].btm_field_paddr
) &&
409 (hw_nvn
!= gdp
->node_list
[i
].top_field_paddr
))
410 return &gdp
->node_list
[i
];
412 /* in hazardious cases restart with the first node */
413 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
414 sti_plane_to_str(&gdp
->plane
), hw_nvn
);
417 return &gdp
->node_list
[0];
421 * sti_gdp_get_current_nodes
424 * Look for GDP nodes that are currently read by the HW.
427 * Pointer to the current GDP node list
430 struct sti_gdp_node_list
*sti_gdp_get_current_nodes(struct sti_gdp
*gdp
)
435 hw_nvn
= readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
439 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++)
440 if ((hw_nvn
== gdp
->node_list
[i
].btm_field_paddr
) ||
441 (hw_nvn
== gdp
->node_list
[i
].top_field_paddr
))
442 return &gdp
->node_list
[i
];
445 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
446 hw_nvn
, sti_plane_to_str(&gdp
->plane
));
457 static void sti_gdp_disable(struct sti_gdp
*gdp
)
461 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp
->plane
));
463 /* Set the nodes as 'to be ignored on mixer' */
464 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++) {
465 gdp
->node_list
[i
].top_field
->gam_gdp_ppt
|= GAM_GDP_PPT_IGNORE
;
466 gdp
->node_list
[i
].btm_field
->gam_gdp_ppt
|= GAM_GDP_PPT_IGNORE
;
469 if (sti_vtg_unregister_client(gdp
->vtg
, &gdp
->vtg_field_nb
))
470 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
473 clk_disable_unprepare(gdp
->clk_pix
);
475 gdp
->plane
.status
= STI_PLANE_DISABLED
;
480 * @nb: notifier block
481 * @event: event message
482 * @data: private data
484 * Handle VTG top field and bottom field event.
489 int sti_gdp_field_cb(struct notifier_block
*nb
,
490 unsigned long event
, void *data
)
492 struct sti_gdp
*gdp
= container_of(nb
, struct sti_gdp
, vtg_field_nb
);
494 if (gdp
->plane
.status
== STI_PLANE_FLUSHING
) {
495 /* disable need to be synchronize on vsync event */
496 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
497 sti_plane_to_str(&gdp
->plane
));
499 sti_gdp_disable(gdp
);
503 case VTG_TOP_FIELD_EVENT
:
504 gdp
->is_curr_top
= true;
506 case VTG_BOTTOM_FIELD_EVENT
:
507 gdp
->is_curr_top
= false;
510 DRM_ERROR("unsupported event: %lu\n", event
);
517 static void sti_gdp_init(struct sti_gdp
*gdp
)
519 struct device_node
*np
= gdp
->dev
->of_node
;
522 unsigned int i
, size
;
524 /* Allocate all the nodes within a single memory page */
525 size
= sizeof(struct sti_gdp_node
) *
526 GDP_NODE_PER_FIELD
* GDP_NODE_NB_BANK
;
527 base
= dma_alloc_wc(gdp
->dev
, size
, &dma_addr
, GFP_KERNEL
| GFP_DMA
);
530 DRM_ERROR("Failed to allocate memory for GDP node\n");
533 memset(base
, 0, size
);
535 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++) {
536 if (dma_addr
& 0xF) {
537 DRM_ERROR("Mem alignment failed\n");
540 gdp
->node_list
[i
].top_field
= base
;
541 gdp
->node_list
[i
].top_field_paddr
= dma_addr
;
543 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i
, base
);
544 base
+= sizeof(struct sti_gdp_node
);
545 dma_addr
+= sizeof(struct sti_gdp_node
);
547 if (dma_addr
& 0xF) {
548 DRM_ERROR("Mem alignment failed\n");
551 gdp
->node_list
[i
].btm_field
= base
;
552 gdp
->node_list
[i
].btm_field_paddr
= dma_addr
;
553 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i
, base
);
554 base
+= sizeof(struct sti_gdp_node
);
555 dma_addr
+= sizeof(struct sti_gdp_node
);
558 if (of_device_is_compatible(np
, "st,stih407-compositor")) {
559 /* GDP of STiH407 chip have its own pixel clock */
562 switch (gdp
->plane
.desc
) {
564 clk_name
= "pix_gdp1";
567 clk_name
= "pix_gdp2";
570 clk_name
= "pix_gdp3";
573 clk_name
= "pix_gdp4";
576 DRM_ERROR("GDP id not recognized\n");
580 gdp
->clk_pix
= devm_clk_get(gdp
->dev
, clk_name
);
581 if (IS_ERR(gdp
->clk_pix
))
582 DRM_ERROR("Cannot get %s clock\n", clk_name
);
584 gdp
->clk_main_parent
= devm_clk_get(gdp
->dev
, "main_parent");
585 if (IS_ERR(gdp
->clk_main_parent
))
586 DRM_ERROR("Cannot get main_parent clock\n");
588 gdp
->clk_aux_parent
= devm_clk_get(gdp
->dev
, "aux_parent");
589 if (IS_ERR(gdp
->clk_aux_parent
))
590 DRM_ERROR("Cannot get aux_parent clock\n");
597 * @dst: requested destination size
600 * Return the cropped / clamped destination size
603 * cropped / clamped destination size
605 static int sti_gdp_get_dst(struct device
*dev
, int dst
, int src
)
611 dev_dbg(dev
, "WARNING: GDP scale not supported, will crop\n");
615 dev_dbg(dev
, "WARNING: GDP scale not supported, will clamp\n");
619 static int sti_gdp_atomic_check(struct drm_plane
*drm_plane
,
620 struct drm_plane_state
*state
)
622 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
623 struct sti_gdp
*gdp
= to_sti_gdp(plane
);
624 struct drm_crtc
*crtc
= state
->crtc
;
625 struct sti_compositor
*compo
= dev_get_drvdata(gdp
->dev
);
626 struct drm_framebuffer
*fb
= state
->fb
;
627 bool first_prepare
= plane
->status
== STI_PLANE_DISABLED
? true : false;
628 struct drm_crtc_state
*crtc_state
;
629 struct sti_mixer
*mixer
;
630 struct drm_display_mode
*mode
;
631 int dst_x
, dst_y
, dst_w
, dst_h
;
632 int src_x
, src_y
, src_w
, src_h
;
635 /* no need for further checks if the plane is being disabled */
639 mixer
= to_sti_mixer(crtc
);
640 crtc_state
= drm_atomic_get_crtc_state(state
->state
, crtc
);
641 mode
= &crtc_state
->mode
;
642 dst_x
= state
->crtc_x
;
643 dst_y
= state
->crtc_y
;
644 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->crtc_hdisplay
- dst_x
);
645 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->crtc_vdisplay
- dst_y
);
646 /* src_x are in 16.16 format */
647 src_x
= state
->src_x
>> 16;
648 src_y
= state
->src_y
>> 16;
649 src_w
= clamp_val(state
->src_w
>> 16, 0, GAM_GDP_SIZE_MAX
);
650 src_h
= clamp_val(state
->src_h
>> 16, 0, GAM_GDP_SIZE_MAX
);
652 format
= sti_gdp_fourcc2format(fb
->pixel_format
);
654 DRM_ERROR("Format not supported by GDP %.4s\n",
655 (char *)&fb
->pixel_format
);
659 if (!drm_fb_cma_get_gem_obj(fb
, 0)) {
660 DRM_ERROR("Can't get CMA GEM object for fb\n");
665 /* Register gdp callback */
666 gdp
->vtg
= mixer
->id
== STI_MIXER_MAIN
?
667 compo
->vtg_main
: compo
->vtg_aux
;
668 if (sti_vtg_register_client(gdp
->vtg
,
669 &gdp
->vtg_field_nb
, crtc
)) {
670 DRM_ERROR("Cannot register VTG notifier\n");
674 /* Set and enable gdp clock */
677 int rate
= mode
->clock
* 1000;
681 * According to the mixer used, the gdp pixel clock
682 * should have a different parent clock.
684 if (mixer
->id
== STI_MIXER_MAIN
)
685 clkp
= gdp
->clk_main_parent
;
687 clkp
= gdp
->clk_aux_parent
;
690 clk_set_parent(gdp
->clk_pix
, clkp
);
692 res
= clk_set_rate(gdp
->clk_pix
, rate
);
694 DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
699 if (clk_prepare_enable(gdp
->clk_pix
)) {
700 DRM_ERROR("Failed to prepare/enable gdp\n");
706 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
707 crtc
->base
.id
, sti_mixer_to_str(mixer
),
708 drm_plane
->base
.id
, sti_plane_to_str(plane
));
709 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
710 sti_plane_to_str(plane
),
711 dst_w
, dst_h
, dst_x
, dst_y
,
712 src_w
, src_h
, src_x
, src_y
);
717 static void sti_gdp_atomic_update(struct drm_plane
*drm_plane
,
718 struct drm_plane_state
*oldstate
)
720 struct drm_plane_state
*state
= drm_plane
->state
;
721 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
722 struct sti_gdp
*gdp
= to_sti_gdp(plane
);
723 struct drm_crtc
*crtc
= state
->crtc
;
724 struct drm_framebuffer
*fb
= state
->fb
;
725 struct drm_display_mode
*mode
;
726 int dst_x
, dst_y
, dst_w
, dst_h
;
727 int src_x
, src_y
, src_w
, src_h
;
728 struct drm_gem_cma_object
*cma_obj
;
729 struct sti_gdp_node_list
*list
;
730 struct sti_gdp_node_list
*curr_list
;
731 struct sti_gdp_node
*top_field
, *btm_field
;
735 unsigned int depth
, bpp
;
736 u32 ydo
, xdo
, yds
, xds
;
742 dst_x
= state
->crtc_x
;
743 dst_y
= state
->crtc_y
;
744 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->crtc_hdisplay
- dst_x
);
745 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->crtc_vdisplay
- dst_y
);
746 /* src_x are in 16.16 format */
747 src_x
= state
->src_x
>> 16;
748 src_y
= state
->src_y
>> 16;
749 src_w
= clamp_val(state
->src_w
>> 16, 0, GAM_GDP_SIZE_MAX
);
750 src_h
= clamp_val(state
->src_h
>> 16, 0, GAM_GDP_SIZE_MAX
);
752 list
= sti_gdp_get_free_nodes(gdp
);
753 top_field
= list
->top_field
;
754 btm_field
= list
->btm_field
;
756 dev_dbg(gdp
->dev
, "%s %s top_node:0x%p btm_node:0x%p\n", __func__
,
757 sti_plane_to_str(plane
), top_field
, btm_field
);
759 /* build the top field */
760 top_field
->gam_gdp_agc
= GAM_GDP_AGC_FULL_RANGE
;
761 top_field
->gam_gdp_ctl
= WAIT_NEXT_VSYNC
;
762 format
= sti_gdp_fourcc2format(fb
->pixel_format
);
763 top_field
->gam_gdp_ctl
|= format
;
764 top_field
->gam_gdp_ctl
|= sti_gdp_get_alpharange(format
);
765 top_field
->gam_gdp_ppt
&= ~GAM_GDP_PPT_IGNORE
;
767 cma_obj
= drm_fb_cma_get_gem_obj(fb
, 0);
769 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb
->base
.id
,
770 (char *)&fb
->pixel_format
,
771 (unsigned long)cma_obj
->paddr
);
773 /* pixel memory location */
774 drm_fb_get_bpp_depth(fb
->pixel_format
, &depth
, &bpp
);
775 top_field
->gam_gdp_pml
= (u32
)cma_obj
->paddr
+ fb
->offsets
[0];
776 top_field
->gam_gdp_pml
+= src_x
* (bpp
>> 3);
777 top_field
->gam_gdp_pml
+= src_y
* fb
->pitches
[0];
779 /* output parameters (clamped / cropped) */
780 dst_w
= sti_gdp_get_dst(gdp
->dev
, dst_w
, src_w
);
781 dst_h
= sti_gdp_get_dst(gdp
->dev
, dst_h
, src_h
);
782 ydo
= sti_vtg_get_line_number(*mode
, dst_y
);
783 yds
= sti_vtg_get_line_number(*mode
, dst_y
+ dst_h
- 1);
784 xdo
= sti_vtg_get_pixel_number(*mode
, dst_x
);
785 xds
= sti_vtg_get_pixel_number(*mode
, dst_x
+ dst_w
- 1);
786 top_field
->gam_gdp_vpo
= (ydo
<< 16) | xdo
;
787 top_field
->gam_gdp_vps
= (yds
<< 16) | xds
;
789 /* input parameters */
791 top_field
->gam_gdp_pmp
= fb
->pitches
[0];
792 top_field
->gam_gdp_size
= src_h
<< 16 | src_w
;
794 /* Same content and chained together */
795 memcpy(btm_field
, top_field
, sizeof(*btm_field
));
796 top_field
->gam_gdp_nvn
= list
->btm_field_paddr
;
797 btm_field
->gam_gdp_nvn
= list
->top_field_paddr
;
799 /* Interlaced mode */
800 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
801 btm_field
->gam_gdp_pml
= top_field
->gam_gdp_pml
+
804 /* Update the NVN field of the 'right' field of the current GDP node
805 * (being used by the HW) with the address of the updated ('free') top
807 * - In interlaced mode the 'right' field is the bottom field as we
808 * update frames starting from their top field
809 * - In progressive mode, we update both bottom and top fields which
811 * At the next VSYNC, the updated node list will be used by the HW.
813 curr_list
= sti_gdp_get_current_nodes(gdp
);
814 dma_updated_top
= list
->top_field_paddr
;
815 dma_updated_btm
= list
->btm_field_paddr
;
817 dev_dbg(gdp
->dev
, "Current NVN:0x%X\n",
818 readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
));
819 dev_dbg(gdp
->dev
, "Posted buff: %lx current buff: %x\n",
820 (unsigned long)cma_obj
->paddr
,
821 readl(gdp
->regs
+ GAM_GDP_PML_OFFSET
));
824 /* First update or invalid node should directly write in the
826 DRM_DEBUG_DRIVER("%s first update (or invalid node)",
827 sti_plane_to_str(plane
));
829 writel(gdp
->is_curr_top
?
830 dma_updated_btm
: dma_updated_top
,
831 gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
835 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
836 if (gdp
->is_curr_top
) {
837 /* Do not update in the middle of the frame, but
838 * postpone the update after the bottom field has
840 curr_list
->btm_field
->gam_gdp_nvn
= dma_updated_top
;
842 /* Direct update to avoid one frame delay */
843 writel(dma_updated_top
,
844 gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
847 /* Direct update for progressive to avoid one frame delay */
848 writel(dma_updated_top
, gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
852 sti_plane_update_fps(plane
, true, false);
854 plane
->status
= STI_PLANE_UPDATED
;
857 static void sti_gdp_atomic_disable(struct drm_plane
*drm_plane
,
858 struct drm_plane_state
*oldstate
)
860 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
862 if (!drm_plane
->crtc
) {
863 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
868 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
869 drm_plane
->crtc
->base
.id
,
870 sti_mixer_to_str(to_sti_mixer(drm_plane
->crtc
)),
871 drm_plane
->base
.id
, sti_plane_to_str(plane
));
873 plane
->status
= STI_PLANE_DISABLING
;
876 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs
= {
877 .atomic_check
= sti_gdp_atomic_check
,
878 .atomic_update
= sti_gdp_atomic_update
,
879 .atomic_disable
= sti_gdp_atomic_disable
,
882 struct drm_plane
*sti_gdp_create(struct drm_device
*drm_dev
,
883 struct device
*dev
, int desc
,
884 void __iomem
*baseaddr
,
885 unsigned int possible_crtcs
,
886 enum drm_plane_type type
)
891 gdp
= devm_kzalloc(dev
, sizeof(*gdp
), GFP_KERNEL
);
893 DRM_ERROR("Failed to allocate memory for GDP\n");
898 gdp
->regs
= baseaddr
;
899 gdp
->plane
.desc
= desc
;
900 gdp
->plane
.status
= STI_PLANE_DISABLED
;
902 gdp
->vtg_field_nb
.notifier_call
= sti_gdp_field_cb
;
906 res
= drm_universal_plane_init(drm_dev
, &gdp
->plane
.drm_plane
,
908 &sti_plane_helpers_funcs
,
909 gdp_supported_formats
,
910 ARRAY_SIZE(gdp_supported_formats
),
913 DRM_ERROR("Failed to initialize universal plane\n");
917 drm_plane_helper_add(&gdp
->plane
.drm_plane
, &sti_gdp_helpers_funcs
);
919 sti_plane_init_property(&gdp
->plane
, type
);
921 if (gdp_debugfs_init(gdp
, drm_dev
->primary
))
922 DRM_ERROR("GDP debugfs setup failed\n");
924 return &gdp
->plane
.drm_plane
;
927 devm_kfree(dev
, gdp
);