2 * Copyright (C) STMicroelectronics SA 2014
3 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
8 #include <linux/component.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/seq_file.h>
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_crtc_helper.h>
17 /* HDformatter registers */
18 #define HDA_ANA_CFG 0x0000
19 #define HDA_ANA_SCALE_CTRL_Y 0x0004
20 #define HDA_ANA_SCALE_CTRL_CB 0x0008
21 #define HDA_ANA_SCALE_CTRL_CR 0x000C
22 #define HDA_ANA_ANC_CTRL 0x0010
23 #define HDA_ANA_SRC_Y_CFG 0x0014
24 #define HDA_COEFF_Y_PH1_TAP123 0x0018
25 #define HDA_COEFF_Y_PH1_TAP456 0x001C
26 #define HDA_COEFF_Y_PH2_TAP123 0x0020
27 #define HDA_COEFF_Y_PH2_TAP456 0x0024
28 #define HDA_COEFF_Y_PH3_TAP123 0x0028
29 #define HDA_COEFF_Y_PH3_TAP456 0x002C
30 #define HDA_COEFF_Y_PH4_TAP123 0x0030
31 #define HDA_COEFF_Y_PH4_TAP456 0x0034
32 #define HDA_ANA_SRC_C_CFG 0x0040
33 #define HDA_COEFF_C_PH1_TAP123 0x0044
34 #define HDA_COEFF_C_PH1_TAP456 0x0048
35 #define HDA_COEFF_C_PH2_TAP123 0x004C
36 #define HDA_COEFF_C_PH2_TAP456 0x0050
37 #define HDA_COEFF_C_PH3_TAP123 0x0054
38 #define HDA_COEFF_C_PH3_TAP456 0x0058
39 #define HDA_COEFF_C_PH4_TAP123 0x005C
40 #define HDA_COEFF_C_PH4_TAP456 0x0060
41 #define HDA_SYNC_AWGI 0x0300
44 #define CFG_AWG_ASYNC_EN BIT(0)
45 #define CFG_AWG_ASYNC_HSYNC_MTD BIT(1)
46 #define CFG_AWG_ASYNC_VSYNC_MTD BIT(2)
47 #define CFG_AWG_SYNC_DEL BIT(3)
48 #define CFG_AWG_FLTR_MODE_SHIFT 4
49 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT)
50 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT)
51 #define CFG_AWG_FLTR_MODE_ED (1 << CFG_AWG_FLTR_MODE_SHIFT)
52 #define CFG_AWG_FLTR_MODE_HD (2 << CFG_AWG_FLTR_MODE_SHIFT)
53 #define CFG_SYNC_ON_PBPR_MASK BIT(8)
54 #define CFG_PREFILTER_EN_MASK BIT(9)
55 #define CFG_PBPR_SYNC_OFF_SHIFT 16
56 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
57 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */
59 /* Default scaling values */
60 #define SCALE_CTRL_Y_DFLT 0x00C50256
61 #define SCALE_CTRL_CB_DFLT 0x00DB0249
62 #define SCALE_CTRL_CR_DFLT 0x00DB0249
64 /* Video DACs control */
65 #define VIDEO_DACS_CONTROL_MASK 0x0FFF
66 #define VIDEO_DACS_CONTROL_SYSCFG2535 0x085C /* for stih416 */
67 #define DAC_CFG_HD_OFF_SHIFT 5
68 #define DAC_CFG_HD_OFF_MASK (0x7 << DAC_CFG_HD_OFF_SHIFT)
69 #define VIDEO_DACS_CONTROL_SYSCFG5072 0x0120 /* for stih407 */
70 #define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1)
73 /* Upsampler values for the alternative 2X Filter */
74 #define SAMPLER_COEF_NB 8
75 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000
76 static u32 coef_y_alt_2x
[] = {
77 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
78 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
81 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004
82 static u32 coef_c_alt_2x
[] = {
83 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
84 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
87 /* Upsampler values for the 4X Filter */
88 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005
89 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004
90 static u32 coef_yc_4x
[] = {
91 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
92 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
95 /* AWG instructions for some video modes */
96 #define AWG_MAX_INST 64
99 static u32 AWGi_720p_50
[] = {
100 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
101 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
102 0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
103 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
104 0x00000104, 0x00001AE8
107 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50)
110 static u32 AWGi_720p_60
[] = {
111 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
112 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
113 0x00000C44, 0x00000104, 0x00001804, 0x00000971,
114 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
115 0x00000104, 0x00001AE8
118 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60)
121 static u32 AWGi_1080p_30
[] = {
122 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
123 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
124 0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
125 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
126 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
130 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30)
133 static u32 AWGi_1080p_25
[] = {
134 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
135 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
136 0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
137 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
138 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
142 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25)
145 static u32 AWGi_1080p_24
[] = {
146 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
147 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
148 0x00000E50, 0x00000104, 0x00001804, 0x00000971,
149 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
150 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
154 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24)
157 static u32 AWGi_720x480p_60
[] = {
158 0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
159 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
162 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60)
164 /* Video mode category */
165 enum sti_hda_vid_cat
{
172 struct sti_hda_video_config
{
173 struct drm_display_mode mode
;
176 enum sti_hda_vid_cat vid_cat
;
179 /* HD analog supported modes
180 * Interlaced modes may be added when supported by the whole display chain
182 static const struct sti_hda_video_config hda_supported_modes
[] = {
183 /* 1080p30 74.250Mhz */
184 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2008,
185 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
186 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
187 AWGi_1080p_30
, NN_1080p_30
, VID_HD_74M
},
188 /* 1080p30 74.176Mhz */
189 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74176, 1920, 2008,
190 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
191 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
192 AWGi_1080p_30
, NN_1080p_30
, VID_HD_74M
},
193 /* 1080p24 74.250Mhz */
194 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2558,
195 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
196 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
197 AWGi_1080p_24
, NN_1080p_24
, VID_HD_74M
},
198 /* 1080p24 74.176Mhz */
199 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74176, 1920, 2558,
200 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
201 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
202 AWGi_1080p_24
, NN_1080p_24
, VID_HD_74M
},
203 /* 1080p25 74.250Mhz */
204 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2448,
205 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
206 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
207 AWGi_1080p_25
, NN_1080p_25
, VID_HD_74M
},
208 /* 720p60 74.250Mhz */
209 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1390,
210 1430, 1650, 0, 720, 725, 730, 750, 0,
211 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
212 AWGi_720p_60
, NN_720p_60
, VID_HD_74M
},
213 /* 720p60 74.176Mhz */
214 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74176, 1280, 1390,
215 1430, 1650, 0, 720, 725, 730, 750, 0,
216 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
217 AWGi_720p_60
, NN_720p_60
, VID_HD_74M
},
218 /* 720p50 74.250Mhz */
219 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1720,
220 1760, 1980, 0, 720, 725, 730, 750, 0,
221 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
)},
222 AWGi_720p_50
, NN_720p_50
, VID_HD_74M
},
223 /* 720x480p60 27.027Mhz */
224 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 27027, 720, 736,
225 798, 858, 0, 480, 489, 495, 525, 0,
226 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
)},
227 AWGi_720x480p_60
, NN_720x480p_60
, VID_ED
},
228 /* 720x480p60 27.000Mhz */
229 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 27000, 720, 736,
230 798, 858, 0, 480, 489, 495, 525, 0,
231 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
)},
232 AWGi_720x480p_60
, NN_720x480p_60
, VID_ED
}
236 * STI hd analog structure
238 * @dev: driver device
239 * @drm_dev: pointer to drm device
240 * @mode: current display mode selected
241 * @regs: HD analog register
242 * @video_dacs_ctrl: video DACS control register
243 * @enabled: true if HD analog is enabled else false
247 struct drm_device
*drm_dev
;
248 struct drm_display_mode mode
;
250 void __iomem
*video_dacs_ctrl
;
252 struct clk
*clk_hddac
;
256 struct sti_hda_connector
{
257 struct drm_connector drm_connector
;
258 struct drm_encoder
*encoder
;
262 #define to_sti_hda_connector(x) \
263 container_of(x, struct sti_hda_connector, drm_connector)
265 static u32
hda_read(struct sti_hda
*hda
, int offset
)
267 return readl(hda
->regs
+ offset
);
270 static void hda_write(struct sti_hda
*hda
, u32 val
, int offset
)
272 writel(val
, hda
->regs
+ offset
);
276 * Search for a video mode in the supported modes table
278 * @mode: mode being searched
279 * @idx: index of the found mode
281 * Return true if mode is found
283 static bool hda_get_mode_idx(struct drm_display_mode mode
, int *idx
)
287 for (i
= 0; i
< ARRAY_SIZE(hda_supported_modes
); i
++)
288 if (drm_mode_equal(&hda_supported_modes
[i
].mode
, &mode
)) {
298 * @hda: pointer to HD analog structure
299 * @enable: true if HD DACS need to be enabled, else false
301 static void hda_enable_hd_dacs(struct sti_hda
*hda
, bool enable
)
305 if (hda
->video_dacs_ctrl
) {
308 switch ((u32
)hda
->video_dacs_ctrl
& VIDEO_DACS_CONTROL_MASK
) {
309 case VIDEO_DACS_CONTROL_SYSCFG2535
:
310 mask
= DAC_CFG_HD_OFF_MASK
;
312 case VIDEO_DACS_CONTROL_SYSCFG5072
:
313 mask
= DAC_CFG_HD_HZUVW_OFF_MASK
;
316 DRM_INFO("Video DACS control register not supported!");
320 val
= readl(hda
->video_dacs_ctrl
);
326 writel(val
, hda
->video_dacs_ctrl
);
330 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
331 readl(hda->regs + reg))
333 static void hda_dbg_cfg(struct seq_file
*s
, int val
)
335 seq_puts(s
, "\tAWG ");
336 seq_puts(s
, val
& CFG_AWG_ASYNC_EN
? "enabled" : "disabled");
339 static void hda_dbg_awg_microcode(struct seq_file
*s
, void __iomem
*reg
)
344 seq_puts(s
, " HDA AWG microcode:");
345 for (i
= 0; i
< AWG_MAX_INST
; i
++) {
347 seq_printf(s
, "\n %04X:", i
);
348 seq_printf(s
, " %04X", readl(reg
+ i
* 4));
352 static void hda_dbg_video_dacs_ctrl(struct seq_file
*s
, void __iomem
*reg
)
354 u32 val
= readl(reg
);
357 switch ((u32
)reg
& VIDEO_DACS_CONTROL_MASK
) {
358 case VIDEO_DACS_CONTROL_SYSCFG2535
:
359 mask
= DAC_CFG_HD_OFF_MASK
;
361 case VIDEO_DACS_CONTROL_SYSCFG5072
:
362 mask
= DAC_CFG_HD_HZUVW_OFF_MASK
;
365 DRM_DEBUG_DRIVER("Warning: DACS ctrl register not supported!");
370 seq_printf(s
, "\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val
);
371 seq_puts(s
, "\tHD DACs ");
372 seq_puts(s
, val
& mask
? "disabled" : "enabled");
375 static int hda_dbg_show(struct seq_file
*s
, void *data
)
377 struct drm_info_node
*node
= s
->private;
378 struct sti_hda
*hda
= (struct sti_hda
*)node
->info_ent
->data
;
379 struct drm_device
*dev
= node
->minor
->dev
;
382 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
386 seq_printf(s
, "HD Analog: (vaddr = 0x%p)", hda
->regs
);
387 DBGFS_DUMP(HDA_ANA_CFG
);
388 hda_dbg_cfg(s
, readl(hda
->regs
+ HDA_ANA_CFG
));
389 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y
);
390 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB
);
391 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR
);
392 DBGFS_DUMP(HDA_ANA_ANC_CTRL
);
393 DBGFS_DUMP(HDA_ANA_SRC_Y_CFG
);
394 DBGFS_DUMP(HDA_ANA_SRC_C_CFG
);
395 hda_dbg_awg_microcode(s
, hda
->regs
+ HDA_SYNC_AWGI
);
396 if (hda
->video_dacs_ctrl
)
397 hda_dbg_video_dacs_ctrl(s
, hda
->video_dacs_ctrl
);
400 mutex_unlock(&dev
->struct_mutex
);
404 static struct drm_info_list hda_debugfs_files
[] = {
405 { "hda", hda_dbg_show
, 0, NULL
},
408 static void hda_debugfs_exit(struct sti_hda
*hda
, struct drm_minor
*minor
)
410 drm_debugfs_remove_files(hda_debugfs_files
,
411 ARRAY_SIZE(hda_debugfs_files
),
415 static int hda_debugfs_init(struct sti_hda
*hda
, struct drm_minor
*minor
)
419 for (i
= 0; i
< ARRAY_SIZE(hda_debugfs_files
); i
++)
420 hda_debugfs_files
[i
].data
= hda
;
422 return drm_debugfs_create_files(hda_debugfs_files
,
423 ARRAY_SIZE(hda_debugfs_files
),
424 minor
->debugfs_root
, minor
);
428 * Configure AWG, writing instructions
430 * @hda: pointer to HD analog structure
431 * @awg_instr: pointer to AWG instructions table
432 * @nb: nb of AWG instructions
434 static void sti_hda_configure_awg(struct sti_hda
*hda
, u32
*awg_instr
, int nb
)
438 DRM_DEBUG_DRIVER("\n");
440 for (i
= 0; i
< nb
; i
++)
441 hda_write(hda
, awg_instr
[i
], HDA_SYNC_AWGI
+ i
* 4);
442 for (i
= nb
; i
< AWG_MAX_INST
; i
++)
443 hda_write(hda
, 0, HDA_SYNC_AWGI
+ i
* 4);
446 static void sti_hda_disable(struct drm_bridge
*bridge
)
448 struct sti_hda
*hda
= bridge
->driver_private
;
454 DRM_DEBUG_DRIVER("\n");
456 /* Disable HD DAC and AWG */
457 val
= hda_read(hda
, HDA_ANA_CFG
);
458 val
&= ~CFG_AWG_ASYNC_EN
;
459 hda_write(hda
, val
, HDA_ANA_CFG
);
460 hda_write(hda
, 0, HDA_ANA_ANC_CTRL
);
462 hda_enable_hd_dacs(hda
, false);
464 /* Disable/unprepare hda clock */
465 clk_disable_unprepare(hda
->clk_hddac
);
466 clk_disable_unprepare(hda
->clk_pix
);
468 hda
->enabled
= false;
471 static void sti_hda_pre_enable(struct drm_bridge
*bridge
)
473 struct sti_hda
*hda
= bridge
->driver_private
;
474 u32 val
, i
, mode_idx
;
475 u32 src_filter_y
, src_filter_c
;
476 u32
*coef_y
, *coef_c
;
479 DRM_DEBUG_DRIVER("\n");
484 /* Prepare/enable clocks */
485 if (clk_prepare_enable(hda
->clk_pix
))
486 DRM_ERROR("Failed to prepare/enable hda_pix clk\n");
487 if (clk_prepare_enable(hda
->clk_hddac
))
488 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n");
490 if (!hda_get_mode_idx(hda
->mode
, &mode_idx
)) {
491 DRM_ERROR("Undefined mode\n");
495 switch (hda_supported_modes
[mode_idx
].vid_cat
) {
497 DRM_ERROR("Beyond HD analog capabilities\n");
500 /* HD use alternate 2x filter */
501 filter_mode
= CFG_AWG_FLTR_MODE_HD
;
502 src_filter_y
= HDA_ANA_SRC_Y_CFG_ALT_2X
;
503 src_filter_c
= HDA_ANA_SRC_C_CFG_ALT_2X
;
504 coef_y
= coef_y_alt_2x
;
505 coef_c
= coef_c_alt_2x
;
508 /* ED uses 4x filter */
509 filter_mode
= CFG_AWG_FLTR_MODE_ED
;
510 src_filter_y
= HDA_ANA_SRC_Y_CFG_4X
;
511 src_filter_c
= HDA_ANA_SRC_C_CFG_4X
;
516 DRM_ERROR("Not supported\n");
519 DRM_ERROR("Undefined resolution\n");
522 DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx
);
524 /* Enable HD Video DACs */
525 hda_enable_hd_dacs(hda
, true);
527 /* Configure scaler */
528 hda_write(hda
, SCALE_CTRL_Y_DFLT
, HDA_ANA_SCALE_CTRL_Y
);
529 hda_write(hda
, SCALE_CTRL_CB_DFLT
, HDA_ANA_SCALE_CTRL_CB
);
530 hda_write(hda
, SCALE_CTRL_CR_DFLT
, HDA_ANA_SCALE_CTRL_CR
);
532 /* Configure sampler */
533 hda_write(hda
, src_filter_y
, HDA_ANA_SRC_Y_CFG
);
534 hda_write(hda
, src_filter_c
, HDA_ANA_SRC_C_CFG
);
535 for (i
= 0; i
< SAMPLER_COEF_NB
; i
++) {
536 hda_write(hda
, coef_y
[i
], HDA_COEFF_Y_PH1_TAP123
+ i
* 4);
537 hda_write(hda
, coef_c
[i
], HDA_COEFF_C_PH1_TAP123
+ i
* 4);
540 /* Configure main HDFormatter */
542 val
|= (hda
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ?
543 0 : CFG_AWG_ASYNC_VSYNC_MTD
;
544 val
|= (CFG_PBPR_SYNC_OFF_VAL
<< CFG_PBPR_SYNC_OFF_SHIFT
);
546 hda_write(hda
, val
, HDA_ANA_CFG
);
549 sti_hda_configure_awg(hda
, hda_supported_modes
[mode_idx
].awg_instr
,
550 hda_supported_modes
[mode_idx
].nb_instr
);
553 val
= hda_read(hda
, HDA_ANA_CFG
);
554 val
|= CFG_AWG_ASYNC_EN
;
555 hda_write(hda
, val
, HDA_ANA_CFG
);
560 static void sti_hda_set_mode(struct drm_bridge
*bridge
,
561 struct drm_display_mode
*mode
,
562 struct drm_display_mode
*adjusted_mode
)
564 struct sti_hda
*hda
= bridge
->driver_private
;
569 DRM_DEBUG_DRIVER("\n");
571 memcpy(&hda
->mode
, mode
, sizeof(struct drm_display_mode
));
573 if (!hda_get_mode_idx(hda
->mode
, &mode_idx
)) {
574 DRM_ERROR("Undefined mode\n");
578 switch (hda_supported_modes
[mode_idx
].vid_cat
) {
580 /* HD use alternate 2x filter */
581 hddac_rate
= mode
->clock
* 1000 * 2;
584 /* ED uses 4x filter */
585 hddac_rate
= mode
->clock
* 1000 * 4;
588 DRM_ERROR("Undefined mode\n");
592 /* HD DAC = 148.5Mhz or 108 Mhz */
593 ret
= clk_set_rate(hda
->clk_hddac
, hddac_rate
);
595 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n",
598 /* HDformatter clock = compositor clock */
599 ret
= clk_set_rate(hda
->clk_pix
, mode
->clock
* 1000);
601 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n",
605 static void sti_hda_bridge_nope(struct drm_bridge
*bridge
)
610 static const struct drm_bridge_funcs sti_hda_bridge_funcs
= {
611 .pre_enable
= sti_hda_pre_enable
,
612 .enable
= sti_hda_bridge_nope
,
613 .disable
= sti_hda_disable
,
614 .post_disable
= sti_hda_bridge_nope
,
615 .mode_set
= sti_hda_set_mode
,
618 static int sti_hda_connector_get_modes(struct drm_connector
*connector
)
622 struct sti_hda_connector
*hda_connector
623 = to_sti_hda_connector(connector
);
624 struct sti_hda
*hda
= hda_connector
->hda
;
626 DRM_DEBUG_DRIVER("\n");
628 for (i
= 0; i
< ARRAY_SIZE(hda_supported_modes
); i
++) {
629 struct drm_display_mode
*mode
=
630 drm_mode_duplicate(hda
->drm_dev
,
631 &hda_supported_modes
[i
].mode
);
634 mode
->vrefresh
= drm_mode_vrefresh(mode
);
636 /* the first mode is the preferred mode */
638 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
640 drm_mode_probed_add(connector
, mode
);
647 #define CLK_TOLERANCE_HZ 50
649 static int sti_hda_connector_mode_valid(struct drm_connector
*connector
,
650 struct drm_display_mode
*mode
)
652 int target
= mode
->clock
* 1000;
653 int target_min
= target
- CLK_TOLERANCE_HZ
;
654 int target_max
= target
+ CLK_TOLERANCE_HZ
;
657 struct sti_hda_connector
*hda_connector
658 = to_sti_hda_connector(connector
);
659 struct sti_hda
*hda
= hda_connector
->hda
;
661 if (!hda_get_mode_idx(*mode
, &idx
)) {
664 result
= clk_round_rate(hda
->clk_pix
, target
);
666 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
669 if ((result
< target_min
) || (result
> target_max
)) {
670 DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n",
679 struct drm_encoder
*sti_hda_best_encoder(struct drm_connector
*connector
)
681 struct sti_hda_connector
*hda_connector
682 = to_sti_hda_connector(connector
);
684 /* Best encoder is the one associated during connector creation */
685 return hda_connector
->encoder
;
689 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs
= {
690 .get_modes
= sti_hda_connector_get_modes
,
691 .mode_valid
= sti_hda_connector_mode_valid
,
692 .best_encoder
= sti_hda_best_encoder
,
695 static enum drm_connector_status
696 sti_hda_connector_detect(struct drm_connector
*connector
, bool force
)
698 return connector_status_connected
;
701 static void sti_hda_connector_destroy(struct drm_connector
*connector
)
703 struct sti_hda_connector
*hda_connector
704 = to_sti_hda_connector(connector
);
706 drm_connector_unregister(connector
);
707 drm_connector_cleanup(connector
);
708 kfree(hda_connector
);
711 static const struct drm_connector_funcs sti_hda_connector_funcs
= {
712 .dpms
= drm_atomic_helper_connector_dpms
,
713 .fill_modes
= drm_helper_probe_single_connector_modes
,
714 .detect
= sti_hda_connector_detect
,
715 .destroy
= sti_hda_connector_destroy
,
716 .reset
= drm_atomic_helper_connector_reset
,
717 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
718 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
721 static struct drm_encoder
*sti_hda_find_encoder(struct drm_device
*dev
)
723 struct drm_encoder
*encoder
;
725 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
726 if (encoder
->encoder_type
== DRM_MODE_ENCODER_DAC
)
733 static int sti_hda_bind(struct device
*dev
, struct device
*master
, void *data
)
735 struct sti_hda
*hda
= dev_get_drvdata(dev
);
736 struct drm_device
*drm_dev
= data
;
737 struct drm_encoder
*encoder
;
738 struct sti_hda_connector
*connector
;
739 struct drm_connector
*drm_connector
;
740 struct drm_bridge
*bridge
;
743 /* Set the drm device handle */
744 hda
->drm_dev
= drm_dev
;
746 encoder
= sti_hda_find_encoder(drm_dev
);
750 connector
= devm_kzalloc(dev
, sizeof(*connector
), GFP_KERNEL
);
754 connector
->hda
= hda
;
756 bridge
= devm_kzalloc(dev
, sizeof(*bridge
), GFP_KERNEL
);
760 bridge
->driver_private
= hda
;
761 bridge
->funcs
= &sti_hda_bridge_funcs
;
762 drm_bridge_attach(drm_dev
, bridge
);
764 encoder
->bridge
= bridge
;
765 connector
->encoder
= encoder
;
767 drm_connector
= (struct drm_connector
*)connector
;
769 drm_connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
771 drm_connector_init(drm_dev
, drm_connector
,
772 &sti_hda_connector_funcs
, DRM_MODE_CONNECTOR_Component
);
773 drm_connector_helper_add(drm_connector
,
774 &sti_hda_connector_helper_funcs
);
776 err
= drm_connector_register(drm_connector
);
780 err
= drm_mode_connector_attach_encoder(drm_connector
, encoder
);
782 DRM_ERROR("Failed to attach a connector to a encoder\n");
786 /* force to disable hd dacs at startup */
787 hda_enable_hd_dacs(hda
, false);
789 if (hda_debugfs_init(hda
, drm_dev
->primary
))
790 DRM_ERROR("HDA debugfs setup failed\n");
795 drm_connector_unregister(drm_connector
);
797 drm_connector_cleanup(drm_connector
);
801 static void sti_hda_unbind(struct device
*dev
,
802 struct device
*master
, void *data
)
804 struct sti_hda
*hda
= dev_get_drvdata(dev
);
805 struct drm_device
*drm_dev
= data
;
807 hda_debugfs_exit(hda
, drm_dev
->primary
);
810 static const struct component_ops sti_hda_ops
= {
811 .bind
= sti_hda_bind
,
812 .unbind
= sti_hda_unbind
,
815 static int sti_hda_probe(struct platform_device
*pdev
)
817 struct device
*dev
= &pdev
->dev
;
819 struct resource
*res
;
821 DRM_INFO("%s\n", __func__
);
823 hda
= devm_kzalloc(dev
, sizeof(*hda
), GFP_KERNEL
);
827 hda
->dev
= pdev
->dev
;
830 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "hda-reg");
832 DRM_ERROR("Invalid hda resource\n");
835 hda
->regs
= devm_ioremap_nocache(dev
, res
->start
, resource_size(res
));
839 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
842 hda
->video_dacs_ctrl
= devm_ioremap_nocache(dev
, res
->start
,
844 if (!hda
->video_dacs_ctrl
)
847 /* If no existing video-dacs-ctrl resource continue the probe */
848 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n");
849 hda
->video_dacs_ctrl
= NULL
;
852 /* Get clock resources */
853 hda
->clk_pix
= devm_clk_get(dev
, "pix");
854 if (IS_ERR(hda
->clk_pix
)) {
855 DRM_ERROR("Cannot get hda_pix clock\n");
856 return PTR_ERR(hda
->clk_pix
);
859 hda
->clk_hddac
= devm_clk_get(dev
, "hddac");
860 if (IS_ERR(hda
->clk_hddac
)) {
861 DRM_ERROR("Cannot get hda_hddac clock\n");
862 return PTR_ERR(hda
->clk_hddac
);
865 platform_set_drvdata(pdev
, hda
);
867 return component_add(&pdev
->dev
, &sti_hda_ops
);
870 static int sti_hda_remove(struct platform_device
*pdev
)
872 component_del(&pdev
->dev
, &sti_hda_ops
);
876 static const struct of_device_id hda_of_match
[] = {
877 { .compatible
= "st,stih416-hda", },
878 { .compatible
= "st,stih407-hda", },
881 MODULE_DEVICE_TABLE(of
, hda_of_match
);
883 struct platform_driver sti_hda_driver
= {
886 .owner
= THIS_MODULE
,
887 .of_match_table
= hda_of_match
,
889 .probe
= sti_hda_probe
,
890 .remove
= sti_hda_remove
,
893 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
894 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
895 MODULE_LICENSE("GPL");