2 * Copyright (C) 2016 Free Electrons
3 * Copyright (C) 2016 NextThing Co
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
16 #include "sun4i_tcon.h"
17 #include "sun4i_dotclock.h"
21 struct regmap
*regmap
;
24 static inline struct sun4i_dclk
*hw_to_dclk(struct clk_hw
*hw
)
26 return container_of(hw
, struct sun4i_dclk
, hw
);
29 static void sun4i_dclk_disable(struct clk_hw
*hw
)
31 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
33 regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
,
34 BIT(SUN4I_TCON0_DCLK_GATE_BIT
), 0);
37 static int sun4i_dclk_enable(struct clk_hw
*hw
)
39 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
41 return regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
,
42 BIT(SUN4I_TCON0_DCLK_GATE_BIT
),
43 BIT(SUN4I_TCON0_DCLK_GATE_BIT
));
46 static int sun4i_dclk_is_enabled(struct clk_hw
*hw
)
48 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
51 regmap_read(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
, &val
);
53 return val
& BIT(SUN4I_TCON0_DCLK_GATE_BIT
);
56 static unsigned long sun4i_dclk_recalc_rate(struct clk_hw
*hw
,
57 unsigned long parent_rate
)
59 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
62 regmap_read(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
, &val
);
64 val
>>= SUN4I_TCON0_DCLK_DIV_SHIFT
;
65 val
&= SUN4I_TCON0_DCLK_DIV_WIDTH
;
70 return parent_rate
/ val
;
73 static long sun4i_dclk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
74 unsigned long *parent_rate
)
76 unsigned long best_parent
= 0;
80 for (i
= 6; i
< 127; i
++) {
81 unsigned long ideal
= rate
* i
;
82 unsigned long rounded
;
84 rounded
= clk_hw_round_rate(clk_hw_get_parent(hw
),
87 if (rounded
== ideal
) {
88 best_parent
= rounded
;
93 if ((rounded
< ideal
) && (rounded
> best_parent
)) {
94 best_parent
= rounded
;
100 *parent_rate
= best_parent
;
102 return best_parent
/ best_div
;
105 static int sun4i_dclk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
106 unsigned long parent_rate
)
108 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
109 u8 div
= parent_rate
/ rate
;
111 return regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
,
115 static int sun4i_dclk_get_phase(struct clk_hw
*hw
)
117 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
120 regmap_read(dclk
->regmap
, SUN4I_TCON0_IO_POL_REG
, &val
);
128 static int sun4i_dclk_set_phase(struct clk_hw
*hw
, int degrees
)
130 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
132 regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_IO_POL_REG
,
139 static const struct clk_ops sun4i_dclk_ops
= {
140 .disable
= sun4i_dclk_disable
,
141 .enable
= sun4i_dclk_enable
,
142 .is_enabled
= sun4i_dclk_is_enabled
,
144 .recalc_rate
= sun4i_dclk_recalc_rate
,
145 .round_rate
= sun4i_dclk_round_rate
,
146 .set_rate
= sun4i_dclk_set_rate
,
148 .get_phase
= sun4i_dclk_get_phase
,
149 .set_phase
= sun4i_dclk_set_phase
,
152 int sun4i_dclk_create(struct device
*dev
, struct sun4i_tcon
*tcon
)
154 const char *clk_name
, *parent_name
;
155 struct clk_init_data init
;
156 struct sun4i_dclk
*dclk
;
159 parent_name
= __clk_get_name(tcon
->sclk0
);
160 ret
= of_property_read_string_index(dev
->of_node
,
161 "clock-output-names", 0,
166 dclk
= devm_kzalloc(dev
, sizeof(*dclk
), GFP_KERNEL
);
170 init
.name
= clk_name
;
171 init
.ops
= &sun4i_dclk_ops
;
172 init
.parent_names
= &parent_name
;
173 init
.num_parents
= 1;
174 init
.flags
= CLK_SET_RATE_PARENT
;
176 dclk
->regmap
= tcon
->regs
;
177 dclk
->hw
.init
= &init
;
179 tcon
->dclk
= clk_register(dev
, &dclk
->hw
);
180 if (IS_ERR(tcon
->dclk
))
181 return PTR_ERR(tcon
->dclk
);
185 EXPORT_SYMBOL(sun4i_dclk_create
);
187 int sun4i_dclk_free(struct sun4i_tcon
*tcon
)
189 clk_unregister(tcon
->dclk
);
192 EXPORT_SYMBOL(sun4i_dclk_free
);