2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/reset.h>
18 struct tegra_dc_soc_info
{
19 bool supports_interlacing
;
23 struct drm_plane base
;
27 static inline struct tegra_plane
*to_tegra_plane(struct drm_plane
*plane
)
29 return container_of(plane
, struct tegra_plane
, base
);
32 static unsigned int tegra_dc_format(uint32_t format
, uint32_t *swap
)
34 /* assume no swapping of fetched data */
36 *swap
= BYTE_SWAP_NOSWAP
;
39 case DRM_FORMAT_XBGR8888
:
40 return WIN_COLOR_DEPTH_R8G8B8A8
;
42 case DRM_FORMAT_XRGB8888
:
43 return WIN_COLOR_DEPTH_B8G8R8A8
;
45 case DRM_FORMAT_RGB565
:
46 return WIN_COLOR_DEPTH_B5G6R5
;
49 return WIN_COLOR_DEPTH_YCbCr422
;
53 *swap
= BYTE_SWAP_SWAP2
;
55 return WIN_COLOR_DEPTH_YCbCr422
;
57 case DRM_FORMAT_YUV420
:
58 return WIN_COLOR_DEPTH_YCbCr420P
;
60 case DRM_FORMAT_YUV422
:
61 return WIN_COLOR_DEPTH_YCbCr422P
;
67 WARN(1, "unsupported pixel format %u, using default\n", format
);
68 return WIN_COLOR_DEPTH_B8G8R8A8
;
71 static bool tegra_dc_format_is_yuv(unsigned int format
, bool *planar
)
74 case WIN_COLOR_DEPTH_YCbCr422
:
75 case WIN_COLOR_DEPTH_YUV422
:
81 case WIN_COLOR_DEPTH_YCbCr420P
:
82 case WIN_COLOR_DEPTH_YUV420P
:
83 case WIN_COLOR_DEPTH_YCbCr422P
:
84 case WIN_COLOR_DEPTH_YUV422P
:
85 case WIN_COLOR_DEPTH_YCbCr422R
:
86 case WIN_COLOR_DEPTH_YUV422R
:
87 case WIN_COLOR_DEPTH_YCbCr422RA
:
88 case WIN_COLOR_DEPTH_YUV422RA
:
98 static inline u32
compute_dda_inc(unsigned int in
, unsigned int out
, bool v
,
101 fixed20_12 outf
= dfixed_init(out
);
102 fixed20_12 inf
= dfixed_init(in
);
123 outf
.full
= max_t(u32
, outf
.full
- dfixed_const(1), dfixed_const(1));
124 inf
.full
-= dfixed_const(1);
126 dda_inc
= dfixed_div(inf
, outf
);
127 dda_inc
= min_t(u32
, dda_inc
, dfixed_const(max
));
132 static inline u32
compute_initial_dda(unsigned int in
)
134 fixed20_12 inf
= dfixed_init(in
);
135 return dfixed_frac(inf
);
138 static int tegra_dc_setup_window(struct tegra_dc
*dc
, unsigned int index
,
139 const struct tegra_dc_window
*window
)
141 unsigned h_offset
, v_offset
, h_size
, v_size
, h_dda
, v_dda
, bpp
;
146 * For YUV planar modes, the number of bytes per pixel takes into
147 * account only the luma component and therefore is 1.
149 yuv
= tegra_dc_format_is_yuv(window
->format
, &planar
);
151 bpp
= window
->bits_per_pixel
/ 8;
153 bpp
= planar
? 1 : 2;
155 value
= WINDOW_A_SELECT
<< index
;
156 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
158 tegra_dc_writel(dc
, window
->format
, DC_WIN_COLOR_DEPTH
);
159 tegra_dc_writel(dc
, window
->swap
, DC_WIN_BYTE_SWAP
);
161 value
= V_POSITION(window
->dst
.y
) | H_POSITION(window
->dst
.x
);
162 tegra_dc_writel(dc
, value
, DC_WIN_POSITION
);
164 value
= V_SIZE(window
->dst
.h
) | H_SIZE(window
->dst
.w
);
165 tegra_dc_writel(dc
, value
, DC_WIN_SIZE
);
167 h_offset
= window
->src
.x
* bpp
;
168 v_offset
= window
->src
.y
;
169 h_size
= window
->src
.w
* bpp
;
170 v_size
= window
->src
.h
;
172 value
= V_PRESCALED_SIZE(v_size
) | H_PRESCALED_SIZE(h_size
);
173 tegra_dc_writel(dc
, value
, DC_WIN_PRESCALED_SIZE
);
176 * For DDA computations the number of bytes per pixel for YUV planar
177 * modes needs to take into account all Y, U and V components.
182 h_dda
= compute_dda_inc(window
->src
.w
, window
->dst
.w
, false, bpp
);
183 v_dda
= compute_dda_inc(window
->src
.h
, window
->dst
.h
, true, bpp
);
185 value
= V_DDA_INC(v_dda
) | H_DDA_INC(h_dda
);
186 tegra_dc_writel(dc
, value
, DC_WIN_DDA_INC
);
188 h_dda
= compute_initial_dda(window
->src
.x
);
189 v_dda
= compute_initial_dda(window
->src
.y
);
191 tegra_dc_writel(dc
, h_dda
, DC_WIN_H_INITIAL_DDA
);
192 tegra_dc_writel(dc
, v_dda
, DC_WIN_V_INITIAL_DDA
);
194 tegra_dc_writel(dc
, 0, DC_WIN_UV_BUF_STRIDE
);
195 tegra_dc_writel(dc
, 0, DC_WIN_BUF_STRIDE
);
197 tegra_dc_writel(dc
, window
->base
[0], DC_WINBUF_START_ADDR
);
200 tegra_dc_writel(dc
, window
->base
[1], DC_WINBUF_START_ADDR_U
);
201 tegra_dc_writel(dc
, window
->base
[2], DC_WINBUF_START_ADDR_V
);
202 value
= window
->stride
[1] << 16 | window
->stride
[0];
203 tegra_dc_writel(dc
, value
, DC_WIN_LINE_STRIDE
);
205 tegra_dc_writel(dc
, window
->stride
[0], DC_WIN_LINE_STRIDE
);
208 if (window
->bottom_up
)
209 v_offset
+= window
->src
.h
- 1;
211 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
212 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
215 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
216 DC_WIN_BUFFER_ADDR_MODE_TILE
;
218 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
219 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
222 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
227 /* setup default colorspace conversion coefficients */
228 tegra_dc_writel(dc
, 0x00f0, DC_WIN_CSC_YOF
);
229 tegra_dc_writel(dc
, 0x012a, DC_WIN_CSC_KYRGB
);
230 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KUR
);
231 tegra_dc_writel(dc
, 0x0198, DC_WIN_CSC_KVR
);
232 tegra_dc_writel(dc
, 0x039b, DC_WIN_CSC_KUG
);
233 tegra_dc_writel(dc
, 0x032f, DC_WIN_CSC_KVG
);
234 tegra_dc_writel(dc
, 0x0204, DC_WIN_CSC_KUB
);
235 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KVB
);
238 } else if (window
->bits_per_pixel
< 24) {
239 value
|= COLOR_EXPAND
;
242 if (window
->bottom_up
)
243 value
|= V_DIRECTION
;
245 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
248 * Disable blending and assume Window A is the bottom-most window,
249 * Window C is the top-most window and Window B is in the middle.
251 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_NOKEY
);
252 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_1WIN
);
256 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_X
);
257 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
258 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
262 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
263 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
264 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
268 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
269 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_Y
);
270 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_3WIN_XY
);
274 tegra_dc_writel(dc
, WIN_A_UPDATE
<< index
, DC_CMD_STATE_CONTROL
);
275 tegra_dc_writel(dc
, WIN_A_ACT_REQ
<< index
, DC_CMD_STATE_CONTROL
);
280 static int tegra_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
281 struct drm_framebuffer
*fb
, int crtc_x
,
282 int crtc_y
, unsigned int crtc_w
,
283 unsigned int crtc_h
, uint32_t src_x
,
284 uint32_t src_y
, uint32_t src_w
, uint32_t src_h
)
286 struct tegra_plane
*p
= to_tegra_plane(plane
);
287 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
288 struct tegra_dc_window window
;
291 memset(&window
, 0, sizeof(window
));
292 window
.src
.x
= src_x
>> 16;
293 window
.src
.y
= src_y
>> 16;
294 window
.src
.w
= src_w
>> 16;
295 window
.src
.h
= src_h
>> 16;
296 window
.dst
.x
= crtc_x
;
297 window
.dst
.y
= crtc_y
;
298 window
.dst
.w
= crtc_w
;
299 window
.dst
.h
= crtc_h
;
300 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
301 window
.bits_per_pixel
= fb
->bits_per_pixel
;
302 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
303 window
.tiled
= tegra_fb_is_tiled(fb
);
305 for (i
= 0; i
< drm_format_num_planes(fb
->pixel_format
); i
++) {
306 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, i
);
308 window
.base
[i
] = bo
->paddr
+ fb
->offsets
[i
];
311 * Tegra doesn't support different strides for U and V planes
312 * so we display a warning if the user tries to display a
313 * framebuffer with such a configuration.
316 if (fb
->pitches
[i
] != window
.stride
[1])
317 DRM_ERROR("unsupported UV-plane configuration\n");
319 window
.stride
[i
] = fb
->pitches
[i
];
323 return tegra_dc_setup_window(dc
, p
->index
, &window
);
326 static int tegra_plane_disable(struct drm_plane
*plane
)
328 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
329 struct tegra_plane
*p
= to_tegra_plane(plane
);
335 value
= WINDOW_A_SELECT
<< p
->index
;
336 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
338 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
339 value
&= ~WIN_ENABLE
;
340 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
342 tegra_dc_writel(dc
, WIN_A_UPDATE
<< p
->index
, DC_CMD_STATE_CONTROL
);
343 tegra_dc_writel(dc
, WIN_A_ACT_REQ
<< p
->index
, DC_CMD_STATE_CONTROL
);
348 static void tegra_plane_destroy(struct drm_plane
*plane
)
350 struct tegra_plane
*p
= to_tegra_plane(plane
);
352 tegra_plane_disable(plane
);
353 drm_plane_cleanup(plane
);
357 static const struct drm_plane_funcs tegra_plane_funcs
= {
358 .update_plane
= tegra_plane_update
,
359 .disable_plane
= tegra_plane_disable
,
360 .destroy
= tegra_plane_destroy
,
363 static const uint32_t plane_formats
[] = {
373 static int tegra_dc_add_planes(struct drm_device
*drm
, struct tegra_dc
*dc
)
378 for (i
= 0; i
< 2; i
++) {
379 struct tegra_plane
*plane
;
381 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
385 plane
->index
= 1 + i
;
387 err
= drm_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
388 &tegra_plane_funcs
, plane_formats
,
389 ARRAY_SIZE(plane_formats
), false);
399 static int tegra_dc_set_base(struct tegra_dc
*dc
, int x
, int y
,
400 struct drm_framebuffer
*fb
)
402 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
403 unsigned int h_offset
= 0, v_offset
= 0;
404 unsigned int format
, swap
;
407 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
409 value
= fb
->offsets
[0] + y
* fb
->pitches
[0] +
410 x
* fb
->bits_per_pixel
/ 8;
412 tegra_dc_writel(dc
, bo
->paddr
+ value
, DC_WINBUF_START_ADDR
);
413 tegra_dc_writel(dc
, fb
->pitches
[0], DC_WIN_LINE_STRIDE
);
415 format
= tegra_dc_format(fb
->pixel_format
, &swap
);
416 tegra_dc_writel(dc
, format
, DC_WIN_COLOR_DEPTH
);
417 tegra_dc_writel(dc
, swap
, DC_WIN_BYTE_SWAP
);
419 if (tegra_fb_is_tiled(fb
)) {
420 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
421 DC_WIN_BUFFER_ADDR_MODE_TILE
;
423 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
424 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
427 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
429 /* make sure bottom-up buffers are properly displayed */
430 if (tegra_fb_is_bottom_up(fb
)) {
431 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
432 value
|= V_DIRECTION
;
433 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
435 v_offset
+= fb
->height
- 1;
437 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
438 value
&= ~V_DIRECTION
;
439 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
442 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
443 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
445 value
= GENERAL_UPDATE
| WIN_A_UPDATE
;
446 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
448 value
= GENERAL_ACT_REQ
| WIN_A_ACT_REQ
;
449 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
454 void tegra_dc_enable_vblank(struct tegra_dc
*dc
)
456 unsigned long value
, flags
;
458 spin_lock_irqsave(&dc
->lock
, flags
);
460 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
462 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
464 spin_unlock_irqrestore(&dc
->lock
, flags
);
467 void tegra_dc_disable_vblank(struct tegra_dc
*dc
)
469 unsigned long value
, flags
;
471 spin_lock_irqsave(&dc
->lock
, flags
);
473 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
474 value
&= ~VBLANK_INT
;
475 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
477 spin_unlock_irqrestore(&dc
->lock
, flags
);
480 static void tegra_dc_finish_page_flip(struct tegra_dc
*dc
)
482 struct drm_device
*drm
= dc
->base
.dev
;
483 struct drm_crtc
*crtc
= &dc
->base
;
484 unsigned long flags
, base
;
490 bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
492 /* check if new start address has been latched */
493 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
494 base
= tegra_dc_readl(dc
, DC_WINBUF_START_ADDR
);
495 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
497 if (base
== bo
->paddr
+ crtc
->primary
->fb
->offsets
[0]) {
498 spin_lock_irqsave(&drm
->event_lock
, flags
);
499 drm_send_vblank_event(drm
, dc
->pipe
, dc
->event
);
500 drm_vblank_put(drm
, dc
->pipe
);
502 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
506 void tegra_dc_cancel_page_flip(struct drm_crtc
*crtc
, struct drm_file
*file
)
508 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
509 struct drm_device
*drm
= crtc
->dev
;
512 spin_lock_irqsave(&drm
->event_lock
, flags
);
514 if (dc
->event
&& dc
->event
->base
.file_priv
== file
) {
515 dc
->event
->base
.destroy(&dc
->event
->base
);
516 drm_vblank_put(drm
, dc
->pipe
);
520 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
523 static int tegra_dc_page_flip(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
524 struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
)
526 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
527 struct drm_device
*drm
= crtc
->dev
;
533 event
->pipe
= dc
->pipe
;
535 drm_vblank_get(drm
, dc
->pipe
);
538 tegra_dc_set_base(dc
, 0, 0, fb
);
539 crtc
->primary
->fb
= fb
;
544 static void drm_crtc_clear(struct drm_crtc
*crtc
)
546 memset(crtc
, 0, sizeof(*crtc
));
549 static void tegra_dc_destroy(struct drm_crtc
*crtc
)
551 drm_crtc_cleanup(crtc
);
552 drm_crtc_clear(crtc
);
555 static const struct drm_crtc_funcs tegra_crtc_funcs
= {
556 .page_flip
= tegra_dc_page_flip
,
557 .set_config
= drm_crtc_helper_set_config
,
558 .destroy
= tegra_dc_destroy
,
561 static void tegra_crtc_disable(struct drm_crtc
*crtc
)
563 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
564 struct drm_device
*drm
= crtc
->dev
;
565 struct drm_plane
*plane
;
567 drm_for_each_legacy_plane(plane
, &drm
->mode_config
.plane_list
) {
568 if (plane
->crtc
== crtc
) {
569 tegra_plane_disable(plane
);
573 drm_framebuffer_unreference(plane
->fb
);
579 drm_vblank_off(drm
, dc
->pipe
);
582 static bool tegra_crtc_mode_fixup(struct drm_crtc
*crtc
,
583 const struct drm_display_mode
*mode
,
584 struct drm_display_mode
*adjusted
)
589 static int tegra_dc_set_timings(struct tegra_dc
*dc
,
590 struct drm_display_mode
*mode
)
592 unsigned int h_ref_to_sync
= 1;
593 unsigned int v_ref_to_sync
= 1;
596 tegra_dc_writel(dc
, 0x0, DC_DISP_DISP_TIMING_OPTIONS
);
598 value
= (v_ref_to_sync
<< 16) | h_ref_to_sync
;
599 tegra_dc_writel(dc
, value
, DC_DISP_REF_TO_SYNC
);
601 value
= ((mode
->vsync_end
- mode
->vsync_start
) << 16) |
602 ((mode
->hsync_end
- mode
->hsync_start
) << 0);
603 tegra_dc_writel(dc
, value
, DC_DISP_SYNC_WIDTH
);
605 value
= ((mode
->vtotal
- mode
->vsync_end
) << 16) |
606 ((mode
->htotal
- mode
->hsync_end
) << 0);
607 tegra_dc_writel(dc
, value
, DC_DISP_BACK_PORCH
);
609 value
= ((mode
->vsync_start
- mode
->vdisplay
) << 16) |
610 ((mode
->hsync_start
- mode
->hdisplay
) << 0);
611 tegra_dc_writel(dc
, value
, DC_DISP_FRONT_PORCH
);
613 value
= (mode
->vdisplay
<< 16) | mode
->hdisplay
;
614 tegra_dc_writel(dc
, value
, DC_DISP_ACTIVE
);
619 static int tegra_crtc_setup_clk(struct drm_crtc
*crtc
,
620 struct drm_display_mode
*mode
,
623 unsigned long pclk
= mode
->clock
* 1000, rate
;
624 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
625 struct tegra_output
*output
= NULL
;
626 struct drm_encoder
*encoder
;
629 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
, head
)
630 if (encoder
->crtc
== crtc
) {
631 output
= encoder_to_output(encoder
);
639 * This assumes that the display controller will divide its parent
640 * clock by 2 to generate the pixel clock.
642 err
= tegra_output_setup_clock(output
, dc
->clk
, pclk
* 2);
644 dev_err(dc
->dev
, "failed to setup clock: %ld\n", err
);
648 rate
= clk_get_rate(dc
->clk
);
649 *div
= (rate
* 2 / pclk
) - 2;
651 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate
, *div
);
656 static int tegra_crtc_mode_set(struct drm_crtc
*crtc
,
657 struct drm_display_mode
*mode
,
658 struct drm_display_mode
*adjusted
,
659 int x
, int y
, struct drm_framebuffer
*old_fb
)
661 struct tegra_bo
*bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
662 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
663 struct tegra_dc_window window
;
664 unsigned long div
, value
;
667 drm_vblank_pre_modeset(crtc
->dev
, dc
->pipe
);
669 err
= tegra_crtc_setup_clk(crtc
, mode
, &div
);
671 dev_err(dc
->dev
, "failed to setup clock for CRTC: %d\n", err
);
675 /* program display mode */
676 tegra_dc_set_timings(dc
, mode
);
678 /* interlacing isn't supported yet, so disable it */
679 if (dc
->soc
->supports_interlacing
) {
680 value
= tegra_dc_readl(dc
, DC_DISP_INTERLACE_CONTROL
);
681 value
&= ~INTERLACE_ENABLE
;
682 tegra_dc_writel(dc
, value
, DC_DISP_INTERLACE_CONTROL
);
685 value
= SHIFT_CLK_DIVIDER(div
) | PIXEL_CLK_DIVIDER_PCD1
;
686 tegra_dc_writel(dc
, value
, DC_DISP_DISP_CLOCK_CONTROL
);
688 /* setup window parameters */
689 memset(&window
, 0, sizeof(window
));
692 window
.src
.w
= mode
->hdisplay
;
693 window
.src
.h
= mode
->vdisplay
;
696 window
.dst
.w
= mode
->hdisplay
;
697 window
.dst
.h
= mode
->vdisplay
;
698 window
.format
= tegra_dc_format(crtc
->primary
->fb
->pixel_format
,
700 window
.bits_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
;
701 window
.stride
[0] = crtc
->primary
->fb
->pitches
[0];
702 window
.base
[0] = bo
->paddr
;
704 err
= tegra_dc_setup_window(dc
, 0, &window
);
706 dev_err(dc
->dev
, "failed to enable root plane\n");
711 static int tegra_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
712 struct drm_framebuffer
*old_fb
)
714 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
716 return tegra_dc_set_base(dc
, x
, y
, crtc
->primary
->fb
);
719 static void tegra_crtc_prepare(struct drm_crtc
*crtc
)
721 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
725 /* hardware initialization */
726 reset_control_deassert(dc
->rst
);
727 usleep_range(10000, 20000);
730 syncpt
= SYNCPT_VBLANK1
;
732 syncpt
= SYNCPT_VBLANK0
;
734 /* initialize display controller */
735 tegra_dc_writel(dc
, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
736 tegra_dc_writel(dc
, 0x100 | syncpt
, DC_CMD_CONT_SYNCPT_VSYNC
);
738 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
| WIN_A_OF_INT
;
739 tegra_dc_writel(dc
, value
, DC_CMD_INT_TYPE
);
741 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
742 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
743 tegra_dc_writel(dc
, value
, DC_CMD_INT_POLARITY
);
745 /* initialize timer */
746 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
747 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
748 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY
);
750 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
751 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
752 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
754 value
= VBLANK_INT
| WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
755 tegra_dc_writel(dc
, value
, DC_CMD_INT_ENABLE
);
757 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
758 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
761 static void tegra_crtc_commit(struct drm_crtc
*crtc
)
763 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
766 value
= GENERAL_UPDATE
| WIN_A_UPDATE
;
767 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
769 value
= GENERAL_ACT_REQ
| WIN_A_ACT_REQ
;
770 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
772 drm_vblank_post_modeset(crtc
->dev
, dc
->pipe
);
775 static void tegra_crtc_load_lut(struct drm_crtc
*crtc
)
779 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs
= {
780 .disable
= tegra_crtc_disable
,
781 .mode_fixup
= tegra_crtc_mode_fixup
,
782 .mode_set
= tegra_crtc_mode_set
,
783 .mode_set_base
= tegra_crtc_mode_set_base
,
784 .prepare
= tegra_crtc_prepare
,
785 .commit
= tegra_crtc_commit
,
786 .load_lut
= tegra_crtc_load_lut
,
789 static irqreturn_t
tegra_dc_irq(int irq
, void *data
)
791 struct tegra_dc
*dc
= data
;
792 unsigned long status
;
794 status
= tegra_dc_readl(dc
, DC_CMD_INT_STATUS
);
795 tegra_dc_writel(dc
, status
, DC_CMD_INT_STATUS
);
797 if (status
& FRAME_END_INT
) {
799 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
803 if (status
& VBLANK_INT
) {
805 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
807 drm_handle_vblank(dc
->base
.dev
, dc
->pipe
);
808 tegra_dc_finish_page_flip(dc
);
811 if (status
& (WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
)) {
813 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
820 static int tegra_dc_show_regs(struct seq_file
*s
, void *data
)
822 struct drm_info_node
*node
= s
->private;
823 struct tegra_dc
*dc
= node
->info_ent
->data
;
825 #define DUMP_REG(name) \
826 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
827 tegra_dc_readl(dc, name))
829 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT
);
830 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
831 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR
);
832 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT
);
833 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL
);
834 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR
);
835 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT
);
836 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL
);
837 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR
);
838 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT
);
839 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL
);
840 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR
);
841 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC
);
842 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0
);
843 DUMP_REG(DC_CMD_DISPLAY_COMMAND
);
844 DUMP_REG(DC_CMD_SIGNAL_RAISE
);
845 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL
);
846 DUMP_REG(DC_CMD_INT_STATUS
);
847 DUMP_REG(DC_CMD_INT_MASK
);
848 DUMP_REG(DC_CMD_INT_ENABLE
);
849 DUMP_REG(DC_CMD_INT_TYPE
);
850 DUMP_REG(DC_CMD_INT_POLARITY
);
851 DUMP_REG(DC_CMD_SIGNAL_RAISE1
);
852 DUMP_REG(DC_CMD_SIGNAL_RAISE2
);
853 DUMP_REG(DC_CMD_SIGNAL_RAISE3
);
854 DUMP_REG(DC_CMD_STATE_ACCESS
);
855 DUMP_REG(DC_CMD_STATE_CONTROL
);
856 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER
);
857 DUMP_REG(DC_CMD_REG_ACT_CONTROL
);
858 DUMP_REG(DC_COM_CRC_CONTROL
);
859 DUMP_REG(DC_COM_CRC_CHECKSUM
);
860 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
861 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
862 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
863 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
864 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
865 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
866 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
867 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
868 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
869 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
870 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
871 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
872 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
873 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
874 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
875 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
876 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
877 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
878 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
879 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
880 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
881 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
882 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
883 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
884 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
885 DUMP_REG(DC_COM_PIN_MISC_CONTROL
);
886 DUMP_REG(DC_COM_PIN_PM0_CONTROL
);
887 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE
);
888 DUMP_REG(DC_COM_PIN_PM1_CONTROL
);
889 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE
);
890 DUMP_REG(DC_COM_SPI_CONTROL
);
891 DUMP_REG(DC_COM_SPI_START_BYTE
);
892 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB
);
893 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD
);
894 DUMP_REG(DC_COM_HSPI_CS_DC
);
895 DUMP_REG(DC_COM_SCRATCH_REGISTER_A
);
896 DUMP_REG(DC_COM_SCRATCH_REGISTER_B
);
897 DUMP_REG(DC_COM_GPIO_CTRL
);
898 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER
);
899 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED
);
900 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0
);
901 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1
);
902 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS
);
903 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY
);
904 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
905 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS
);
906 DUMP_REG(DC_DISP_REF_TO_SYNC
);
907 DUMP_REG(DC_DISP_SYNC_WIDTH
);
908 DUMP_REG(DC_DISP_BACK_PORCH
);
909 DUMP_REG(DC_DISP_ACTIVE
);
910 DUMP_REG(DC_DISP_FRONT_PORCH
);
911 DUMP_REG(DC_DISP_H_PULSE0_CONTROL
);
912 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A
);
913 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B
);
914 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C
);
915 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D
);
916 DUMP_REG(DC_DISP_H_PULSE1_CONTROL
);
917 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A
);
918 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B
);
919 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C
);
920 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D
);
921 DUMP_REG(DC_DISP_H_PULSE2_CONTROL
);
922 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A
);
923 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B
);
924 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C
);
925 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D
);
926 DUMP_REG(DC_DISP_V_PULSE0_CONTROL
);
927 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A
);
928 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B
);
929 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C
);
930 DUMP_REG(DC_DISP_V_PULSE1_CONTROL
);
931 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A
);
932 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B
);
933 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C
);
934 DUMP_REG(DC_DISP_V_PULSE2_CONTROL
);
935 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A
);
936 DUMP_REG(DC_DISP_V_PULSE3_CONTROL
);
937 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A
);
938 DUMP_REG(DC_DISP_M0_CONTROL
);
939 DUMP_REG(DC_DISP_M1_CONTROL
);
940 DUMP_REG(DC_DISP_DI_CONTROL
);
941 DUMP_REG(DC_DISP_PP_CONTROL
);
942 DUMP_REG(DC_DISP_PP_SELECT_A
);
943 DUMP_REG(DC_DISP_PP_SELECT_B
);
944 DUMP_REG(DC_DISP_PP_SELECT_C
);
945 DUMP_REG(DC_DISP_PP_SELECT_D
);
946 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL
);
947 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL
);
948 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL
);
949 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS
);
950 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS
);
951 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS
);
952 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS
);
953 DUMP_REG(DC_DISP_BORDER_COLOR
);
954 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER
);
955 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER
);
956 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER
);
957 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER
);
958 DUMP_REG(DC_DISP_CURSOR_FOREGROUND
);
959 DUMP_REG(DC_DISP_CURSOR_BACKGROUND
);
960 DUMP_REG(DC_DISP_CURSOR_START_ADDR
);
961 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS
);
962 DUMP_REG(DC_DISP_CURSOR_POSITION
);
963 DUMP_REG(DC_DISP_CURSOR_POSITION_NS
);
964 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL
);
965 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A
);
966 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B
);
967 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C
);
968 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D
);
969 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL
);
970 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST
);
971 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST
);
972 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST
);
973 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST
);
974 DUMP_REG(DC_DISP_DAC_CRT_CTRL
);
975 DUMP_REG(DC_DISP_DISP_MISC_CONTROL
);
976 DUMP_REG(DC_DISP_SD_CONTROL
);
977 DUMP_REG(DC_DISP_SD_CSC_COEFF
);
978 DUMP_REG(DC_DISP_SD_LUT(0));
979 DUMP_REG(DC_DISP_SD_LUT(1));
980 DUMP_REG(DC_DISP_SD_LUT(2));
981 DUMP_REG(DC_DISP_SD_LUT(3));
982 DUMP_REG(DC_DISP_SD_LUT(4));
983 DUMP_REG(DC_DISP_SD_LUT(5));
984 DUMP_REG(DC_DISP_SD_LUT(6));
985 DUMP_REG(DC_DISP_SD_LUT(7));
986 DUMP_REG(DC_DISP_SD_LUT(8));
987 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL
);
988 DUMP_REG(DC_DISP_DC_PIXEL_COUNT
);
989 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
990 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
991 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
992 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
993 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
994 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
995 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
996 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
997 DUMP_REG(DC_DISP_SD_BL_TF(0));
998 DUMP_REG(DC_DISP_SD_BL_TF(1));
999 DUMP_REG(DC_DISP_SD_BL_TF(2));
1000 DUMP_REG(DC_DISP_SD_BL_TF(3));
1001 DUMP_REG(DC_DISP_SD_BL_CONTROL
);
1002 DUMP_REG(DC_DISP_SD_HW_K_VALUES
);
1003 DUMP_REG(DC_DISP_SD_MAN_K_VALUES
);
1004 DUMP_REG(DC_WIN_WIN_OPTIONS
);
1005 DUMP_REG(DC_WIN_BYTE_SWAP
);
1006 DUMP_REG(DC_WIN_BUFFER_CONTROL
);
1007 DUMP_REG(DC_WIN_COLOR_DEPTH
);
1008 DUMP_REG(DC_WIN_POSITION
);
1009 DUMP_REG(DC_WIN_SIZE
);
1010 DUMP_REG(DC_WIN_PRESCALED_SIZE
);
1011 DUMP_REG(DC_WIN_H_INITIAL_DDA
);
1012 DUMP_REG(DC_WIN_V_INITIAL_DDA
);
1013 DUMP_REG(DC_WIN_DDA_INC
);
1014 DUMP_REG(DC_WIN_LINE_STRIDE
);
1015 DUMP_REG(DC_WIN_BUF_STRIDE
);
1016 DUMP_REG(DC_WIN_UV_BUF_STRIDE
);
1017 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE
);
1018 DUMP_REG(DC_WIN_DV_CONTROL
);
1019 DUMP_REG(DC_WIN_BLEND_NOKEY
);
1020 DUMP_REG(DC_WIN_BLEND_1WIN
);
1021 DUMP_REG(DC_WIN_BLEND_2WIN_X
);
1022 DUMP_REG(DC_WIN_BLEND_2WIN_Y
);
1023 DUMP_REG(DC_WIN_BLEND_3WIN_XY
);
1024 DUMP_REG(DC_WIN_HP_FETCH_CONTROL
);
1025 DUMP_REG(DC_WINBUF_START_ADDR
);
1026 DUMP_REG(DC_WINBUF_START_ADDR_NS
);
1027 DUMP_REG(DC_WINBUF_START_ADDR_U
);
1028 DUMP_REG(DC_WINBUF_START_ADDR_U_NS
);
1029 DUMP_REG(DC_WINBUF_START_ADDR_V
);
1030 DUMP_REG(DC_WINBUF_START_ADDR_V_NS
);
1031 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET
);
1032 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS
);
1033 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET
);
1034 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS
);
1035 DUMP_REG(DC_WINBUF_UFLOW_STATUS
);
1036 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS
);
1037 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS
);
1038 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS
);
1045 static struct drm_info_list debugfs_files
[] = {
1046 { "regs", tegra_dc_show_regs
, 0, NULL
},
1049 static int tegra_dc_debugfs_init(struct tegra_dc
*dc
, struct drm_minor
*minor
)
1055 name
= kasprintf(GFP_KERNEL
, "dc.%d", dc
->pipe
);
1056 dc
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
1062 dc
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
1064 if (!dc
->debugfs_files
) {
1069 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
1070 dc
->debugfs_files
[i
].data
= dc
;
1072 err
= drm_debugfs_create_files(dc
->debugfs_files
,
1073 ARRAY_SIZE(debugfs_files
),
1074 dc
->debugfs
, minor
);
1083 kfree(dc
->debugfs_files
);
1084 dc
->debugfs_files
= NULL
;
1086 debugfs_remove(dc
->debugfs
);
1092 static int tegra_dc_debugfs_exit(struct tegra_dc
*dc
)
1094 drm_debugfs_remove_files(dc
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
1098 kfree(dc
->debugfs_files
);
1099 dc
->debugfs_files
= NULL
;
1101 debugfs_remove(dc
->debugfs
);
1107 static int tegra_dc_init(struct host1x_client
*client
)
1109 struct tegra_drm
*tegra
= dev_get_drvdata(client
->parent
);
1110 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1113 drm_crtc_init(tegra
->drm
, &dc
->base
, &tegra_crtc_funcs
);
1114 drm_mode_crtc_set_gamma_size(&dc
->base
, 256);
1115 drm_crtc_helper_add(&dc
->base
, &tegra_crtc_helper_funcs
);
1117 err
= tegra_dc_rgb_init(tegra
->drm
, dc
);
1118 if (err
< 0 && err
!= -ENODEV
) {
1119 dev_err(dc
->dev
, "failed to initialize RGB output: %d\n", err
);
1123 err
= tegra_dc_add_planes(tegra
->drm
, dc
);
1127 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1128 err
= tegra_dc_debugfs_init(dc
, tegra
->drm
->primary
);
1130 dev_err(dc
->dev
, "debugfs setup failed: %d\n", err
);
1133 err
= devm_request_irq(dc
->dev
, dc
->irq
, tegra_dc_irq
, 0,
1134 dev_name(dc
->dev
), dc
);
1136 dev_err(dc
->dev
, "failed to request IRQ#%u: %d\n", dc
->irq
,
1144 static int tegra_dc_exit(struct host1x_client
*client
)
1146 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1149 devm_free_irq(dc
->dev
, dc
->irq
, dc
);
1151 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1152 err
= tegra_dc_debugfs_exit(dc
);
1154 dev_err(dc
->dev
, "debugfs cleanup failed: %d\n", err
);
1157 err
= tegra_dc_rgb_exit(dc
);
1159 dev_err(dc
->dev
, "failed to shutdown RGB output: %d\n", err
);
1166 static const struct host1x_client_ops dc_client_ops
= {
1167 .init
= tegra_dc_init
,
1168 .exit
= tegra_dc_exit
,
1171 static const struct tegra_dc_soc_info tegra20_dc_soc_info
= {
1172 .supports_interlacing
= false,
1175 static const struct tegra_dc_soc_info tegra30_dc_soc_info
= {
1176 .supports_interlacing
= false,
1179 static const struct tegra_dc_soc_info tegra124_dc_soc_info
= {
1180 .supports_interlacing
= true,
1183 static const struct of_device_id tegra_dc_of_match
[] = {
1185 .compatible
= "nvidia,tegra124-dc",
1186 .data
= &tegra124_dc_soc_info
,
1188 .compatible
= "nvidia,tegra30-dc",
1189 .data
= &tegra30_dc_soc_info
,
1191 .compatible
= "nvidia,tegra20-dc",
1192 .data
= &tegra20_dc_soc_info
,
1198 static int tegra_dc_parse_dt(struct tegra_dc
*dc
)
1200 struct device_node
*np
;
1204 err
= of_property_read_u32(dc
->dev
->of_node
, "nvidia,head", &value
);
1206 dev_err(dc
->dev
, "missing \"nvidia,head\" property\n");
1209 * If the nvidia,head property isn't present, try to find the
1210 * correct head number by looking up the position of this
1211 * display controller's node within the device tree. Assuming
1212 * that the nodes are ordered properly in the DTS file and
1213 * that the translation into a flattened device tree blob
1214 * preserves that ordering this will actually yield the right
1217 * If those assumptions don't hold, this will still work for
1218 * cases where only a single display controller is used.
1220 for_each_matching_node(np
, tegra_dc_of_match
) {
1221 if (np
== dc
->dev
->of_node
)
1233 static int tegra_dc_probe(struct platform_device
*pdev
)
1235 const struct of_device_id
*id
;
1236 struct resource
*regs
;
1237 struct tegra_dc
*dc
;
1240 dc
= devm_kzalloc(&pdev
->dev
, sizeof(*dc
), GFP_KERNEL
);
1244 id
= of_match_node(tegra_dc_of_match
, pdev
->dev
.of_node
);
1248 spin_lock_init(&dc
->lock
);
1249 INIT_LIST_HEAD(&dc
->list
);
1250 dc
->dev
= &pdev
->dev
;
1253 err
= tegra_dc_parse_dt(dc
);
1257 dc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1258 if (IS_ERR(dc
->clk
)) {
1259 dev_err(&pdev
->dev
, "failed to get clock\n");
1260 return PTR_ERR(dc
->clk
);
1263 dc
->rst
= devm_reset_control_get(&pdev
->dev
, "dc");
1264 if (IS_ERR(dc
->rst
)) {
1265 dev_err(&pdev
->dev
, "failed to get reset\n");
1266 return PTR_ERR(dc
->rst
);
1269 err
= clk_prepare_enable(dc
->clk
);
1273 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1274 dc
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1275 if (IS_ERR(dc
->regs
))
1276 return PTR_ERR(dc
->regs
);
1278 dc
->irq
= platform_get_irq(pdev
, 0);
1280 dev_err(&pdev
->dev
, "failed to get IRQ\n");
1284 INIT_LIST_HEAD(&dc
->client
.list
);
1285 dc
->client
.ops
= &dc_client_ops
;
1286 dc
->client
.dev
= &pdev
->dev
;
1288 err
= tegra_dc_rgb_probe(dc
);
1289 if (err
< 0 && err
!= -ENODEV
) {
1290 dev_err(&pdev
->dev
, "failed to probe RGB output: %d\n", err
);
1294 err
= host1x_client_register(&dc
->client
);
1296 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1301 platform_set_drvdata(pdev
, dc
);
1306 static int tegra_dc_remove(struct platform_device
*pdev
)
1308 struct tegra_dc
*dc
= platform_get_drvdata(pdev
);
1311 err
= host1x_client_unregister(&dc
->client
);
1313 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1318 err
= tegra_dc_rgb_remove(dc
);
1320 dev_err(&pdev
->dev
, "failed to remove RGB output: %d\n", err
);
1324 clk_disable_unprepare(dc
->clk
);
1329 struct platform_driver tegra_dc_driver
= {
1332 .owner
= THIS_MODULE
,
1333 .of_match_table
= tegra_dc_of_match
,
1335 .probe
= tegra_dc_probe
,
1336 .remove
= tegra_dc_remove
,