2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
16 #include <soc/tegra/pmc.h>
22 #include <drm/drm_atomic.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_plane_helper.h>
26 struct tegra_dc_soc_info
{
27 bool supports_border_color
;
28 bool supports_interlacing
;
30 bool supports_block_linear
;
31 unsigned int pitch_align
;
36 struct drm_plane base
;
40 static inline struct tegra_plane
*to_tegra_plane(struct drm_plane
*plane
)
42 return container_of(plane
, struct tegra_plane
, base
);
45 struct tegra_dc_state
{
46 struct drm_crtc_state base
;
55 static inline struct tegra_dc_state
*to_dc_state(struct drm_crtc_state
*state
)
58 return container_of(state
, struct tegra_dc_state
, base
);
63 struct tegra_plane_state
{
64 struct drm_plane_state base
;
66 struct tegra_bo_tiling tiling
;
71 static inline struct tegra_plane_state
*
72 to_tegra_plane_state(struct drm_plane_state
*state
)
75 return container_of(state
, struct tegra_plane_state
, base
);
80 static void tegra_dc_stats_reset(struct tegra_dc_stats
*stats
)
89 * Reads the active copy of a register. This takes the dc->lock spinlock to
90 * prevent races with the VBLANK processing which also needs access to the
91 * active copy of some registers.
93 static u32
tegra_dc_readl_active(struct tegra_dc
*dc
, unsigned long offset
)
98 spin_lock_irqsave(&dc
->lock
, flags
);
100 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
101 value
= tegra_dc_readl(dc
, offset
);
102 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
104 spin_unlock_irqrestore(&dc
->lock
, flags
);
109 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
110 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
111 * Latching happens mmediately if the display controller is in STOP mode or
112 * on the next frame boundary otherwise.
114 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
115 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
116 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
117 * into the ACTIVE copy, either immediately if the display controller is in
118 * STOP mode, or at the next frame boundary otherwise.
120 void tegra_dc_commit(struct tegra_dc
*dc
)
122 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
123 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
126 static int tegra_dc_format(u32 fourcc
, u32
*format
, u32
*swap
)
128 /* assume no swapping of fetched data */
130 *swap
= BYTE_SWAP_NOSWAP
;
133 case DRM_FORMAT_XBGR8888
:
134 *format
= WIN_COLOR_DEPTH_R8G8B8A8
;
137 case DRM_FORMAT_XRGB8888
:
138 *format
= WIN_COLOR_DEPTH_B8G8R8A8
;
141 case DRM_FORMAT_RGB565
:
142 *format
= WIN_COLOR_DEPTH_B5G6R5
;
145 case DRM_FORMAT_UYVY
:
146 *format
= WIN_COLOR_DEPTH_YCbCr422
;
149 case DRM_FORMAT_YUYV
:
151 *swap
= BYTE_SWAP_SWAP2
;
153 *format
= WIN_COLOR_DEPTH_YCbCr422
;
156 case DRM_FORMAT_YUV420
:
157 *format
= WIN_COLOR_DEPTH_YCbCr420P
;
160 case DRM_FORMAT_YUV422
:
161 *format
= WIN_COLOR_DEPTH_YCbCr422P
;
171 static bool tegra_dc_format_is_yuv(unsigned int format
, bool *planar
)
174 case WIN_COLOR_DEPTH_YCbCr422
:
175 case WIN_COLOR_DEPTH_YUV422
:
181 case WIN_COLOR_DEPTH_YCbCr420P
:
182 case WIN_COLOR_DEPTH_YUV420P
:
183 case WIN_COLOR_DEPTH_YCbCr422P
:
184 case WIN_COLOR_DEPTH_YUV422P
:
185 case WIN_COLOR_DEPTH_YCbCr422R
:
186 case WIN_COLOR_DEPTH_YUV422R
:
187 case WIN_COLOR_DEPTH_YCbCr422RA
:
188 case WIN_COLOR_DEPTH_YUV422RA
:
201 static inline u32
compute_dda_inc(unsigned int in
, unsigned int out
, bool v
,
204 fixed20_12 outf
= dfixed_init(out
);
205 fixed20_12 inf
= dfixed_init(in
);
226 outf
.full
= max_t(u32
, outf
.full
- dfixed_const(1), dfixed_const(1));
227 inf
.full
-= dfixed_const(1);
229 dda_inc
= dfixed_div(inf
, outf
);
230 dda_inc
= min_t(u32
, dda_inc
, dfixed_const(max
));
235 static inline u32
compute_initial_dda(unsigned int in
)
237 fixed20_12 inf
= dfixed_init(in
);
238 return dfixed_frac(inf
);
241 static void tegra_dc_setup_window(struct tegra_dc
*dc
, unsigned int index
,
242 const struct tegra_dc_window
*window
)
244 unsigned h_offset
, v_offset
, h_size
, v_size
, h_dda
, v_dda
, bpp
;
245 unsigned long value
, flags
;
249 * For YUV planar modes, the number of bytes per pixel takes into
250 * account only the luma component and therefore is 1.
252 yuv
= tegra_dc_format_is_yuv(window
->format
, &planar
);
254 bpp
= window
->bits_per_pixel
/ 8;
256 bpp
= planar
? 1 : 2;
258 spin_lock_irqsave(&dc
->lock
, flags
);
260 value
= WINDOW_A_SELECT
<< index
;
261 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
263 tegra_dc_writel(dc
, window
->format
, DC_WIN_COLOR_DEPTH
);
264 tegra_dc_writel(dc
, window
->swap
, DC_WIN_BYTE_SWAP
);
266 value
= V_POSITION(window
->dst
.y
) | H_POSITION(window
->dst
.x
);
267 tegra_dc_writel(dc
, value
, DC_WIN_POSITION
);
269 value
= V_SIZE(window
->dst
.h
) | H_SIZE(window
->dst
.w
);
270 tegra_dc_writel(dc
, value
, DC_WIN_SIZE
);
272 h_offset
= window
->src
.x
* bpp
;
273 v_offset
= window
->src
.y
;
274 h_size
= window
->src
.w
* bpp
;
275 v_size
= window
->src
.h
;
277 value
= V_PRESCALED_SIZE(v_size
) | H_PRESCALED_SIZE(h_size
);
278 tegra_dc_writel(dc
, value
, DC_WIN_PRESCALED_SIZE
);
281 * For DDA computations the number of bytes per pixel for YUV planar
282 * modes needs to take into account all Y, U and V components.
287 h_dda
= compute_dda_inc(window
->src
.w
, window
->dst
.w
, false, bpp
);
288 v_dda
= compute_dda_inc(window
->src
.h
, window
->dst
.h
, true, bpp
);
290 value
= V_DDA_INC(v_dda
) | H_DDA_INC(h_dda
);
291 tegra_dc_writel(dc
, value
, DC_WIN_DDA_INC
);
293 h_dda
= compute_initial_dda(window
->src
.x
);
294 v_dda
= compute_initial_dda(window
->src
.y
);
296 tegra_dc_writel(dc
, h_dda
, DC_WIN_H_INITIAL_DDA
);
297 tegra_dc_writel(dc
, v_dda
, DC_WIN_V_INITIAL_DDA
);
299 tegra_dc_writel(dc
, 0, DC_WIN_UV_BUF_STRIDE
);
300 tegra_dc_writel(dc
, 0, DC_WIN_BUF_STRIDE
);
302 tegra_dc_writel(dc
, window
->base
[0], DC_WINBUF_START_ADDR
);
305 tegra_dc_writel(dc
, window
->base
[1], DC_WINBUF_START_ADDR_U
);
306 tegra_dc_writel(dc
, window
->base
[2], DC_WINBUF_START_ADDR_V
);
307 value
= window
->stride
[1] << 16 | window
->stride
[0];
308 tegra_dc_writel(dc
, value
, DC_WIN_LINE_STRIDE
);
310 tegra_dc_writel(dc
, window
->stride
[0], DC_WIN_LINE_STRIDE
);
313 if (window
->bottom_up
)
314 v_offset
+= window
->src
.h
- 1;
316 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
317 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
319 if (dc
->soc
->supports_block_linear
) {
320 unsigned long height
= window
->tiling
.value
;
322 switch (window
->tiling
.mode
) {
323 case TEGRA_BO_TILING_MODE_PITCH
:
324 value
= DC_WINBUF_SURFACE_KIND_PITCH
;
327 case TEGRA_BO_TILING_MODE_TILED
:
328 value
= DC_WINBUF_SURFACE_KIND_TILED
;
331 case TEGRA_BO_TILING_MODE_BLOCK
:
332 value
= DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height
) |
333 DC_WINBUF_SURFACE_KIND_BLOCK
;
337 tegra_dc_writel(dc
, value
, DC_WINBUF_SURFACE_KIND
);
339 switch (window
->tiling
.mode
) {
340 case TEGRA_BO_TILING_MODE_PITCH
:
341 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
342 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
345 case TEGRA_BO_TILING_MODE_TILED
:
346 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
347 DC_WIN_BUFFER_ADDR_MODE_TILE
;
350 case TEGRA_BO_TILING_MODE_BLOCK
:
352 * No need to handle this here because ->atomic_check
353 * will already have filtered it out.
358 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
364 /* setup default colorspace conversion coefficients */
365 tegra_dc_writel(dc
, 0x00f0, DC_WIN_CSC_YOF
);
366 tegra_dc_writel(dc
, 0x012a, DC_WIN_CSC_KYRGB
);
367 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KUR
);
368 tegra_dc_writel(dc
, 0x0198, DC_WIN_CSC_KVR
);
369 tegra_dc_writel(dc
, 0x039b, DC_WIN_CSC_KUG
);
370 tegra_dc_writel(dc
, 0x032f, DC_WIN_CSC_KVG
);
371 tegra_dc_writel(dc
, 0x0204, DC_WIN_CSC_KUB
);
372 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KVB
);
375 } else if (window
->bits_per_pixel
< 24) {
376 value
|= COLOR_EXPAND
;
379 if (window
->bottom_up
)
380 value
|= V_DIRECTION
;
382 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
385 * Disable blending and assume Window A is the bottom-most window,
386 * Window C is the top-most window and Window B is in the middle.
388 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_NOKEY
);
389 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_1WIN
);
393 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_X
);
394 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
395 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
399 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
400 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
401 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
405 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
406 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_Y
);
407 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_3WIN_XY
);
411 spin_unlock_irqrestore(&dc
->lock
, flags
);
414 static void tegra_plane_destroy(struct drm_plane
*plane
)
416 struct tegra_plane
*p
= to_tegra_plane(plane
);
418 drm_plane_cleanup(plane
);
422 static const u32 tegra_primary_plane_formats
[] = {
428 static void tegra_primary_plane_destroy(struct drm_plane
*plane
)
430 tegra_plane_destroy(plane
);
433 static void tegra_plane_reset(struct drm_plane
*plane
)
435 struct tegra_plane_state
*state
;
438 __drm_atomic_helper_plane_destroy_state(plane
->state
);
443 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
445 plane
->state
= &state
->base
;
446 plane
->state
->plane
= plane
;
450 static struct drm_plane_state
*tegra_plane_atomic_duplicate_state(struct drm_plane
*plane
)
452 struct tegra_plane_state
*state
= to_tegra_plane_state(plane
->state
);
453 struct tegra_plane_state
*copy
;
455 copy
= kmalloc(sizeof(*copy
), GFP_KERNEL
);
459 __drm_atomic_helper_plane_duplicate_state(plane
, ©
->base
);
460 copy
->tiling
= state
->tiling
;
461 copy
->format
= state
->format
;
462 copy
->swap
= state
->swap
;
467 static void tegra_plane_atomic_destroy_state(struct drm_plane
*plane
,
468 struct drm_plane_state
*state
)
470 __drm_atomic_helper_plane_destroy_state(state
);
474 static const struct drm_plane_funcs tegra_primary_plane_funcs
= {
475 .update_plane
= drm_atomic_helper_update_plane
,
476 .disable_plane
= drm_atomic_helper_disable_plane
,
477 .destroy
= tegra_primary_plane_destroy
,
478 .reset
= tegra_plane_reset
,
479 .atomic_duplicate_state
= tegra_plane_atomic_duplicate_state
,
480 .atomic_destroy_state
= tegra_plane_atomic_destroy_state
,
483 static int tegra_plane_state_add(struct tegra_plane
*plane
,
484 struct drm_plane_state
*state
)
486 struct drm_crtc_state
*crtc_state
;
487 struct tegra_dc_state
*tegra
;
489 /* Propagate errors from allocation or locking failures. */
490 crtc_state
= drm_atomic_get_crtc_state(state
->state
, state
->crtc
);
491 if (IS_ERR(crtc_state
))
492 return PTR_ERR(crtc_state
);
494 tegra
= to_dc_state(crtc_state
);
496 tegra
->planes
|= WIN_A_ACT_REQ
<< plane
->index
;
501 static int tegra_plane_atomic_check(struct drm_plane
*plane
,
502 struct drm_plane_state
*state
)
504 struct tegra_plane_state
*plane_state
= to_tegra_plane_state(state
);
505 struct tegra_bo_tiling
*tiling
= &plane_state
->tiling
;
506 struct tegra_plane
*tegra
= to_tegra_plane(plane
);
507 struct tegra_dc
*dc
= to_tegra_dc(state
->crtc
);
510 /* no need for further checks if the plane is being disabled */
514 err
= tegra_dc_format(state
->fb
->pixel_format
, &plane_state
->format
,
519 err
= tegra_fb_get_tiling(state
->fb
, tiling
);
523 if (tiling
->mode
== TEGRA_BO_TILING_MODE_BLOCK
&&
524 !dc
->soc
->supports_block_linear
) {
525 DRM_ERROR("hardware doesn't support block linear mode\n");
530 * Tegra doesn't support different strides for U and V planes so we
531 * error out if the user tries to display a framebuffer with such a
534 if (drm_format_num_planes(state
->fb
->pixel_format
) > 2) {
535 if (state
->fb
->pitches
[2] != state
->fb
->pitches
[1]) {
536 DRM_ERROR("unsupported UV-plane configuration\n");
541 err
= tegra_plane_state_add(tegra
, state
);
548 static void tegra_plane_atomic_update(struct drm_plane
*plane
,
549 struct drm_plane_state
*old_state
)
551 struct tegra_plane_state
*state
= to_tegra_plane_state(plane
->state
);
552 struct tegra_dc
*dc
= to_tegra_dc(plane
->state
->crtc
);
553 struct drm_framebuffer
*fb
= plane
->state
->fb
;
554 struct tegra_plane
*p
= to_tegra_plane(plane
);
555 struct tegra_dc_window window
;
558 /* rien ne va plus */
559 if (!plane
->state
->crtc
|| !plane
->state
->fb
)
562 memset(&window
, 0, sizeof(window
));
563 window
.src
.x
= plane
->state
->src_x
>> 16;
564 window
.src
.y
= plane
->state
->src_y
>> 16;
565 window
.src
.w
= plane
->state
->src_w
>> 16;
566 window
.src
.h
= plane
->state
->src_h
>> 16;
567 window
.dst
.x
= plane
->state
->crtc_x
;
568 window
.dst
.y
= plane
->state
->crtc_y
;
569 window
.dst
.w
= plane
->state
->crtc_w
;
570 window
.dst
.h
= plane
->state
->crtc_h
;
571 window
.bits_per_pixel
= fb
->bits_per_pixel
;
572 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
574 /* copy from state */
575 window
.tiling
= state
->tiling
;
576 window
.format
= state
->format
;
577 window
.swap
= state
->swap
;
579 for (i
= 0; i
< drm_format_num_planes(fb
->pixel_format
); i
++) {
580 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, i
);
582 window
.base
[i
] = bo
->paddr
+ fb
->offsets
[i
];
583 window
.stride
[i
] = fb
->pitches
[i
];
586 tegra_dc_setup_window(dc
, p
->index
, &window
);
589 static void tegra_plane_atomic_disable(struct drm_plane
*plane
,
590 struct drm_plane_state
*old_state
)
592 struct tegra_plane
*p
= to_tegra_plane(plane
);
597 /* rien ne va plus */
598 if (!old_state
|| !old_state
->crtc
)
601 dc
= to_tegra_dc(old_state
->crtc
);
603 spin_lock_irqsave(&dc
->lock
, flags
);
605 value
= WINDOW_A_SELECT
<< p
->index
;
606 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
608 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
609 value
&= ~WIN_ENABLE
;
610 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
612 spin_unlock_irqrestore(&dc
->lock
, flags
);
615 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs
= {
616 .atomic_check
= tegra_plane_atomic_check
,
617 .atomic_update
= tegra_plane_atomic_update
,
618 .atomic_disable
= tegra_plane_atomic_disable
,
621 static struct drm_plane
*tegra_dc_primary_plane_create(struct drm_device
*drm
,
625 * Ideally this would use drm_crtc_mask(), but that would require the
626 * CRTC to already be in the mode_config's list of CRTCs. However, it
627 * will only be added to that list in the drm_crtc_init_with_planes()
628 * (in tegra_dc_init()), which in turn requires registration of these
629 * planes. So we have ourselves a nice little chicken and egg problem
632 * We work around this by manually creating the mask from the number
633 * of CRTCs that have been registered, and should therefore always be
634 * the same as drm_crtc_index() after registration.
636 unsigned long possible_crtcs
= 1 << drm
->mode_config
.num_crtc
;
637 struct tegra_plane
*plane
;
638 unsigned int num_formats
;
642 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
644 return ERR_PTR(-ENOMEM
);
646 num_formats
= ARRAY_SIZE(tegra_primary_plane_formats
);
647 formats
= tegra_primary_plane_formats
;
649 err
= drm_universal_plane_init(drm
, &plane
->base
, possible_crtcs
,
650 &tegra_primary_plane_funcs
, formats
,
651 num_formats
, DRM_PLANE_TYPE_PRIMARY
,
658 drm_plane_helper_add(&plane
->base
, &tegra_primary_plane_helper_funcs
);
663 static const u32 tegra_cursor_plane_formats
[] = {
667 static int tegra_cursor_atomic_check(struct drm_plane
*plane
,
668 struct drm_plane_state
*state
)
670 struct tegra_plane
*tegra
= to_tegra_plane(plane
);
673 /* no need for further checks if the plane is being disabled */
677 /* scaling not supported for cursor */
678 if ((state
->src_w
>> 16 != state
->crtc_w
) ||
679 (state
->src_h
>> 16 != state
->crtc_h
))
682 /* only square cursors supported */
683 if (state
->src_w
!= state
->src_h
)
686 if (state
->crtc_w
!= 32 && state
->crtc_w
!= 64 &&
687 state
->crtc_w
!= 128 && state
->crtc_w
!= 256)
690 err
= tegra_plane_state_add(tegra
, state
);
697 static void tegra_cursor_atomic_update(struct drm_plane
*plane
,
698 struct drm_plane_state
*old_state
)
700 struct tegra_bo
*bo
= tegra_fb_get_plane(plane
->state
->fb
, 0);
701 struct tegra_dc
*dc
= to_tegra_dc(plane
->state
->crtc
);
702 struct drm_plane_state
*state
= plane
->state
;
703 u32 value
= CURSOR_CLIP_DISPLAY
;
705 /* rien ne va plus */
706 if (!plane
->state
->crtc
|| !plane
->state
->fb
)
709 switch (state
->crtc_w
) {
711 value
|= CURSOR_SIZE_32x32
;
715 value
|= CURSOR_SIZE_64x64
;
719 value
|= CURSOR_SIZE_128x128
;
723 value
|= CURSOR_SIZE_256x256
;
727 WARN(1, "cursor size %ux%u not supported\n", state
->crtc_w
,
732 value
|= (bo
->paddr
>> 10) & 0x3fffff;
733 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR
);
735 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
736 value
= (bo
->paddr
>> 32) & 0x3;
737 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR_HI
);
740 /* enable cursor and set blend mode */
741 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
742 value
|= CURSOR_ENABLE
;
743 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
745 value
= tegra_dc_readl(dc
, DC_DISP_BLEND_CURSOR_CONTROL
);
746 value
&= ~CURSOR_DST_BLEND_MASK
;
747 value
&= ~CURSOR_SRC_BLEND_MASK
;
748 value
|= CURSOR_MODE_NORMAL
;
749 value
|= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC
;
750 value
|= CURSOR_SRC_BLEND_K1_TIMES_SRC
;
751 value
|= CURSOR_ALPHA
;
752 tegra_dc_writel(dc
, value
, DC_DISP_BLEND_CURSOR_CONTROL
);
754 /* position the cursor */
755 value
= (state
->crtc_y
& 0x3fff) << 16 | (state
->crtc_x
& 0x3fff);
756 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_POSITION
);
759 static void tegra_cursor_atomic_disable(struct drm_plane
*plane
,
760 struct drm_plane_state
*old_state
)
765 /* rien ne va plus */
766 if (!old_state
|| !old_state
->crtc
)
769 dc
= to_tegra_dc(old_state
->crtc
);
771 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
772 value
&= ~CURSOR_ENABLE
;
773 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
776 static const struct drm_plane_funcs tegra_cursor_plane_funcs
= {
777 .update_plane
= drm_atomic_helper_update_plane
,
778 .disable_plane
= drm_atomic_helper_disable_plane
,
779 .destroy
= tegra_plane_destroy
,
780 .reset
= tegra_plane_reset
,
781 .atomic_duplicate_state
= tegra_plane_atomic_duplicate_state
,
782 .atomic_destroy_state
= tegra_plane_atomic_destroy_state
,
785 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs
= {
786 .atomic_check
= tegra_cursor_atomic_check
,
787 .atomic_update
= tegra_cursor_atomic_update
,
788 .atomic_disable
= tegra_cursor_atomic_disable
,
791 static struct drm_plane
*tegra_dc_cursor_plane_create(struct drm_device
*drm
,
794 struct tegra_plane
*plane
;
795 unsigned int num_formats
;
799 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
801 return ERR_PTR(-ENOMEM
);
804 * This index is kind of fake. The cursor isn't a regular plane, but
805 * its update and activation request bits in DC_CMD_STATE_CONTROL do
806 * use the same programming. Setting this fake index here allows the
807 * code in tegra_add_plane_state() to do the right thing without the
808 * need to special-casing the cursor plane.
812 num_formats
= ARRAY_SIZE(tegra_cursor_plane_formats
);
813 formats
= tegra_cursor_plane_formats
;
815 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
816 &tegra_cursor_plane_funcs
, formats
,
817 num_formats
, DRM_PLANE_TYPE_CURSOR
,
824 drm_plane_helper_add(&plane
->base
, &tegra_cursor_plane_helper_funcs
);
829 static void tegra_overlay_plane_destroy(struct drm_plane
*plane
)
831 tegra_plane_destroy(plane
);
834 static const struct drm_plane_funcs tegra_overlay_plane_funcs
= {
835 .update_plane
= drm_atomic_helper_update_plane
,
836 .disable_plane
= drm_atomic_helper_disable_plane
,
837 .destroy
= tegra_overlay_plane_destroy
,
838 .reset
= tegra_plane_reset
,
839 .atomic_duplicate_state
= tegra_plane_atomic_duplicate_state
,
840 .atomic_destroy_state
= tegra_plane_atomic_destroy_state
,
843 static const uint32_t tegra_overlay_plane_formats
[] = {
853 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs
= {
854 .atomic_check
= tegra_plane_atomic_check
,
855 .atomic_update
= tegra_plane_atomic_update
,
856 .atomic_disable
= tegra_plane_atomic_disable
,
859 static struct drm_plane
*tegra_dc_overlay_plane_create(struct drm_device
*drm
,
863 struct tegra_plane
*plane
;
864 unsigned int num_formats
;
868 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
870 return ERR_PTR(-ENOMEM
);
872 plane
->index
= index
;
874 num_formats
= ARRAY_SIZE(tegra_overlay_plane_formats
);
875 formats
= tegra_overlay_plane_formats
;
877 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
878 &tegra_overlay_plane_funcs
, formats
,
879 num_formats
, DRM_PLANE_TYPE_OVERLAY
,
886 drm_plane_helper_add(&plane
->base
, &tegra_overlay_plane_helper_funcs
);
891 static int tegra_dc_add_planes(struct drm_device
*drm
, struct tegra_dc
*dc
)
893 struct drm_plane
*plane
;
896 for (i
= 0; i
< 2; i
++) {
897 plane
= tegra_dc_overlay_plane_create(drm
, dc
, 1 + i
);
899 return PTR_ERR(plane
);
905 u32
tegra_dc_get_vblank_counter(struct tegra_dc
*dc
)
908 return host1x_syncpt_read(dc
->syncpt
);
910 /* fallback to software emulated VBLANK counter */
911 return drm_crtc_vblank_count(&dc
->base
);
914 void tegra_dc_enable_vblank(struct tegra_dc
*dc
)
916 unsigned long value
, flags
;
918 spin_lock_irqsave(&dc
->lock
, flags
);
920 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
922 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
924 spin_unlock_irqrestore(&dc
->lock
, flags
);
927 void tegra_dc_disable_vblank(struct tegra_dc
*dc
)
929 unsigned long value
, flags
;
931 spin_lock_irqsave(&dc
->lock
, flags
);
933 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
934 value
&= ~VBLANK_INT
;
935 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
937 spin_unlock_irqrestore(&dc
->lock
, flags
);
940 static void tegra_dc_finish_page_flip(struct tegra_dc
*dc
)
942 struct drm_device
*drm
= dc
->base
.dev
;
943 struct drm_crtc
*crtc
= &dc
->base
;
944 unsigned long flags
, base
;
947 spin_lock_irqsave(&drm
->event_lock
, flags
);
950 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
954 bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
956 spin_lock(&dc
->lock
);
958 /* check if new start address has been latched */
959 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
960 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
961 base
= tegra_dc_readl(dc
, DC_WINBUF_START_ADDR
);
962 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
964 spin_unlock(&dc
->lock
);
966 if (base
== bo
->paddr
+ crtc
->primary
->fb
->offsets
[0]) {
967 drm_crtc_send_vblank_event(crtc
, dc
->event
);
968 drm_crtc_vblank_put(crtc
);
972 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
975 static void tegra_dc_destroy(struct drm_crtc
*crtc
)
977 drm_crtc_cleanup(crtc
);
980 static void tegra_crtc_reset(struct drm_crtc
*crtc
)
982 struct tegra_dc_state
*state
;
985 __drm_atomic_helper_crtc_destroy_state(crtc
->state
);
990 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
992 crtc
->state
= &state
->base
;
993 crtc
->state
->crtc
= crtc
;
996 drm_crtc_vblank_reset(crtc
);
999 static struct drm_crtc_state
*
1000 tegra_crtc_atomic_duplicate_state(struct drm_crtc
*crtc
)
1002 struct tegra_dc_state
*state
= to_dc_state(crtc
->state
);
1003 struct tegra_dc_state
*copy
;
1005 copy
= kmalloc(sizeof(*copy
), GFP_KERNEL
);
1009 __drm_atomic_helper_crtc_duplicate_state(crtc
, ©
->base
);
1010 copy
->clk
= state
->clk
;
1011 copy
->pclk
= state
->pclk
;
1012 copy
->div
= state
->div
;
1013 copy
->planes
= state
->planes
;
1018 static void tegra_crtc_atomic_destroy_state(struct drm_crtc
*crtc
,
1019 struct drm_crtc_state
*state
)
1021 __drm_atomic_helper_crtc_destroy_state(state
);
1025 static const struct drm_crtc_funcs tegra_crtc_funcs
= {
1026 .page_flip
= drm_atomic_helper_page_flip
,
1027 .set_config
= drm_atomic_helper_set_config
,
1028 .destroy
= tegra_dc_destroy
,
1029 .reset
= tegra_crtc_reset
,
1030 .atomic_duplicate_state
= tegra_crtc_atomic_duplicate_state
,
1031 .atomic_destroy_state
= tegra_crtc_atomic_destroy_state
,
1034 static int tegra_dc_set_timings(struct tegra_dc
*dc
,
1035 struct drm_display_mode
*mode
)
1037 unsigned int h_ref_to_sync
= 1;
1038 unsigned int v_ref_to_sync
= 1;
1039 unsigned long value
;
1041 tegra_dc_writel(dc
, 0x0, DC_DISP_DISP_TIMING_OPTIONS
);
1043 value
= (v_ref_to_sync
<< 16) | h_ref_to_sync
;
1044 tegra_dc_writel(dc
, value
, DC_DISP_REF_TO_SYNC
);
1046 value
= ((mode
->vsync_end
- mode
->vsync_start
) << 16) |
1047 ((mode
->hsync_end
- mode
->hsync_start
) << 0);
1048 tegra_dc_writel(dc
, value
, DC_DISP_SYNC_WIDTH
);
1050 value
= ((mode
->vtotal
- mode
->vsync_end
) << 16) |
1051 ((mode
->htotal
- mode
->hsync_end
) << 0);
1052 tegra_dc_writel(dc
, value
, DC_DISP_BACK_PORCH
);
1054 value
= ((mode
->vsync_start
- mode
->vdisplay
) << 16) |
1055 ((mode
->hsync_start
- mode
->hdisplay
) << 0);
1056 tegra_dc_writel(dc
, value
, DC_DISP_FRONT_PORCH
);
1058 value
= (mode
->vdisplay
<< 16) | mode
->hdisplay
;
1059 tegra_dc_writel(dc
, value
, DC_DISP_ACTIVE
);
1065 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1067 * @dc: display controller
1068 * @crtc_state: CRTC atomic state
1069 * @clk: parent clock for display controller
1070 * @pclk: pixel clock
1071 * @div: shift clock divider
1074 * 0 on success or a negative error-code on failure.
1076 int tegra_dc_state_setup_clock(struct tegra_dc
*dc
,
1077 struct drm_crtc_state
*crtc_state
,
1078 struct clk
*clk
, unsigned long pclk
,
1081 struct tegra_dc_state
*state
= to_dc_state(crtc_state
);
1083 if (!clk_has_parent(dc
->clk
, clk
))
1093 static void tegra_dc_commit_state(struct tegra_dc
*dc
,
1094 struct tegra_dc_state
*state
)
1099 err
= clk_set_parent(dc
->clk
, state
->clk
);
1101 dev_err(dc
->dev
, "failed to set parent clock: %d\n", err
);
1104 * Outputs may not want to change the parent clock rate. This is only
1105 * relevant to Tegra20 where only a single display PLL is available.
1106 * Since that PLL would typically be used for HDMI, an internal LVDS
1107 * panel would need to be driven by some other clock such as PLL_P
1108 * which is shared with other peripherals. Changing the clock rate
1109 * should therefore be avoided.
1111 if (state
->pclk
> 0) {
1112 err
= clk_set_rate(state
->clk
, state
->pclk
);
1115 "failed to set clock rate to %lu Hz\n",
1119 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc
->clk
),
1121 DRM_DEBUG_KMS("pclk: %lu\n", state
->pclk
);
1123 value
= SHIFT_CLK_DIVIDER(state
->div
) | PIXEL_CLK_DIVIDER_PCD1
;
1124 tegra_dc_writel(dc
, value
, DC_DISP_DISP_CLOCK_CONTROL
);
1127 static void tegra_dc_stop(struct tegra_dc
*dc
)
1131 /* stop the display controller */
1132 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_COMMAND
);
1133 value
&= ~DISP_CTRL_MODE_MASK
;
1134 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_COMMAND
);
1136 tegra_dc_commit(dc
);
1139 static bool tegra_dc_idle(struct tegra_dc
*dc
)
1143 value
= tegra_dc_readl_active(dc
, DC_CMD_DISPLAY_COMMAND
);
1145 return (value
& DISP_CTRL_MODE_MASK
) == 0;
1148 static int tegra_dc_wait_idle(struct tegra_dc
*dc
, unsigned long timeout
)
1150 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
1152 while (time_before(jiffies
, timeout
)) {
1153 if (tegra_dc_idle(dc
))
1156 usleep_range(1000, 2000);
1159 dev_dbg(dc
->dev
, "timeout waiting for DC to become idle\n");
1163 static void tegra_crtc_disable(struct drm_crtc
*crtc
)
1165 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1168 if (!tegra_dc_idle(dc
)) {
1172 * Ignore the return value, there isn't anything useful to do
1173 * in case this fails.
1175 tegra_dc_wait_idle(dc
, 100);
1179 * This should really be part of the RGB encoder driver, but clearing
1180 * these bits has the side-effect of stopping the display controller.
1181 * When that happens no VBLANK interrupts will be raised. At the same
1182 * time the encoder is disabled before the display controller, so the
1183 * above code is always going to timeout waiting for the controller
1186 * Given the close coupling between the RGB encoder and the display
1187 * controller doing it here is still kind of okay. None of the other
1188 * encoder drivers require these bits to be cleared.
1190 * XXX: Perhaps given that the display controller is switched off at
1191 * this point anyway maybe clearing these bits isn't even useful for
1195 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_POWER_CONTROL
);
1196 value
&= ~(PW0_ENABLE
| PW1_ENABLE
| PW2_ENABLE
| PW3_ENABLE
|
1197 PW4_ENABLE
| PM0_ENABLE
| PM1_ENABLE
);
1198 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_POWER_CONTROL
);
1201 tegra_dc_stats_reset(&dc
->stats
);
1202 drm_crtc_vblank_off(crtc
);
1204 pm_runtime_put_sync(dc
->dev
);
1207 static void tegra_crtc_enable(struct drm_crtc
*crtc
)
1209 struct drm_display_mode
*mode
= &crtc
->state
->adjusted_mode
;
1210 struct tegra_dc_state
*state
= to_dc_state(crtc
->state
);
1211 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1214 pm_runtime_get_sync(dc
->dev
);
1216 /* initialize display controller */
1218 u32 syncpt
= host1x_syncpt_id(dc
->syncpt
);
1220 value
= SYNCPT_CNTRL_NO_STALL
;
1221 tegra_dc_writel(dc
, value
, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1223 value
= SYNCPT_VSYNC_ENABLE
| syncpt
;
1224 tegra_dc_writel(dc
, value
, DC_CMD_CONT_SYNCPT_VSYNC
);
1227 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
1228 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
1229 tegra_dc_writel(dc
, value
, DC_CMD_INT_TYPE
);
1231 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
1232 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
1233 tegra_dc_writel(dc
, value
, DC_CMD_INT_POLARITY
);
1235 /* initialize timer */
1236 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1237 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1238 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1240 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1241 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1242 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1244 value
= VBLANK_INT
| WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
1245 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
1246 tegra_dc_writel(dc
, value
, DC_CMD_INT_ENABLE
);
1248 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
1249 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
1250 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
1252 if (dc
->soc
->supports_border_color
)
1253 tegra_dc_writel(dc
, 0, DC_DISP_BORDER_COLOR
);
1255 /* apply PLL and pixel clock changes */
1256 tegra_dc_commit_state(dc
, state
);
1258 /* program display mode */
1259 tegra_dc_set_timings(dc
, mode
);
1261 /* interlacing isn't supported yet, so disable it */
1262 if (dc
->soc
->supports_interlacing
) {
1263 value
= tegra_dc_readl(dc
, DC_DISP_INTERLACE_CONTROL
);
1264 value
&= ~INTERLACE_ENABLE
;
1265 tegra_dc_writel(dc
, value
, DC_DISP_INTERLACE_CONTROL
);
1268 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_COMMAND
);
1269 value
&= ~DISP_CTRL_MODE_MASK
;
1270 value
|= DISP_CTRL_MODE_C_DISPLAY
;
1271 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_COMMAND
);
1273 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_POWER_CONTROL
);
1274 value
|= PW0_ENABLE
| PW1_ENABLE
| PW2_ENABLE
| PW3_ENABLE
|
1275 PW4_ENABLE
| PM0_ENABLE
| PM1_ENABLE
;
1276 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_POWER_CONTROL
);
1278 tegra_dc_commit(dc
);
1280 drm_crtc_vblank_on(crtc
);
1283 static int tegra_crtc_atomic_check(struct drm_crtc
*crtc
,
1284 struct drm_crtc_state
*state
)
1289 static void tegra_crtc_atomic_begin(struct drm_crtc
*crtc
,
1290 struct drm_crtc_state
*old_crtc_state
)
1292 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1294 if (crtc
->state
->event
) {
1295 crtc
->state
->event
->pipe
= drm_crtc_index(crtc
);
1297 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
1299 dc
->event
= crtc
->state
->event
;
1300 crtc
->state
->event
= NULL
;
1304 static void tegra_crtc_atomic_flush(struct drm_crtc
*crtc
,
1305 struct drm_crtc_state
*old_crtc_state
)
1307 struct tegra_dc_state
*state
= to_dc_state(crtc
->state
);
1308 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1310 tegra_dc_writel(dc
, state
->planes
<< 8, DC_CMD_STATE_CONTROL
);
1311 tegra_dc_writel(dc
, state
->planes
, DC_CMD_STATE_CONTROL
);
1314 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs
= {
1315 .disable
= tegra_crtc_disable
,
1316 .enable
= tegra_crtc_enable
,
1317 .atomic_check
= tegra_crtc_atomic_check
,
1318 .atomic_begin
= tegra_crtc_atomic_begin
,
1319 .atomic_flush
= tegra_crtc_atomic_flush
,
1322 static irqreturn_t
tegra_dc_irq(int irq
, void *data
)
1324 struct tegra_dc
*dc
= data
;
1325 unsigned long status
;
1327 status
= tegra_dc_readl(dc
, DC_CMD_INT_STATUS
);
1328 tegra_dc_writel(dc
, status
, DC_CMD_INT_STATUS
);
1330 if (status
& FRAME_END_INT
) {
1332 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1337 if (status
& VBLANK_INT
) {
1339 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1341 drm_crtc_handle_vblank(&dc
->base
);
1342 tegra_dc_finish_page_flip(dc
);
1346 if (status
& (WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
)) {
1348 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1350 dc
->stats
.underflow
++;
1353 if (status
& (WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
)) {
1355 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1357 dc
->stats
.overflow
++;
1363 static int tegra_dc_show_regs(struct seq_file
*s
, void *data
)
1365 struct drm_info_node
*node
= s
->private;
1366 struct tegra_dc
*dc
= node
->info_ent
->data
;
1369 drm_modeset_lock_crtc(&dc
->base
, NULL
);
1371 if (!dc
->base
.state
->active
) {
1376 #define DUMP_REG(name) \
1377 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1378 tegra_dc_readl(dc, name))
1380 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT
);
1381 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1382 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR
);
1383 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT
);
1384 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL
);
1385 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR
);
1386 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT
);
1387 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL
);
1388 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR
);
1389 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT
);
1390 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL
);
1391 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR
);
1392 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC
);
1393 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0
);
1394 DUMP_REG(DC_CMD_DISPLAY_COMMAND
);
1395 DUMP_REG(DC_CMD_SIGNAL_RAISE
);
1396 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL
);
1397 DUMP_REG(DC_CMD_INT_STATUS
);
1398 DUMP_REG(DC_CMD_INT_MASK
);
1399 DUMP_REG(DC_CMD_INT_ENABLE
);
1400 DUMP_REG(DC_CMD_INT_TYPE
);
1401 DUMP_REG(DC_CMD_INT_POLARITY
);
1402 DUMP_REG(DC_CMD_SIGNAL_RAISE1
);
1403 DUMP_REG(DC_CMD_SIGNAL_RAISE2
);
1404 DUMP_REG(DC_CMD_SIGNAL_RAISE3
);
1405 DUMP_REG(DC_CMD_STATE_ACCESS
);
1406 DUMP_REG(DC_CMD_STATE_CONTROL
);
1407 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER
);
1408 DUMP_REG(DC_CMD_REG_ACT_CONTROL
);
1409 DUMP_REG(DC_COM_CRC_CONTROL
);
1410 DUMP_REG(DC_COM_CRC_CHECKSUM
);
1411 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1412 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1413 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1414 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1415 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1416 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1417 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1418 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1419 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1420 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1421 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1422 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1423 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1424 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1425 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1426 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1427 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1428 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1429 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1430 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1431 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1432 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1433 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1434 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1435 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1436 DUMP_REG(DC_COM_PIN_MISC_CONTROL
);
1437 DUMP_REG(DC_COM_PIN_PM0_CONTROL
);
1438 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE
);
1439 DUMP_REG(DC_COM_PIN_PM1_CONTROL
);
1440 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE
);
1441 DUMP_REG(DC_COM_SPI_CONTROL
);
1442 DUMP_REG(DC_COM_SPI_START_BYTE
);
1443 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB
);
1444 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD
);
1445 DUMP_REG(DC_COM_HSPI_CS_DC
);
1446 DUMP_REG(DC_COM_SCRATCH_REGISTER_A
);
1447 DUMP_REG(DC_COM_SCRATCH_REGISTER_B
);
1448 DUMP_REG(DC_COM_GPIO_CTRL
);
1449 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER
);
1450 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED
);
1451 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0
);
1452 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1
);
1453 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS
);
1454 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1455 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1456 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS
);
1457 DUMP_REG(DC_DISP_REF_TO_SYNC
);
1458 DUMP_REG(DC_DISP_SYNC_WIDTH
);
1459 DUMP_REG(DC_DISP_BACK_PORCH
);
1460 DUMP_REG(DC_DISP_ACTIVE
);
1461 DUMP_REG(DC_DISP_FRONT_PORCH
);
1462 DUMP_REG(DC_DISP_H_PULSE0_CONTROL
);
1463 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A
);
1464 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B
);
1465 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C
);
1466 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D
);
1467 DUMP_REG(DC_DISP_H_PULSE1_CONTROL
);
1468 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A
);
1469 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B
);
1470 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C
);
1471 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D
);
1472 DUMP_REG(DC_DISP_H_PULSE2_CONTROL
);
1473 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A
);
1474 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B
);
1475 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C
);
1476 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D
);
1477 DUMP_REG(DC_DISP_V_PULSE0_CONTROL
);
1478 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A
);
1479 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B
);
1480 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C
);
1481 DUMP_REG(DC_DISP_V_PULSE1_CONTROL
);
1482 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A
);
1483 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B
);
1484 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C
);
1485 DUMP_REG(DC_DISP_V_PULSE2_CONTROL
);
1486 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A
);
1487 DUMP_REG(DC_DISP_V_PULSE3_CONTROL
);
1488 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A
);
1489 DUMP_REG(DC_DISP_M0_CONTROL
);
1490 DUMP_REG(DC_DISP_M1_CONTROL
);
1491 DUMP_REG(DC_DISP_DI_CONTROL
);
1492 DUMP_REG(DC_DISP_PP_CONTROL
);
1493 DUMP_REG(DC_DISP_PP_SELECT_A
);
1494 DUMP_REG(DC_DISP_PP_SELECT_B
);
1495 DUMP_REG(DC_DISP_PP_SELECT_C
);
1496 DUMP_REG(DC_DISP_PP_SELECT_D
);
1497 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL
);
1498 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL
);
1499 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL
);
1500 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS
);
1501 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS
);
1502 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS
);
1503 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS
);
1504 DUMP_REG(DC_DISP_BORDER_COLOR
);
1505 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER
);
1506 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER
);
1507 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER
);
1508 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER
);
1509 DUMP_REG(DC_DISP_CURSOR_FOREGROUND
);
1510 DUMP_REG(DC_DISP_CURSOR_BACKGROUND
);
1511 DUMP_REG(DC_DISP_CURSOR_START_ADDR
);
1512 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS
);
1513 DUMP_REG(DC_DISP_CURSOR_POSITION
);
1514 DUMP_REG(DC_DISP_CURSOR_POSITION_NS
);
1515 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL
);
1516 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A
);
1517 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B
);
1518 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C
);
1519 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D
);
1520 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL
);
1521 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST
);
1522 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST
);
1523 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST
);
1524 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST
);
1525 DUMP_REG(DC_DISP_DAC_CRT_CTRL
);
1526 DUMP_REG(DC_DISP_DISP_MISC_CONTROL
);
1527 DUMP_REG(DC_DISP_SD_CONTROL
);
1528 DUMP_REG(DC_DISP_SD_CSC_COEFF
);
1529 DUMP_REG(DC_DISP_SD_LUT(0));
1530 DUMP_REG(DC_DISP_SD_LUT(1));
1531 DUMP_REG(DC_DISP_SD_LUT(2));
1532 DUMP_REG(DC_DISP_SD_LUT(3));
1533 DUMP_REG(DC_DISP_SD_LUT(4));
1534 DUMP_REG(DC_DISP_SD_LUT(5));
1535 DUMP_REG(DC_DISP_SD_LUT(6));
1536 DUMP_REG(DC_DISP_SD_LUT(7));
1537 DUMP_REG(DC_DISP_SD_LUT(8));
1538 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL
);
1539 DUMP_REG(DC_DISP_DC_PIXEL_COUNT
);
1540 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1541 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1542 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1543 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1544 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1545 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1546 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1547 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1548 DUMP_REG(DC_DISP_SD_BL_TF(0));
1549 DUMP_REG(DC_DISP_SD_BL_TF(1));
1550 DUMP_REG(DC_DISP_SD_BL_TF(2));
1551 DUMP_REG(DC_DISP_SD_BL_TF(3));
1552 DUMP_REG(DC_DISP_SD_BL_CONTROL
);
1553 DUMP_REG(DC_DISP_SD_HW_K_VALUES
);
1554 DUMP_REG(DC_DISP_SD_MAN_K_VALUES
);
1555 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI
);
1556 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL
);
1557 DUMP_REG(DC_WIN_WIN_OPTIONS
);
1558 DUMP_REG(DC_WIN_BYTE_SWAP
);
1559 DUMP_REG(DC_WIN_BUFFER_CONTROL
);
1560 DUMP_REG(DC_WIN_COLOR_DEPTH
);
1561 DUMP_REG(DC_WIN_POSITION
);
1562 DUMP_REG(DC_WIN_SIZE
);
1563 DUMP_REG(DC_WIN_PRESCALED_SIZE
);
1564 DUMP_REG(DC_WIN_H_INITIAL_DDA
);
1565 DUMP_REG(DC_WIN_V_INITIAL_DDA
);
1566 DUMP_REG(DC_WIN_DDA_INC
);
1567 DUMP_REG(DC_WIN_LINE_STRIDE
);
1568 DUMP_REG(DC_WIN_BUF_STRIDE
);
1569 DUMP_REG(DC_WIN_UV_BUF_STRIDE
);
1570 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE
);
1571 DUMP_REG(DC_WIN_DV_CONTROL
);
1572 DUMP_REG(DC_WIN_BLEND_NOKEY
);
1573 DUMP_REG(DC_WIN_BLEND_1WIN
);
1574 DUMP_REG(DC_WIN_BLEND_2WIN_X
);
1575 DUMP_REG(DC_WIN_BLEND_2WIN_Y
);
1576 DUMP_REG(DC_WIN_BLEND_3WIN_XY
);
1577 DUMP_REG(DC_WIN_HP_FETCH_CONTROL
);
1578 DUMP_REG(DC_WINBUF_START_ADDR
);
1579 DUMP_REG(DC_WINBUF_START_ADDR_NS
);
1580 DUMP_REG(DC_WINBUF_START_ADDR_U
);
1581 DUMP_REG(DC_WINBUF_START_ADDR_U_NS
);
1582 DUMP_REG(DC_WINBUF_START_ADDR_V
);
1583 DUMP_REG(DC_WINBUF_START_ADDR_V_NS
);
1584 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET
);
1585 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS
);
1586 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET
);
1587 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS
);
1588 DUMP_REG(DC_WINBUF_UFLOW_STATUS
);
1589 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS
);
1590 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS
);
1591 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS
);
1596 drm_modeset_unlock_crtc(&dc
->base
);
1600 static int tegra_dc_show_crc(struct seq_file
*s
, void *data
)
1602 struct drm_info_node
*node
= s
->private;
1603 struct tegra_dc
*dc
= node
->info_ent
->data
;
1607 drm_modeset_lock_crtc(&dc
->base
, NULL
);
1609 if (!dc
->base
.state
->active
) {
1614 value
= DC_COM_CRC_CONTROL_ACTIVE_DATA
| DC_COM_CRC_CONTROL_ENABLE
;
1615 tegra_dc_writel(dc
, value
, DC_COM_CRC_CONTROL
);
1616 tegra_dc_commit(dc
);
1618 drm_crtc_wait_one_vblank(&dc
->base
);
1619 drm_crtc_wait_one_vblank(&dc
->base
);
1621 value
= tegra_dc_readl(dc
, DC_COM_CRC_CHECKSUM
);
1622 seq_printf(s
, "%08x\n", value
);
1624 tegra_dc_writel(dc
, 0, DC_COM_CRC_CONTROL
);
1627 drm_modeset_unlock_crtc(&dc
->base
);
1631 static int tegra_dc_show_stats(struct seq_file
*s
, void *data
)
1633 struct drm_info_node
*node
= s
->private;
1634 struct tegra_dc
*dc
= node
->info_ent
->data
;
1636 seq_printf(s
, "frames: %lu\n", dc
->stats
.frames
);
1637 seq_printf(s
, "vblank: %lu\n", dc
->stats
.vblank
);
1638 seq_printf(s
, "underflow: %lu\n", dc
->stats
.underflow
);
1639 seq_printf(s
, "overflow: %lu\n", dc
->stats
.overflow
);
1644 static struct drm_info_list debugfs_files
[] = {
1645 { "regs", tegra_dc_show_regs
, 0, NULL
},
1646 { "crc", tegra_dc_show_crc
, 0, NULL
},
1647 { "stats", tegra_dc_show_stats
, 0, NULL
},
1650 static int tegra_dc_debugfs_init(struct tegra_dc
*dc
, struct drm_minor
*minor
)
1656 name
= kasprintf(GFP_KERNEL
, "dc.%d", dc
->pipe
);
1657 dc
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
1663 dc
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
1665 if (!dc
->debugfs_files
) {
1670 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
1671 dc
->debugfs_files
[i
].data
= dc
;
1673 err
= drm_debugfs_create_files(dc
->debugfs_files
,
1674 ARRAY_SIZE(debugfs_files
),
1675 dc
->debugfs
, minor
);
1684 kfree(dc
->debugfs_files
);
1685 dc
->debugfs_files
= NULL
;
1687 debugfs_remove(dc
->debugfs
);
1693 static int tegra_dc_debugfs_exit(struct tegra_dc
*dc
)
1695 drm_debugfs_remove_files(dc
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
1699 kfree(dc
->debugfs_files
);
1700 dc
->debugfs_files
= NULL
;
1702 debugfs_remove(dc
->debugfs
);
1708 static int tegra_dc_init(struct host1x_client
*client
)
1710 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
1711 unsigned long flags
= HOST1X_SYNCPT_CLIENT_MANAGED
;
1712 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1713 struct tegra_drm
*tegra
= drm
->dev_private
;
1714 struct drm_plane
*primary
= NULL
;
1715 struct drm_plane
*cursor
= NULL
;
1718 dc
->syncpt
= host1x_syncpt_request(dc
->dev
, flags
);
1720 dev_warn(dc
->dev
, "failed to allocate syncpoint\n");
1722 if (tegra
->domain
) {
1723 err
= iommu_attach_device(tegra
->domain
, dc
->dev
);
1725 dev_err(dc
->dev
, "failed to attach to domain: %d\n",
1730 dc
->domain
= tegra
->domain
;
1733 primary
= tegra_dc_primary_plane_create(drm
, dc
);
1734 if (IS_ERR(primary
)) {
1735 err
= PTR_ERR(primary
);
1739 if (dc
->soc
->supports_cursor
) {
1740 cursor
= tegra_dc_cursor_plane_create(drm
, dc
);
1741 if (IS_ERR(cursor
)) {
1742 err
= PTR_ERR(cursor
);
1747 err
= drm_crtc_init_with_planes(drm
, &dc
->base
, primary
, cursor
,
1748 &tegra_crtc_funcs
, NULL
);
1752 drm_crtc_helper_add(&dc
->base
, &tegra_crtc_helper_funcs
);
1755 * Keep track of the minimum pitch alignment across all display
1758 if (dc
->soc
->pitch_align
> tegra
->pitch_align
)
1759 tegra
->pitch_align
= dc
->soc
->pitch_align
;
1761 err
= tegra_dc_rgb_init(drm
, dc
);
1762 if (err
< 0 && err
!= -ENODEV
) {
1763 dev_err(dc
->dev
, "failed to initialize RGB output: %d\n", err
);
1767 err
= tegra_dc_add_planes(drm
, dc
);
1771 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1772 err
= tegra_dc_debugfs_init(dc
, drm
->primary
);
1774 dev_err(dc
->dev
, "debugfs setup failed: %d\n", err
);
1777 err
= devm_request_irq(dc
->dev
, dc
->irq
, tegra_dc_irq
, 0,
1778 dev_name(dc
->dev
), dc
);
1780 dev_err(dc
->dev
, "failed to request IRQ#%u: %d\n", dc
->irq
,
1789 drm_plane_cleanup(cursor
);
1792 drm_plane_cleanup(primary
);
1794 if (tegra
->domain
) {
1795 iommu_detach_device(tegra
->domain
, dc
->dev
);
1802 static int tegra_dc_exit(struct host1x_client
*client
)
1804 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1807 devm_free_irq(dc
->dev
, dc
->irq
, dc
);
1809 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1810 err
= tegra_dc_debugfs_exit(dc
);
1812 dev_err(dc
->dev
, "debugfs cleanup failed: %d\n", err
);
1815 err
= tegra_dc_rgb_exit(dc
);
1817 dev_err(dc
->dev
, "failed to shutdown RGB output: %d\n", err
);
1822 iommu_detach_device(dc
->domain
, dc
->dev
);
1826 host1x_syncpt_free(dc
->syncpt
);
1831 static const struct host1x_client_ops dc_client_ops
= {
1832 .init
= tegra_dc_init
,
1833 .exit
= tegra_dc_exit
,
1836 static const struct tegra_dc_soc_info tegra20_dc_soc_info
= {
1837 .supports_border_color
= true,
1838 .supports_interlacing
= false,
1839 .supports_cursor
= false,
1840 .supports_block_linear
= false,
1842 .has_powergate
= false,
1845 static const struct tegra_dc_soc_info tegra30_dc_soc_info
= {
1846 .supports_border_color
= true,
1847 .supports_interlacing
= false,
1848 .supports_cursor
= false,
1849 .supports_block_linear
= false,
1851 .has_powergate
= false,
1854 static const struct tegra_dc_soc_info tegra114_dc_soc_info
= {
1855 .supports_border_color
= true,
1856 .supports_interlacing
= false,
1857 .supports_cursor
= false,
1858 .supports_block_linear
= false,
1860 .has_powergate
= true,
1863 static const struct tegra_dc_soc_info tegra124_dc_soc_info
= {
1864 .supports_border_color
= false,
1865 .supports_interlacing
= true,
1866 .supports_cursor
= true,
1867 .supports_block_linear
= true,
1869 .has_powergate
= true,
1872 static const struct tegra_dc_soc_info tegra210_dc_soc_info
= {
1873 .supports_border_color
= false,
1874 .supports_interlacing
= true,
1875 .supports_cursor
= true,
1876 .supports_block_linear
= true,
1878 .has_powergate
= true,
1881 static const struct of_device_id tegra_dc_of_match
[] = {
1883 .compatible
= "nvidia,tegra210-dc",
1884 .data
= &tegra210_dc_soc_info
,
1886 .compatible
= "nvidia,tegra124-dc",
1887 .data
= &tegra124_dc_soc_info
,
1889 .compatible
= "nvidia,tegra114-dc",
1890 .data
= &tegra114_dc_soc_info
,
1892 .compatible
= "nvidia,tegra30-dc",
1893 .data
= &tegra30_dc_soc_info
,
1895 .compatible
= "nvidia,tegra20-dc",
1896 .data
= &tegra20_dc_soc_info
,
1901 MODULE_DEVICE_TABLE(of
, tegra_dc_of_match
);
1903 static int tegra_dc_parse_dt(struct tegra_dc
*dc
)
1905 struct device_node
*np
;
1909 err
= of_property_read_u32(dc
->dev
->of_node
, "nvidia,head", &value
);
1911 dev_err(dc
->dev
, "missing \"nvidia,head\" property\n");
1914 * If the nvidia,head property isn't present, try to find the
1915 * correct head number by looking up the position of this
1916 * display controller's node within the device tree. Assuming
1917 * that the nodes are ordered properly in the DTS file and
1918 * that the translation into a flattened device tree blob
1919 * preserves that ordering this will actually yield the right
1922 * If those assumptions don't hold, this will still work for
1923 * cases where only a single display controller is used.
1925 for_each_matching_node(np
, tegra_dc_of_match
) {
1926 if (np
== dc
->dev
->of_node
) {
1940 static int tegra_dc_probe(struct platform_device
*pdev
)
1942 const struct of_device_id
*id
;
1943 struct resource
*regs
;
1944 struct tegra_dc
*dc
;
1947 dc
= devm_kzalloc(&pdev
->dev
, sizeof(*dc
), GFP_KERNEL
);
1951 id
= of_match_node(tegra_dc_of_match
, pdev
->dev
.of_node
);
1955 spin_lock_init(&dc
->lock
);
1956 INIT_LIST_HEAD(&dc
->list
);
1957 dc
->dev
= &pdev
->dev
;
1960 err
= tegra_dc_parse_dt(dc
);
1964 dc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1965 if (IS_ERR(dc
->clk
)) {
1966 dev_err(&pdev
->dev
, "failed to get clock\n");
1967 return PTR_ERR(dc
->clk
);
1970 dc
->rst
= devm_reset_control_get(&pdev
->dev
, "dc");
1971 if (IS_ERR(dc
->rst
)) {
1972 dev_err(&pdev
->dev
, "failed to get reset\n");
1973 return PTR_ERR(dc
->rst
);
1976 reset_control_assert(dc
->rst
);
1978 if (dc
->soc
->has_powergate
) {
1980 dc
->powergate
= TEGRA_POWERGATE_DIS
;
1982 dc
->powergate
= TEGRA_POWERGATE_DISB
;
1984 tegra_powergate_power_off(dc
->powergate
);
1987 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1988 dc
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1989 if (IS_ERR(dc
->regs
))
1990 return PTR_ERR(dc
->regs
);
1992 dc
->irq
= platform_get_irq(pdev
, 0);
1994 dev_err(&pdev
->dev
, "failed to get IRQ\n");
1998 err
= tegra_dc_rgb_probe(dc
);
1999 if (err
< 0 && err
!= -ENODEV
) {
2000 dev_err(&pdev
->dev
, "failed to probe RGB output: %d\n", err
);
2004 platform_set_drvdata(pdev
, dc
);
2005 pm_runtime_enable(&pdev
->dev
);
2007 INIT_LIST_HEAD(&dc
->client
.list
);
2008 dc
->client
.ops
= &dc_client_ops
;
2009 dc
->client
.dev
= &pdev
->dev
;
2011 err
= host1x_client_register(&dc
->client
);
2013 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
2021 static int tegra_dc_remove(struct platform_device
*pdev
)
2023 struct tegra_dc
*dc
= platform_get_drvdata(pdev
);
2026 err
= host1x_client_unregister(&dc
->client
);
2028 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
2033 err
= tegra_dc_rgb_remove(dc
);
2035 dev_err(&pdev
->dev
, "failed to remove RGB output: %d\n", err
);
2039 pm_runtime_disable(&pdev
->dev
);
2045 static int tegra_dc_suspend(struct device
*dev
)
2047 struct tegra_dc
*dc
= dev_get_drvdata(dev
);
2050 err
= reset_control_assert(dc
->rst
);
2052 dev_err(dev
, "failed to assert reset: %d\n", err
);
2056 if (dc
->soc
->has_powergate
)
2057 tegra_powergate_power_off(dc
->powergate
);
2059 clk_disable_unprepare(dc
->clk
);
2064 static int tegra_dc_resume(struct device
*dev
)
2066 struct tegra_dc
*dc
= dev_get_drvdata(dev
);
2069 if (dc
->soc
->has_powergate
) {
2070 err
= tegra_powergate_sequence_power_up(dc
->powergate
, dc
->clk
,
2073 dev_err(dev
, "failed to power partition: %d\n", err
);
2077 err
= clk_prepare_enable(dc
->clk
);
2079 dev_err(dev
, "failed to enable clock: %d\n", err
);
2083 err
= reset_control_deassert(dc
->rst
);
2085 dev_err(dev
, "failed to deassert reset: %d\n", err
);
2094 static const struct dev_pm_ops tegra_dc_pm_ops
= {
2095 SET_RUNTIME_PM_OPS(tegra_dc_suspend
, tegra_dc_resume
, NULL
)
2098 struct platform_driver tegra_dc_driver
= {
2101 .of_match_table
= tegra_dc_of_match
,
2102 .pm
= &tegra_dc_pm_ops
,
2104 .probe
= tegra_dc_probe
,
2105 .remove
= tegra_dc_remove
,