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drm/tegra: dsi: Soft-reset controller on ->disable
[deliverable/linux.git] / drivers / gpu / drm / tegra / dsi.c
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17
18 #include <linux/regulator/consumer.h>
19
20 #include <drm/drm_mipi_dsi.h>
21 #include <drm/drm_panel.h>
22
23 #include <video/mipi_display.h>
24
25 #include "dc.h"
26 #include "drm.h"
27 #include "dsi.h"
28 #include "mipi-phy.h"
29
30 struct tegra_dsi {
31 struct host1x_client client;
32 struct tegra_output output;
33 struct device *dev;
34
35 void __iomem *regs;
36
37 struct reset_control *rst;
38 struct clk *clk_parent;
39 struct clk *clk_lp;
40 struct clk *clk;
41
42 struct drm_info_list *debugfs_files;
43 struct drm_minor *minor;
44 struct dentry *debugfs;
45
46 unsigned long flags;
47 enum mipi_dsi_pixel_format format;
48 unsigned int lanes;
49
50 struct tegra_mipi_device *mipi;
51 struct mipi_dsi_host host;
52
53 struct regulator *vdd;
54 bool enabled;
55
56 unsigned int video_fifo_depth;
57 unsigned int host_fifo_depth;
58
59 /* for ganged-mode support */
60 struct tegra_dsi *master;
61 struct tegra_dsi *slave;
62 };
63
64 static inline struct tegra_dsi *
65 host1x_client_to_dsi(struct host1x_client *client)
66 {
67 return container_of(client, struct tegra_dsi, client);
68 }
69
70 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
71 {
72 return container_of(host, struct tegra_dsi, host);
73 }
74
75 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
76 {
77 return container_of(output, struct tegra_dsi, output);
78 }
79
80 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
81 {
82 return readl(dsi->regs + (reg << 2));
83 }
84
85 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
86 unsigned long reg)
87 {
88 writel(value, dsi->regs + (reg << 2));
89 }
90
91 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
92 {
93 struct drm_info_node *node = s->private;
94 struct tegra_dsi *dsi = node->info_ent->data;
95
96 #define DUMP_REG(name) \
97 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
98 tegra_dsi_readl(dsi, name))
99
100 DUMP_REG(DSI_INCR_SYNCPT);
101 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
102 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
103 DUMP_REG(DSI_CTXSW);
104 DUMP_REG(DSI_RD_DATA);
105 DUMP_REG(DSI_WR_DATA);
106 DUMP_REG(DSI_POWER_CONTROL);
107 DUMP_REG(DSI_INT_ENABLE);
108 DUMP_REG(DSI_INT_STATUS);
109 DUMP_REG(DSI_INT_MASK);
110 DUMP_REG(DSI_HOST_CONTROL);
111 DUMP_REG(DSI_CONTROL);
112 DUMP_REG(DSI_SOL_DELAY);
113 DUMP_REG(DSI_MAX_THRESHOLD);
114 DUMP_REG(DSI_TRIGGER);
115 DUMP_REG(DSI_TX_CRC);
116 DUMP_REG(DSI_STATUS);
117
118 DUMP_REG(DSI_INIT_SEQ_CONTROL);
119 DUMP_REG(DSI_INIT_SEQ_DATA_0);
120 DUMP_REG(DSI_INIT_SEQ_DATA_1);
121 DUMP_REG(DSI_INIT_SEQ_DATA_2);
122 DUMP_REG(DSI_INIT_SEQ_DATA_3);
123 DUMP_REG(DSI_INIT_SEQ_DATA_4);
124 DUMP_REG(DSI_INIT_SEQ_DATA_5);
125 DUMP_REG(DSI_INIT_SEQ_DATA_6);
126 DUMP_REG(DSI_INIT_SEQ_DATA_7);
127
128 DUMP_REG(DSI_PKT_SEQ_0_LO);
129 DUMP_REG(DSI_PKT_SEQ_0_HI);
130 DUMP_REG(DSI_PKT_SEQ_1_LO);
131 DUMP_REG(DSI_PKT_SEQ_1_HI);
132 DUMP_REG(DSI_PKT_SEQ_2_LO);
133 DUMP_REG(DSI_PKT_SEQ_2_HI);
134 DUMP_REG(DSI_PKT_SEQ_3_LO);
135 DUMP_REG(DSI_PKT_SEQ_3_HI);
136 DUMP_REG(DSI_PKT_SEQ_4_LO);
137 DUMP_REG(DSI_PKT_SEQ_4_HI);
138 DUMP_REG(DSI_PKT_SEQ_5_LO);
139 DUMP_REG(DSI_PKT_SEQ_5_HI);
140
141 DUMP_REG(DSI_DCS_CMDS);
142
143 DUMP_REG(DSI_PKT_LEN_0_1);
144 DUMP_REG(DSI_PKT_LEN_2_3);
145 DUMP_REG(DSI_PKT_LEN_4_5);
146 DUMP_REG(DSI_PKT_LEN_6_7);
147
148 DUMP_REG(DSI_PHY_TIMING_0);
149 DUMP_REG(DSI_PHY_TIMING_1);
150 DUMP_REG(DSI_PHY_TIMING_2);
151 DUMP_REG(DSI_BTA_TIMING);
152
153 DUMP_REG(DSI_TIMEOUT_0);
154 DUMP_REG(DSI_TIMEOUT_1);
155 DUMP_REG(DSI_TO_TALLY);
156
157 DUMP_REG(DSI_PAD_CONTROL_0);
158 DUMP_REG(DSI_PAD_CONTROL_CD);
159 DUMP_REG(DSI_PAD_CD_STATUS);
160 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
161 DUMP_REG(DSI_PAD_CONTROL_1);
162 DUMP_REG(DSI_PAD_CONTROL_2);
163 DUMP_REG(DSI_PAD_CONTROL_3);
164 DUMP_REG(DSI_PAD_CONTROL_4);
165
166 DUMP_REG(DSI_GANGED_MODE_CONTROL);
167 DUMP_REG(DSI_GANGED_MODE_START);
168 DUMP_REG(DSI_GANGED_MODE_SIZE);
169
170 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
171 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
172
173 DUMP_REG(DSI_INIT_SEQ_DATA_8);
174 DUMP_REG(DSI_INIT_SEQ_DATA_9);
175 DUMP_REG(DSI_INIT_SEQ_DATA_10);
176 DUMP_REG(DSI_INIT_SEQ_DATA_11);
177 DUMP_REG(DSI_INIT_SEQ_DATA_12);
178 DUMP_REG(DSI_INIT_SEQ_DATA_13);
179 DUMP_REG(DSI_INIT_SEQ_DATA_14);
180 DUMP_REG(DSI_INIT_SEQ_DATA_15);
181
182 #undef DUMP_REG
183
184 return 0;
185 }
186
187 static struct drm_info_list debugfs_files[] = {
188 { "regs", tegra_dsi_show_regs, 0, NULL },
189 };
190
191 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
192 struct drm_minor *minor)
193 {
194 const char *name = dev_name(dsi->dev);
195 unsigned int i;
196 int err;
197
198 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
199 if (!dsi->debugfs)
200 return -ENOMEM;
201
202 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
203 GFP_KERNEL);
204 if (!dsi->debugfs_files) {
205 err = -ENOMEM;
206 goto remove;
207 }
208
209 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
210 dsi->debugfs_files[i].data = dsi;
211
212 err = drm_debugfs_create_files(dsi->debugfs_files,
213 ARRAY_SIZE(debugfs_files),
214 dsi->debugfs, minor);
215 if (err < 0)
216 goto free;
217
218 dsi->minor = minor;
219
220 return 0;
221
222 free:
223 kfree(dsi->debugfs_files);
224 dsi->debugfs_files = NULL;
225 remove:
226 debugfs_remove(dsi->debugfs);
227 dsi->debugfs = NULL;
228
229 return err;
230 }
231
232 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
233 {
234 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
235 dsi->minor);
236 dsi->minor = NULL;
237
238 kfree(dsi->debugfs_files);
239 dsi->debugfs_files = NULL;
240
241 debugfs_remove(dsi->debugfs);
242 dsi->debugfs = NULL;
243
244 return 0;
245 }
246
247 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
248 #define PKT_LEN0(len) (((len) & 0x07) << 0)
249 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
250 #define PKT_LEN1(len) (((len) & 0x07) << 10)
251 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
252 #define PKT_LEN2(len) (((len) & 0x07) << 20)
253
254 #define PKT_LP (1 << 30)
255 #define NUM_PKT_SEQ 12
256
257 /*
258 * non-burst mode with sync pulses
259 */
260 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
261 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
262 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
263 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
264 PKT_LP,
265 [ 1] = 0,
266 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
267 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
268 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
269 PKT_LP,
270 [ 3] = 0,
271 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
272 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
273 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
274 PKT_LP,
275 [ 5] = 0,
276 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
277 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
278 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
279 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
280 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
281 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
282 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
283 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
284 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
285 PKT_LP,
286 [ 9] = 0,
287 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
288 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
289 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
290 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
291 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
292 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
293 };
294
295 /*
296 * non-burst mode with sync events
297 */
298 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
299 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
300 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
301 PKT_LP,
302 [ 1] = 0,
303 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
304 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
305 PKT_LP,
306 [ 3] = 0,
307 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
309 PKT_LP,
310 [ 5] = 0,
311 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
312 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
313 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
314 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
315 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
316 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
317 PKT_LP,
318 [ 9] = 0,
319 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
320 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
321 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
322 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
323 };
324
325 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
326 [ 0] = 0,
327 [ 1] = 0,
328 [ 2] = 0,
329 [ 3] = 0,
330 [ 4] = 0,
331 [ 5] = 0,
332 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
333 [ 7] = 0,
334 [ 8] = 0,
335 [ 9] = 0,
336 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
337 [11] = 0,
338 };
339
340 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
341 {
342 struct mipi_dphy_timing timing;
343 unsigned long period;
344 u32 value;
345 long rate;
346 int err;
347
348 rate = clk_get_rate(dsi->clk);
349 if (rate < 0)
350 return rate;
351
352 period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate * 2);
353
354 err = mipi_dphy_timing_get_default(&timing, period);
355 if (err < 0)
356 return err;
357
358 err = mipi_dphy_timing_validate(&timing, period);
359 if (err < 0) {
360 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
361 return err;
362 }
363
364 /*
365 * The D-PHY timing fields below are expressed in byte-clock cycles,
366 * so multiply the period by 8.
367 */
368 period *= 8;
369
370 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
371 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
372 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
373 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
374 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
375
376 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
377 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
378 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
379 DSI_TIMING_FIELD(timing.lpx, period, 1);
380 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
381
382 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
383 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
384 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
385 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
386
387 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
388 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
389 DSI_TIMING_FIELD(timing.tago, period, 1);
390 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
391
392 if (dsi->slave)
393 return tegra_dsi_set_phy_timing(dsi->slave);
394
395 return 0;
396 }
397
398 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
399 unsigned int *mulp, unsigned int *divp)
400 {
401 switch (format) {
402 case MIPI_DSI_FMT_RGB666_PACKED:
403 case MIPI_DSI_FMT_RGB888:
404 *mulp = 3;
405 *divp = 1;
406 break;
407
408 case MIPI_DSI_FMT_RGB565:
409 *mulp = 2;
410 *divp = 1;
411 break;
412
413 case MIPI_DSI_FMT_RGB666:
414 *mulp = 9;
415 *divp = 4;
416 break;
417
418 default:
419 return -EINVAL;
420 }
421
422 return 0;
423 }
424
425 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
426 enum tegra_dsi_format *fmt)
427 {
428 switch (format) {
429 case MIPI_DSI_FMT_RGB888:
430 *fmt = TEGRA_DSI_FORMAT_24P;
431 break;
432
433 case MIPI_DSI_FMT_RGB666:
434 *fmt = TEGRA_DSI_FORMAT_18NP;
435 break;
436
437 case MIPI_DSI_FMT_RGB666_PACKED:
438 *fmt = TEGRA_DSI_FORMAT_18P;
439 break;
440
441 case MIPI_DSI_FMT_RGB565:
442 *fmt = TEGRA_DSI_FORMAT_16P;
443 break;
444
445 default:
446 return -EINVAL;
447 }
448
449 return 0;
450 }
451
452 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
453 unsigned int size)
454 {
455 u32 value;
456
457 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
458 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
459
460 value = DSI_GANGED_MODE_CONTROL_ENABLE;
461 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
462 }
463
464 static void tegra_dsi_enable(struct tegra_dsi *dsi)
465 {
466 u32 value;
467
468 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
469 value |= DSI_POWER_CONTROL_ENABLE;
470 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
471
472 if (dsi->slave)
473 tegra_dsi_enable(dsi->slave);
474 }
475
476 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
477 {
478 if (dsi->master)
479 return dsi->master->lanes + dsi->lanes;
480
481 if (dsi->slave)
482 return dsi->lanes + dsi->slave->lanes;
483
484 return dsi->lanes;
485 }
486
487 static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
488 const struct drm_display_mode *mode)
489 {
490 unsigned int hact, hsw, hbp, hfp, i, mul, div;
491 enum tegra_dsi_format format;
492 const u32 *pkt_seq;
493 u32 value;
494 int err;
495
496 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
497 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
498 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
499 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
500 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
501 pkt_seq = pkt_seq_video_non_burst_sync_events;
502 } else {
503 DRM_DEBUG_KMS("Command mode\n");
504 pkt_seq = pkt_seq_command_mode;
505 }
506
507 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
508 if (err < 0)
509 return err;
510
511 err = tegra_dsi_get_format(dsi->format, &format);
512 if (err < 0)
513 return err;
514
515 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
516 DSI_CONTROL_LANES(dsi->lanes - 1) |
517 DSI_CONTROL_SOURCE(pipe);
518 tegra_dsi_writel(dsi, value, DSI_CONTROL);
519
520 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
521
522 value = DSI_HOST_CONTROL_HS;
523 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
524
525 value = tegra_dsi_readl(dsi, DSI_CONTROL);
526
527 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
528 value |= DSI_CONTROL_HS_CLK_CTRL;
529
530 value &= ~DSI_CONTROL_TX_TRIG(3);
531
532 /* enable DCS commands for command mode */
533 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
534 value &= ~DSI_CONTROL_DCS_ENABLE;
535 else
536 value |= DSI_CONTROL_DCS_ENABLE;
537
538 value |= DSI_CONTROL_VIDEO_ENABLE;
539 value &= ~DSI_CONTROL_HOST_ENABLE;
540 tegra_dsi_writel(dsi, value, DSI_CONTROL);
541
542 for (i = 0; i < NUM_PKT_SEQ; i++)
543 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
544
545 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
546 /* horizontal active pixels */
547 hact = mode->hdisplay * mul / div;
548
549 /* horizontal sync width */
550 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
551 hsw -= 10;
552
553 /* horizontal back porch */
554 hbp = (mode->htotal - mode->hsync_end) * mul / div;
555 hbp -= 14;
556
557 /* horizontal front porch */
558 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
559 hfp -= 8;
560
561 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
562 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
563 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
564 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
565
566 /* set SOL delay (for non-burst mode only) */
567 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
568
569 /* TODO: implement ganged mode */
570 } else {
571 u16 bytes;
572
573 if (dsi->master || dsi->slave) {
574 /*
575 * For ganged mode, assume symmetric left-right mode.
576 */
577 bytes = 1 + (mode->hdisplay / 2) * mul / div;
578 } else {
579 /* 1 byte (DCS command) + pixel data */
580 bytes = 1 + mode->hdisplay * mul / div;
581 }
582
583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
584 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
585 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
586 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
587
588 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
589 MIPI_DCS_WRITE_MEMORY_CONTINUE;
590 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
591
592 /* set SOL delay */
593 if (dsi->master || dsi->slave) {
594 unsigned int lanes = tegra_dsi_get_lanes(dsi);
595 unsigned long delay, bclk, bclk_ganged;
596
597 /* SOL to valid, valid to FIFO and FIFO write delay */
598 delay = 4 + 4 + 2;
599 delay = DIV_ROUND_UP(delay * mul, div * lanes);
600 /* FIFO read delay */
601 delay = delay + 6;
602
603 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
604 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
605 value = bclk - bclk_ganged + delay + 20;
606 } else {
607 /* TODO: revisit for non-ganged mode */
608 value = 8 * mul / div;
609 }
610
611 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
612 }
613
614 if (dsi->slave) {
615 err = tegra_dsi_configure(dsi->slave, pipe, mode);
616 if (err < 0)
617 return err;
618
619 /*
620 * TODO: Support modes other than symmetrical left-right
621 * split.
622 */
623 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
624 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
625 mode->hdisplay / 2);
626 }
627
628 return 0;
629 }
630
631 static int tegra_output_dsi_enable(struct tegra_output *output)
632 {
633 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
634 const struct drm_display_mode *mode = &dc->base.mode;
635 struct tegra_dsi *dsi = to_dsi(output);
636 u32 value;
637 int err;
638
639 if (dsi->enabled)
640 return 0;
641
642 err = tegra_dsi_configure(dsi, dc->pipe, mode);
643 if (err < 0)
644 return err;
645
646 /* enable display controller */
647 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
648 value |= DSI_ENABLE;
649 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
650
651 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
652 value &= ~DISP_CTRL_MODE_MASK;
653 value |= DISP_CTRL_MODE_C_DISPLAY;
654 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
655
656 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
657 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
658 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
659 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
660
661 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
662 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
663
664 /* enable DSI controller */
665 tegra_dsi_enable(dsi);
666
667 dsi->enabled = true;
668
669 return 0;
670 }
671
672 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
673 {
674 u32 value;
675
676 timeout = jiffies + msecs_to_jiffies(timeout);
677
678 while (time_before(jiffies, timeout)) {
679 value = tegra_dsi_readl(dsi, DSI_STATUS);
680 if (value & DSI_STATUS_IDLE)
681 return 0;
682
683 usleep_range(1000, 2000);
684 }
685
686 return -ETIMEDOUT;
687 }
688
689 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
690 {
691 u32 value;
692
693 value = tegra_dsi_readl(dsi, DSI_CONTROL);
694 value &= ~DSI_CONTROL_VIDEO_ENABLE;
695 tegra_dsi_writel(dsi, value, DSI_CONTROL);
696
697 if (dsi->slave)
698 tegra_dsi_video_disable(dsi->slave);
699 }
700
701 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
702 {
703 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
704 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
705 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
706 }
707
708 static void tegra_dsi_disable(struct tegra_dsi *dsi)
709 {
710 u32 value;
711
712 if (dsi->slave) {
713 tegra_dsi_ganged_disable(dsi->slave);
714 tegra_dsi_ganged_disable(dsi);
715 }
716
717 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
718 value &= ~DSI_POWER_CONTROL_ENABLE;
719 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
720
721 if (dsi->slave)
722 tegra_dsi_disable(dsi->slave);
723
724 usleep_range(5000, 10000);
725 }
726
727 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
728 {
729 u32 value;
730
731 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
732 value &= ~DSI_POWER_CONTROL_ENABLE;
733 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
734
735 usleep_range(300, 1000);
736
737 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
738 value |= DSI_POWER_CONTROL_ENABLE;
739 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
740
741 usleep_range(300, 1000);
742
743 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
744 if (value)
745 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
746
747 if (dsi->slave)
748 tegra_dsi_soft_reset(dsi->slave);
749 }
750
751 static int tegra_output_dsi_disable(struct tegra_output *output)
752 {
753 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
754 struct tegra_dsi *dsi = to_dsi(output);
755 u32 value;
756 int err;
757
758 if (!dsi->enabled)
759 return 0;
760
761 tegra_dsi_video_disable(dsi);
762
763 /*
764 * The following accesses registers of the display controller, so make
765 * sure it's only executed when the output is attached to one.
766 */
767 if (dc) {
768 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
769 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
770 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
771 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
772
773 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
774 value &= ~DISP_CTRL_MODE_MASK;
775 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
776
777 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
778 value &= ~DSI_ENABLE;
779 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
780
781 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
782 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
783 }
784
785 err = tegra_dsi_wait_idle(dsi, 100);
786 if (err < 0)
787 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
788
789 tegra_dsi_soft_reset(dsi);
790 tegra_dsi_disable(dsi);
791
792 dsi->enabled = false;
793
794 return 0;
795 }
796
797 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
798 unsigned int vrefresh)
799 {
800 unsigned int timeout;
801 u32 value;
802
803 /* one frame high-speed transmission timeout */
804 timeout = (bclk / vrefresh) / 512;
805 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
806 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
807
808 /* 2 ms peripheral timeout for panel */
809 timeout = 2 * bclk / 512 * 1000;
810 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
811 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
812
813 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
814 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
815
816 if (dsi->slave)
817 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
818 }
819
820 static int tegra_output_dsi_setup_clock(struct tegra_output *output,
821 struct clk *clk, unsigned long pclk,
822 unsigned int *divp)
823 {
824 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
825 struct drm_display_mode *mode = &dc->base.mode;
826 struct tegra_dsi *dsi = to_dsi(output);
827 unsigned int mul, div, vrefresh, lanes;
828 unsigned long bclk, plld;
829 int err;
830
831 lanes = tegra_dsi_get_lanes(dsi);
832
833 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
834 if (err < 0)
835 return err;
836
837 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, lanes);
838 vrefresh = drm_mode_vrefresh(mode);
839 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
840
841 /* compute byte clock */
842 bclk = (pclk * mul) / (div * lanes);
843
844 /*
845 * Compute bit clock and round up to the next MHz.
846 */
847 plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
848
849 /*
850 * We divide the frequency by two here, but we make up for that by
851 * setting the shift clock divider (further below) to half of the
852 * correct value.
853 */
854 plld /= 2;
855
856 err = clk_set_parent(clk, dsi->clk_parent);
857 if (err < 0) {
858 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
859 return err;
860 }
861
862 err = clk_set_rate(dsi->clk_parent, plld);
863 if (err < 0) {
864 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
865 plld);
866 return err;
867 }
868
869 /*
870 * Derive pixel clock from bit clock using the shift clock divider.
871 * Note that this is only half of what we would expect, but we need
872 * that to make up for the fact that we divided the bit clock by a
873 * factor of two above.
874 *
875 * It's not clear exactly why this is necessary, but the display is
876 * not working properly otherwise. Perhaps the PLLs cannot generate
877 * frequencies sufficiently high.
878 */
879 *divp = ((8 * mul) / (div * lanes)) - 2;
880
881 /*
882 * XXX: Move the below somewhere else so that we don't need to have
883 * access to the vrefresh in this function?
884 */
885 tegra_dsi_set_timeout(dsi, bclk, vrefresh);
886
887 err = tegra_dsi_set_phy_timing(dsi);
888 if (err < 0)
889 return err;
890
891 return 0;
892 }
893
894 static int tegra_output_dsi_check_mode(struct tegra_output *output,
895 struct drm_display_mode *mode,
896 enum drm_mode_status *status)
897 {
898 /*
899 * FIXME: For now, always assume that the mode is okay.
900 */
901
902 *status = MODE_OK;
903
904 return 0;
905 }
906
907 static const struct tegra_output_ops dsi_ops = {
908 .enable = tegra_output_dsi_enable,
909 .disable = tegra_output_dsi_disable,
910 .setup_clock = tegra_output_dsi_setup_clock,
911 .check_mode = tegra_output_dsi_check_mode,
912 };
913
914 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
915 {
916 u32 value;
917
918 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
919 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
920
921 return 0;
922 }
923
924 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
925 {
926 u32 value;
927
928 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
929 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
930 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
931 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
932 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
933
934 /* start calibration */
935 tegra_dsi_pad_enable(dsi);
936
937 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
938 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
939 DSI_PAD_OUT_CLK(0x0);
940 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
941
942 return tegra_mipi_calibrate(dsi->mipi);
943 }
944
945 static int tegra_dsi_init(struct host1x_client *client)
946 {
947 struct drm_device *drm = dev_get_drvdata(client->parent);
948 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
949 int err;
950
951 /* Gangsters must not register their own outputs. */
952 if (!dsi->master) {
953 dsi->output.type = TEGRA_OUTPUT_DSI;
954 dsi->output.dev = client->dev;
955 dsi->output.ops = &dsi_ops;
956
957 err = tegra_output_init(drm, &dsi->output);
958 if (err < 0) {
959 dev_err(client->dev, "output setup failed: %d\n", err);
960 return err;
961 }
962 }
963
964 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
965 err = tegra_dsi_debugfs_init(dsi, drm->primary);
966 if (err < 0)
967 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
968 }
969
970 return 0;
971 }
972
973 static int tegra_dsi_exit(struct host1x_client *client)
974 {
975 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
976 int err;
977
978 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
979 err = tegra_dsi_debugfs_exit(dsi);
980 if (err < 0)
981 dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
982 }
983
984 if (!dsi->master) {
985 err = tegra_output_disable(&dsi->output);
986 if (err < 0) {
987 dev_err(client->dev, "output failed to disable: %d\n",
988 err);
989 return err;
990 }
991
992 err = tegra_output_exit(&dsi->output);
993 if (err < 0) {
994 dev_err(client->dev, "output cleanup failed: %d\n",
995 err);
996 return err;
997 }
998 }
999
1000 return 0;
1001 }
1002
1003 static const struct host1x_client_ops dsi_client_ops = {
1004 .init = tegra_dsi_init,
1005 .exit = tegra_dsi_exit,
1006 };
1007
1008 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1009 {
1010 struct clk *parent;
1011 int err;
1012
1013 parent = clk_get_parent(dsi->clk);
1014 if (!parent)
1015 return -EINVAL;
1016
1017 err = clk_set_parent(parent, dsi->clk_parent);
1018 if (err < 0)
1019 return err;
1020
1021 return 0;
1022 }
1023
1024 static const char * const error_report[16] = {
1025 "SoT Error",
1026 "SoT Sync Error",
1027 "EoT Sync Error",
1028 "Escape Mode Entry Command Error",
1029 "Low-Power Transmit Sync Error",
1030 "Peripheral Timeout Error",
1031 "False Control Error",
1032 "Contention Detected",
1033 "ECC Error, single-bit",
1034 "ECC Error, multi-bit",
1035 "Checksum Error",
1036 "DSI Data Type Not Recognized",
1037 "DSI VC ID Invalid",
1038 "Invalid Transmission Length",
1039 "Reserved",
1040 "DSI Protocol Violation",
1041 };
1042
1043 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1044 const struct mipi_dsi_msg *msg,
1045 size_t count)
1046 {
1047 u8 *rx = msg->rx_buf;
1048 unsigned int i, j, k;
1049 size_t size = 0;
1050 u16 errors;
1051 u32 value;
1052
1053 /* read and parse packet header */
1054 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1055
1056 switch (value & 0x3f) {
1057 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1058 errors = (value >> 8) & 0xffff;
1059 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1060 errors);
1061 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1062 if (errors & BIT(i))
1063 dev_dbg(dsi->dev, " %2u: %s\n", i,
1064 error_report[i]);
1065 break;
1066
1067 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1068 rx[0] = (value >> 8) & 0xff;
1069 size = 1;
1070 break;
1071
1072 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1073 rx[0] = (value >> 8) & 0xff;
1074 rx[1] = (value >> 16) & 0xff;
1075 size = 2;
1076 break;
1077
1078 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1079 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1080 break;
1081
1082 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1083 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1084 break;
1085
1086 default:
1087 dev_err(dsi->dev, "unhandled response type: %02x\n",
1088 value & 0x3f);
1089 return -EPROTO;
1090 }
1091
1092 size = min(size, msg->rx_len);
1093
1094 if (msg->rx_buf && size > 0) {
1095 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1096 u8 *rx = msg->rx_buf + j;
1097
1098 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1099
1100 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1101 rx[j + k] = (value >> (k << 3)) & 0xff;
1102 }
1103 }
1104
1105 return size;
1106 }
1107
1108 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1109 {
1110 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1111
1112 timeout = jiffies + msecs_to_jiffies(timeout);
1113
1114 while (time_before(jiffies, timeout)) {
1115 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1116 if ((value & DSI_TRIGGER_HOST) == 0)
1117 return 0;
1118
1119 usleep_range(1000, 2000);
1120 }
1121
1122 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1123 return -ETIMEDOUT;
1124 }
1125
1126 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1127 unsigned long timeout)
1128 {
1129 timeout = jiffies + msecs_to_jiffies(250);
1130
1131 while (time_before(jiffies, timeout)) {
1132 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1133 u8 count = value & 0x1f;
1134
1135 if (count > 0)
1136 return count;
1137
1138 usleep_range(1000, 2000);
1139 }
1140
1141 DRM_DEBUG_KMS("peripheral returned no data\n");
1142 return -ETIMEDOUT;
1143 }
1144
1145 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1146 const void *buffer, size_t size)
1147 {
1148 const u8 *buf = buffer;
1149 size_t i, j;
1150 u32 value;
1151
1152 for (j = 0; j < size; j += 4) {
1153 value = 0;
1154
1155 for (i = 0; i < 4 && j + i < size; i++)
1156 value |= buf[j + i] << (i << 3);
1157
1158 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1159 }
1160 }
1161
1162 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1163 const struct mipi_dsi_msg *msg)
1164 {
1165 struct tegra_dsi *dsi = host_to_tegra(host);
1166 struct mipi_dsi_packet packet;
1167 const u8 *header;
1168 size_t count;
1169 ssize_t err;
1170 u32 value;
1171
1172 err = mipi_dsi_create_packet(&packet, msg);
1173 if (err < 0)
1174 return err;
1175
1176 header = packet.header;
1177
1178 /* maximum FIFO depth is 1920 words */
1179 if (packet.size > dsi->video_fifo_depth * 4)
1180 return -ENOSPC;
1181
1182 /* reset underflow/overflow flags */
1183 value = tegra_dsi_readl(dsi, DSI_STATUS);
1184 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1185 value = DSI_HOST_CONTROL_FIFO_RESET;
1186 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1187 usleep_range(10, 20);
1188 }
1189
1190 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1191 value |= DSI_POWER_CONTROL_ENABLE;
1192 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1193
1194 usleep_range(5000, 10000);
1195
1196 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1197 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1198
1199 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1200 value |= DSI_HOST_CONTROL_HS;
1201
1202 /*
1203 * The host FIFO has a maximum of 64 words, so larger transmissions
1204 * need to use the video FIFO.
1205 */
1206 if (packet.size > dsi->host_fifo_depth * 4)
1207 value |= DSI_HOST_CONTROL_FIFO_SEL;
1208
1209 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1210
1211 /*
1212 * For reads and messages with explicitly requested ACK, generate a
1213 * BTA sequence after the transmission of the packet.
1214 */
1215 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1216 (msg->rx_buf && msg->rx_len > 0)) {
1217 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1218 value |= DSI_HOST_CONTROL_PKT_BTA;
1219 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1220 }
1221
1222 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1223 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1224
1225 /* write packet header, ECC is generated by hardware */
1226 value = header[2] << 16 | header[1] << 8 | header[0];
1227 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1228
1229 /* write payload (if any) */
1230 if (packet.payload_length > 0)
1231 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1232 packet.payload_length);
1233
1234 err = tegra_dsi_transmit(dsi, 250);
1235 if (err < 0)
1236 return err;
1237
1238 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1239 (msg->rx_buf && msg->rx_len > 0)) {
1240 err = tegra_dsi_wait_for_response(dsi, 250);
1241 if (err < 0)
1242 return err;
1243
1244 count = err;
1245
1246 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1247 switch (value) {
1248 case 0x84:
1249 /*
1250 dev_dbg(dsi->dev, "ACK\n");
1251 */
1252 break;
1253
1254 case 0x87:
1255 /*
1256 dev_dbg(dsi->dev, "ESCAPE\n");
1257 */
1258 break;
1259
1260 default:
1261 dev_err(dsi->dev, "unknown status: %08x\n", value);
1262 break;
1263 }
1264
1265 if (count > 1) {
1266 err = tegra_dsi_read_response(dsi, msg, count);
1267 if (err < 0)
1268 dev_err(dsi->dev,
1269 "failed to parse response: %zd\n",
1270 err);
1271 else {
1272 /*
1273 * For read commands, return the number of
1274 * bytes returned by the peripheral.
1275 */
1276 count = err;
1277 }
1278 }
1279 } else {
1280 /*
1281 * For write commands, we have transmitted the 4-byte header
1282 * plus the variable-length payload.
1283 */
1284 count = 4 + packet.payload_length;
1285 }
1286
1287 return count;
1288 }
1289
1290 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1291 {
1292 struct clk *parent;
1293 int err;
1294
1295 /* make sure both DSI controllers share the same PLL */
1296 parent = clk_get_parent(dsi->slave->clk);
1297 if (!parent)
1298 return -EINVAL;
1299
1300 err = clk_set_parent(parent, dsi->clk_parent);
1301 if (err < 0)
1302 return err;
1303
1304 return 0;
1305 }
1306
1307 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1308 struct mipi_dsi_device *device)
1309 {
1310 struct tegra_dsi *dsi = host_to_tegra(host);
1311
1312 dsi->flags = device->mode_flags;
1313 dsi->format = device->format;
1314 dsi->lanes = device->lanes;
1315
1316 if (dsi->slave) {
1317 int err;
1318
1319 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1320 dev_name(&device->dev));
1321
1322 err = tegra_dsi_ganged_setup(dsi);
1323 if (err < 0) {
1324 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1325 err);
1326 return err;
1327 }
1328 }
1329
1330 /*
1331 * Slaves don't have a panel associated with them, so they provide
1332 * merely the second channel.
1333 */
1334 if (!dsi->master) {
1335 struct tegra_output *output = &dsi->output;
1336
1337 output->panel = of_drm_find_panel(device->dev.of_node);
1338 if (output->panel && output->connector.dev) {
1339 drm_panel_attach(output->panel, &output->connector);
1340 drm_helper_hpd_irq_event(output->connector.dev);
1341 }
1342 }
1343
1344 return 0;
1345 }
1346
1347 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1348 struct mipi_dsi_device *device)
1349 {
1350 struct tegra_dsi *dsi = host_to_tegra(host);
1351 struct tegra_output *output = &dsi->output;
1352
1353 if (output->panel && &device->dev == output->panel->dev) {
1354 output->panel = NULL;
1355
1356 if (output->connector.dev)
1357 drm_helper_hpd_irq_event(output->connector.dev);
1358 }
1359
1360 return 0;
1361 }
1362
1363 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1364 .attach = tegra_dsi_host_attach,
1365 .detach = tegra_dsi_host_detach,
1366 .transfer = tegra_dsi_host_transfer,
1367 };
1368
1369 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1370 {
1371 struct device_node *np;
1372
1373 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1374 if (np) {
1375 struct platform_device *gangster = of_find_device_by_node(np);
1376
1377 dsi->slave = platform_get_drvdata(gangster);
1378 of_node_put(np);
1379
1380 if (!dsi->slave)
1381 return -EPROBE_DEFER;
1382
1383 dsi->slave->master = dsi;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static int tegra_dsi_probe(struct platform_device *pdev)
1390 {
1391 struct tegra_dsi *dsi;
1392 struct resource *regs;
1393 int err;
1394
1395 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1396 if (!dsi)
1397 return -ENOMEM;
1398
1399 dsi->output.dev = dsi->dev = &pdev->dev;
1400 dsi->video_fifo_depth = 1920;
1401 dsi->host_fifo_depth = 64;
1402
1403 err = tegra_dsi_ganged_probe(dsi);
1404 if (err < 0)
1405 return err;
1406
1407 err = tegra_output_probe(&dsi->output);
1408 if (err < 0)
1409 return err;
1410
1411 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1412
1413 /*
1414 * Assume these values by default. When a DSI peripheral driver
1415 * attaches to the DSI host, the parameters will be taken from
1416 * the attached device.
1417 */
1418 dsi->flags = MIPI_DSI_MODE_VIDEO;
1419 dsi->format = MIPI_DSI_FMT_RGB888;
1420 dsi->lanes = 4;
1421
1422 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1423 if (IS_ERR(dsi->rst))
1424 return PTR_ERR(dsi->rst);
1425
1426 err = reset_control_deassert(dsi->rst);
1427 if (err < 0) {
1428 dev_err(&pdev->dev, "failed to bring DSI out of reset: %d\n",
1429 err);
1430 return err;
1431 }
1432
1433 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1434 if (IS_ERR(dsi->clk)) {
1435 dev_err(&pdev->dev, "cannot get DSI clock\n");
1436 err = PTR_ERR(dsi->clk);
1437 goto reset;
1438 }
1439
1440 err = clk_prepare_enable(dsi->clk);
1441 if (err < 0) {
1442 dev_err(&pdev->dev, "cannot enable DSI clock\n");
1443 goto reset;
1444 }
1445
1446 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1447 if (IS_ERR(dsi->clk_lp)) {
1448 dev_err(&pdev->dev, "cannot get low-power clock\n");
1449 err = PTR_ERR(dsi->clk_lp);
1450 goto disable_clk;
1451 }
1452
1453 err = clk_prepare_enable(dsi->clk_lp);
1454 if (err < 0) {
1455 dev_err(&pdev->dev, "cannot enable low-power clock\n");
1456 goto disable_clk;
1457 }
1458
1459 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1460 if (IS_ERR(dsi->clk_parent)) {
1461 dev_err(&pdev->dev, "cannot get parent clock\n");
1462 err = PTR_ERR(dsi->clk_parent);
1463 goto disable_clk_lp;
1464 }
1465
1466 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1467 if (IS_ERR(dsi->vdd)) {
1468 dev_err(&pdev->dev, "cannot get VDD supply\n");
1469 err = PTR_ERR(dsi->vdd);
1470 goto disable_clk_lp;
1471 }
1472
1473 err = regulator_enable(dsi->vdd);
1474 if (err < 0) {
1475 dev_err(&pdev->dev, "cannot enable VDD supply\n");
1476 goto disable_clk_lp;
1477 }
1478
1479 err = tegra_dsi_setup_clocks(dsi);
1480 if (err < 0) {
1481 dev_err(&pdev->dev, "cannot setup clocks\n");
1482 goto disable_vdd;
1483 }
1484
1485 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1487 if (IS_ERR(dsi->regs)) {
1488 err = PTR_ERR(dsi->regs);
1489 goto disable_vdd;
1490 }
1491
1492 dsi->mipi = tegra_mipi_request(&pdev->dev);
1493 if (IS_ERR(dsi->mipi)) {
1494 err = PTR_ERR(dsi->mipi);
1495 goto disable_vdd;
1496 }
1497
1498 err = tegra_dsi_pad_calibrate(dsi);
1499 if (err < 0) {
1500 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
1501 goto mipi_free;
1502 }
1503
1504 dsi->host.ops = &tegra_dsi_host_ops;
1505 dsi->host.dev = &pdev->dev;
1506
1507 err = mipi_dsi_host_register(&dsi->host);
1508 if (err < 0) {
1509 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1510 goto mipi_free;
1511 }
1512
1513 INIT_LIST_HEAD(&dsi->client.list);
1514 dsi->client.ops = &dsi_client_ops;
1515 dsi->client.dev = &pdev->dev;
1516
1517 err = host1x_client_register(&dsi->client);
1518 if (err < 0) {
1519 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1520 err);
1521 goto unregister;
1522 }
1523
1524 platform_set_drvdata(pdev, dsi);
1525
1526 return 0;
1527
1528 unregister:
1529 mipi_dsi_host_unregister(&dsi->host);
1530 mipi_free:
1531 tegra_mipi_free(dsi->mipi);
1532 disable_vdd:
1533 regulator_disable(dsi->vdd);
1534 disable_clk_lp:
1535 clk_disable_unprepare(dsi->clk_lp);
1536 disable_clk:
1537 clk_disable_unprepare(dsi->clk);
1538 reset:
1539 reset_control_assert(dsi->rst);
1540 return err;
1541 }
1542
1543 static int tegra_dsi_remove(struct platform_device *pdev)
1544 {
1545 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1546 int err;
1547
1548 err = host1x_client_unregister(&dsi->client);
1549 if (err < 0) {
1550 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1551 err);
1552 return err;
1553 }
1554
1555 mipi_dsi_host_unregister(&dsi->host);
1556 tegra_mipi_free(dsi->mipi);
1557
1558 regulator_disable(dsi->vdd);
1559 clk_disable_unprepare(dsi->clk_lp);
1560 clk_disable_unprepare(dsi->clk);
1561 reset_control_assert(dsi->rst);
1562
1563 err = tegra_output_remove(&dsi->output);
1564 if (err < 0) {
1565 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
1566 return err;
1567 }
1568
1569 return 0;
1570 }
1571
1572 static const struct of_device_id tegra_dsi_of_match[] = {
1573 { .compatible = "nvidia,tegra114-dsi", },
1574 { },
1575 };
1576 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1577
1578 struct platform_driver tegra_dsi_driver = {
1579 .driver = {
1580 .name = "tegra-dsi",
1581 .of_match_table = tegra_dsi_of_match,
1582 },
1583 .probe = tegra_dsi_probe,
1584 .remove = tegra_dsi_remove,
1585 };
Linux kernel - Deliverables
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