2 * Copyright (C) 2015 Broadcom
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
21 * DOC: VC4 Falcon HDMI module
23 * The HDMI core has a state machine and a PHY. Most of the unit
24 * operates off of the HSM clock from CPRMAN. It also internally uses
25 * the PLLH_PIX clock for the PHY.
28 #include "drm_atomic_helper.h"
29 #include "drm_crtc_helper.h"
31 #include "linux/clk.h"
32 #include "linux/component.h"
33 #include "linux/i2c.h"
34 #include "linux/of_gpio.h"
35 #include "linux/of_platform.h"
39 /* General HDMI hardware state. */
41 struct platform_device
*pdev
;
43 struct drm_encoder
*encoder
;
44 struct drm_connector
*connector
;
46 struct i2c_adapter
*ddc
;
47 void __iomem
*hdmicore_regs
;
48 void __iomem
*hd_regs
;
52 struct clk
*pixel_clock
;
53 struct clk
*hsm_clock
;
56 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
57 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
58 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
59 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
61 /* VC4 HDMI encoder KMS struct */
62 struct vc4_hdmi_encoder
{
63 struct vc4_encoder base
;
67 static inline struct vc4_hdmi_encoder
*
68 to_vc4_hdmi_encoder(struct drm_encoder
*encoder
)
70 return container_of(encoder
, struct vc4_hdmi_encoder
, base
.base
);
73 /* VC4 HDMI connector KMS struct */
74 struct vc4_hdmi_connector
{
75 struct drm_connector base
;
77 /* Since the connector is attached to just the one encoder,
78 * this is the reference to it so we can do the best_encoder()
81 struct drm_encoder
*encoder
;
84 static inline struct vc4_hdmi_connector
*
85 to_vc4_hdmi_connector(struct drm_connector
*connector
)
87 return container_of(connector
, struct vc4_hdmi_connector
, base
);
90 #define HDMI_REG(reg) { reg, #reg }
95 HDMI_REG(VC4_HDMI_CORE_REV
),
96 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL
),
97 HDMI_REG(VC4_HDMI_HOTPLUG_INT
),
98 HDMI_REG(VC4_HDMI_HOTPLUG
),
99 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG
),
100 HDMI_REG(VC4_HDMI_HORZA
),
101 HDMI_REG(VC4_HDMI_HORZB
),
102 HDMI_REG(VC4_HDMI_FIFO_CTL
),
103 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL
),
104 HDMI_REG(VC4_HDMI_VERTA0
),
105 HDMI_REG(VC4_HDMI_VERTA1
),
106 HDMI_REG(VC4_HDMI_VERTB0
),
107 HDMI_REG(VC4_HDMI_VERTB1
),
108 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL
),
111 static const struct {
115 HDMI_REG(VC4_HD_M_CTL
),
116 HDMI_REG(VC4_HD_MAI_CTL
),
117 HDMI_REG(VC4_HD_VID_CTL
),
118 HDMI_REG(VC4_HD_CSC_CTL
),
119 HDMI_REG(VC4_HD_FRAME_COUNT
),
122 #ifdef CONFIG_DEBUG_FS
123 int vc4_hdmi_debugfs_regs(struct seq_file
*m
, void *unused
)
125 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
126 struct drm_device
*dev
= node
->minor
->dev
;
127 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
130 for (i
= 0; i
< ARRAY_SIZE(hdmi_regs
); i
++) {
131 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
132 hdmi_regs
[i
].name
, hdmi_regs
[i
].reg
,
133 HDMI_READ(hdmi_regs
[i
].reg
));
136 for (i
= 0; i
< ARRAY_SIZE(hd_regs
); i
++) {
137 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
138 hd_regs
[i
].name
, hd_regs
[i
].reg
,
139 HD_READ(hd_regs
[i
].reg
));
144 #endif /* CONFIG_DEBUG_FS */
146 static void vc4_hdmi_dump_regs(struct drm_device
*dev
)
148 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
151 for (i
= 0; i
< ARRAY_SIZE(hdmi_regs
); i
++) {
152 DRM_INFO("0x%04x (%s): 0x%08x\n",
153 hdmi_regs
[i
].reg
, hdmi_regs
[i
].name
,
154 HDMI_READ(hdmi_regs
[i
].reg
));
156 for (i
= 0; i
< ARRAY_SIZE(hd_regs
); i
++) {
157 DRM_INFO("0x%04x (%s): 0x%08x\n",
158 hd_regs
[i
].reg
, hd_regs
[i
].name
,
159 HD_READ(hd_regs
[i
].reg
));
163 static enum drm_connector_status
164 vc4_hdmi_connector_detect(struct drm_connector
*connector
, bool force
)
166 struct drm_device
*dev
= connector
->dev
;
167 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
169 if (vc4
->hdmi
->hpd_gpio
) {
170 if (gpio_get_value_cansleep(vc4
->hdmi
->hpd_gpio
) ^
171 vc4
->hdmi
->hpd_active_low
)
172 return connector_status_connected
;
174 return connector_status_disconnected
;
177 if (HDMI_READ(VC4_HDMI_HOTPLUG
) & VC4_HDMI_HOTPLUG_CONNECTED
)
178 return connector_status_connected
;
180 return connector_status_disconnected
;
183 static void vc4_hdmi_connector_destroy(struct drm_connector
*connector
)
185 drm_connector_unregister(connector
);
186 drm_connector_cleanup(connector
);
189 static int vc4_hdmi_connector_get_modes(struct drm_connector
*connector
)
191 struct vc4_hdmi_connector
*vc4_connector
=
192 to_vc4_hdmi_connector(connector
);
193 struct drm_encoder
*encoder
= vc4_connector
->encoder
;
194 struct vc4_hdmi_encoder
*vc4_encoder
= to_vc4_hdmi_encoder(encoder
);
195 struct drm_device
*dev
= connector
->dev
;
196 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
200 edid
= drm_get_edid(connector
, vc4
->hdmi
->ddc
);
204 vc4_encoder
->hdmi_monitor
= drm_detect_hdmi_monitor(edid
);
205 drm_mode_connector_update_edid_property(connector
, edid
);
206 ret
= drm_add_edid_modes(connector
, edid
);
212 * drm_helper_probe_single_connector_modes() applies drm_mode_set_crtcinfo to
213 * all modes with flag CRTC_INTERLACE_HALVE_V. We don't want this, as it
214 * screws up vblank timestamping for interlaced modes, so fix it up.
216 static int vc4_hdmi_connector_probe_modes(struct drm_connector
*connector
,
217 uint32_t maxX
, uint32_t maxY
)
219 struct drm_display_mode
*mode
;
222 count
= drm_helper_probe_single_connector_modes(connector
, maxX
, maxY
);
226 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed adapted modes :\n",
227 connector
->base
.id
, connector
->name
);
228 list_for_each_entry(mode
, &connector
->modes
, head
) {
229 drm_mode_set_crtcinfo(mode
, 0);
230 drm_mode_debug_printmodeline(mode
);
236 static const struct drm_connector_funcs vc4_hdmi_connector_funcs
= {
237 .dpms
= drm_atomic_helper_connector_dpms
,
238 .detect
= vc4_hdmi_connector_detect
,
239 .fill_modes
= vc4_hdmi_connector_probe_modes
,
240 .destroy
= vc4_hdmi_connector_destroy
,
241 .reset
= drm_atomic_helper_connector_reset
,
242 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
243 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
246 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs
= {
247 .get_modes
= vc4_hdmi_connector_get_modes
,
250 static struct drm_connector
*vc4_hdmi_connector_init(struct drm_device
*dev
,
251 struct drm_encoder
*encoder
)
253 struct drm_connector
*connector
= NULL
;
254 struct vc4_hdmi_connector
*hdmi_connector
;
257 hdmi_connector
= devm_kzalloc(dev
->dev
, sizeof(*hdmi_connector
),
259 if (!hdmi_connector
) {
263 connector
= &hdmi_connector
->base
;
265 hdmi_connector
->encoder
= encoder
;
267 drm_connector_init(dev
, connector
, &vc4_hdmi_connector_funcs
,
268 DRM_MODE_CONNECTOR_HDMIA
);
269 drm_connector_helper_add(connector
, &vc4_hdmi_connector_helper_funcs
);
271 connector
->polled
= (DRM_CONNECTOR_POLL_CONNECT
|
272 DRM_CONNECTOR_POLL_DISCONNECT
);
274 connector
->interlace_allowed
= 1;
275 connector
->doublescan_allowed
= 0;
277 drm_mode_connector_attach_encoder(connector
, encoder
);
283 vc4_hdmi_connector_destroy(connector
);
288 static void vc4_hdmi_encoder_destroy(struct drm_encoder
*encoder
)
290 drm_encoder_cleanup(encoder
);
293 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs
= {
294 .destroy
= vc4_hdmi_encoder_destroy
,
297 static void vc4_hdmi_encoder_mode_set(struct drm_encoder
*encoder
,
298 struct drm_display_mode
*unadjusted_mode
,
299 struct drm_display_mode
*mode
)
301 struct drm_device
*dev
= encoder
->dev
;
302 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
303 bool debug_dump_regs
= false;
304 bool hsync_pos
= mode
->flags
& DRM_MODE_FLAG_PHSYNC
;
305 bool vsync_pos
= mode
->flags
& DRM_MODE_FLAG_PVSYNC
;
306 u32 vactive
= (mode
->vdisplay
>>
307 ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ? 1 : 0));
308 u32 verta
= (VC4_SET_FIELD(mode
->vsync_end
- mode
->vsync_start
,
309 VC4_HDMI_VERTA_VSP
) |
310 VC4_SET_FIELD(mode
->vsync_start
- mode
->vdisplay
,
311 VC4_HDMI_VERTA_VFP
) |
312 VC4_SET_FIELD(vactive
, VC4_HDMI_VERTA_VAL
));
313 u32 vertb
= (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO
) |
314 VC4_SET_FIELD(mode
->vtotal
- mode
->vsync_end
,
315 VC4_HDMI_VERTB_VBP
));
317 if (debug_dump_regs
) {
318 DRM_INFO("HDMI regs before:\n");
319 vc4_hdmi_dump_regs(dev
);
322 HD_WRITE(VC4_HD_VID_CTL
, 0);
324 clk_set_rate(vc4
->hdmi
->pixel_clock
, mode
->clock
* 1000);
326 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
327 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) |
328 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT
|
329 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS
);
331 HDMI_WRITE(VC4_HDMI_HORZA
,
332 (vsync_pos
? VC4_HDMI_HORZA_VPOS
: 0) |
333 (hsync_pos
? VC4_HDMI_HORZA_HPOS
: 0) |
334 VC4_SET_FIELD(mode
->hdisplay
, VC4_HDMI_HORZA_HAP
));
336 HDMI_WRITE(VC4_HDMI_HORZB
,
337 VC4_SET_FIELD(mode
->htotal
- mode
->hsync_end
,
338 VC4_HDMI_HORZB_HBP
) |
339 VC4_SET_FIELD(mode
->hsync_end
- mode
->hsync_start
,
340 VC4_HDMI_HORZB_HSP
) |
341 VC4_SET_FIELD(mode
->hsync_start
- mode
->hdisplay
,
342 VC4_HDMI_HORZB_HFP
));
344 HDMI_WRITE(VC4_HDMI_VERTA0
, verta
);
345 HDMI_WRITE(VC4_HDMI_VERTA1
, verta
);
347 HDMI_WRITE(VC4_HDMI_VERTB0
, vertb
);
348 HDMI_WRITE(VC4_HDMI_VERTB1
, vertb
);
350 HD_WRITE(VC4_HD_VID_CTL
,
351 (vsync_pos
? 0 : VC4_HD_VID_CTL_VSYNC_LOW
) |
352 (hsync_pos
? 0 : VC4_HD_VID_CTL_HSYNC_LOW
));
354 /* The RGB order applies even when CSC is disabled. */
355 HD_WRITE(VC4_HD_CSC_CTL
, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR
,
356 VC4_HD_CSC_CTL_ORDER
));
358 HDMI_WRITE(VC4_HDMI_FIFO_CTL
, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N
);
360 if (debug_dump_regs
) {
361 DRM_INFO("HDMI regs after:\n");
362 vc4_hdmi_dump_regs(dev
);
366 static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder
)
368 struct drm_device
*dev
= encoder
->dev
;
369 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
371 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL
, 0xf << 16);
372 HD_WRITE(VC4_HD_VID_CTL
,
373 HD_READ(VC4_HD_VID_CTL
) & ~VC4_HD_VID_CTL_ENABLE
);
376 static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder
)
378 struct vc4_hdmi_encoder
*vc4_encoder
= to_vc4_hdmi_encoder(encoder
);
379 struct drm_device
*dev
= encoder
->dev
;
380 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
383 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL
, 0);
385 HD_WRITE(VC4_HD_VID_CTL
,
386 HD_READ(VC4_HD_VID_CTL
) |
387 VC4_HD_VID_CTL_ENABLE
|
388 VC4_HD_VID_CTL_UNDERFLOW_ENABLE
|
389 VC4_HD_VID_CTL_FRAME_COUNTER_RESET
);
391 if (vc4_encoder
->hdmi_monitor
) {
392 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
393 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) |
394 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI
);
396 ret
= wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
397 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE
, 1);
398 WARN_ONCE(ret
, "Timeout waiting for "
399 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
401 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG
,
402 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG
) &
403 ~(VC4_HDMI_RAM_PACKET_ENABLE
));
404 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
405 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
406 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI
);
408 ret
= wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
409 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE
), 1);
410 WARN_ONCE(ret
, "Timeout waiting for "
411 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
414 if (vc4_encoder
->hdmi_monitor
) {
417 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
418 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE
));
419 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
420 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) |
421 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT
);
423 /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
427 drift
= HDMI_READ(VC4_HDMI_FIFO_CTL
);
428 drift
&= VC4_HDMI_FIFO_VALID_WRITE_MASK
;
430 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
431 drift
& ~VC4_HDMI_FIFO_CTL_RECENTER
);
432 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
433 drift
| VC4_HDMI_FIFO_CTL_RECENTER
);
435 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
436 drift
& ~VC4_HDMI_FIFO_CTL_RECENTER
);
437 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
438 drift
| VC4_HDMI_FIFO_CTL_RECENTER
);
440 ret
= wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL
) &
441 VC4_HDMI_FIFO_CTL_RECENTER_DONE
, 1);
442 WARN_ONCE(ret
, "Timeout waiting for "
443 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
447 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs
= {
448 .mode_set
= vc4_hdmi_encoder_mode_set
,
449 .disable
= vc4_hdmi_encoder_disable
,
450 .enable
= vc4_hdmi_encoder_enable
,
453 static int vc4_hdmi_bind(struct device
*dev
, struct device
*master
, void *data
)
455 struct platform_device
*pdev
= to_platform_device(dev
);
456 struct drm_device
*drm
= dev_get_drvdata(master
);
457 struct vc4_dev
*vc4
= drm
->dev_private
;
458 struct vc4_hdmi
*hdmi
;
459 struct vc4_hdmi_encoder
*vc4_hdmi_encoder
;
460 struct device_node
*ddc_node
;
464 hdmi
= devm_kzalloc(dev
, sizeof(*hdmi
), GFP_KERNEL
);
468 vc4_hdmi_encoder
= devm_kzalloc(dev
, sizeof(*vc4_hdmi_encoder
),
470 if (!vc4_hdmi_encoder
)
472 vc4_hdmi_encoder
->base
.type
= VC4_ENCODER_TYPE_HDMI
;
473 hdmi
->encoder
= &vc4_hdmi_encoder
->base
.base
;
476 hdmi
->hdmicore_regs
= vc4_ioremap_regs(pdev
, 0);
477 if (IS_ERR(hdmi
->hdmicore_regs
))
478 return PTR_ERR(hdmi
->hdmicore_regs
);
480 hdmi
->hd_regs
= vc4_ioremap_regs(pdev
, 1);
481 if (IS_ERR(hdmi
->hd_regs
))
482 return PTR_ERR(hdmi
->hd_regs
);
484 hdmi
->pixel_clock
= devm_clk_get(dev
, "pixel");
485 if (IS_ERR(hdmi
->pixel_clock
)) {
486 DRM_ERROR("Failed to get pixel clock\n");
487 return PTR_ERR(hdmi
->pixel_clock
);
489 hdmi
->hsm_clock
= devm_clk_get(dev
, "hdmi");
490 if (IS_ERR(hdmi
->hsm_clock
)) {
491 DRM_ERROR("Failed to get HDMI state machine clock\n");
492 return PTR_ERR(hdmi
->hsm_clock
);
495 ddc_node
= of_parse_phandle(dev
->of_node
, "ddc", 0);
497 DRM_ERROR("Failed to find ddc node in device tree\n");
501 hdmi
->ddc
= of_find_i2c_adapter_by_node(ddc_node
);
502 of_node_put(ddc_node
);
504 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
505 return -EPROBE_DEFER
;
508 /* Enable the clocks at startup. We can't quite recover from
509 * turning off the pixel clock during disable/enables yet, so
510 * it's always running.
512 ret
= clk_prepare_enable(hdmi
->pixel_clock
);
514 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret
);
518 /* This is the rate that is set by the firmware. The number
519 * needs to be a bit higher than the pixel clock rate
520 * (generally 148.5Mhz).
522 ret
= clk_set_rate(hdmi
->hsm_clock
, 163682864);
524 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret
);
525 goto err_unprepare_pix
;
528 ret
= clk_prepare_enable(hdmi
->hsm_clock
);
530 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
532 goto err_unprepare_pix
;
535 /* Only use the GPIO HPD pin if present in the DT, otherwise
536 * we'll use the HDMI core's register.
538 if (of_find_property(dev
->of_node
, "hpd-gpios", &value
)) {
539 enum of_gpio_flags hpd_gpio_flags
;
541 hdmi
->hpd_gpio
= of_get_named_gpio_flags(dev
->of_node
,
544 if (hdmi
->hpd_gpio
< 0) {
545 ret
= hdmi
->hpd_gpio
;
546 goto err_unprepare_hsm
;
549 hdmi
->hpd_active_low
= hpd_gpio_flags
& OF_GPIO_ACTIVE_LOW
;
554 /* HDMI core must be enabled. */
555 if (!(HD_READ(VC4_HD_M_CTL
) & VC4_HD_M_ENABLE
)) {
556 HD_WRITE(VC4_HD_M_CTL
, VC4_HD_M_SW_RST
);
558 HD_WRITE(VC4_HD_M_CTL
, 0);
560 HD_WRITE(VC4_HD_M_CTL
, VC4_HD_M_ENABLE
);
562 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL
,
563 VC4_HDMI_SW_RESET_HDMI
|
564 VC4_HDMI_SW_RESET_FORMAT_DETECT
);
566 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL
, 0);
568 /* PHY should be in reset, like
569 * vc4_hdmi_encoder_disable() does.
571 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL
, 0xf << 16);
574 drm_encoder_init(drm
, hdmi
->encoder
, &vc4_hdmi_encoder_funcs
,
575 DRM_MODE_ENCODER_TMDS
, NULL
);
576 drm_encoder_helper_add(hdmi
->encoder
, &vc4_hdmi_encoder_helper_funcs
);
578 hdmi
->connector
= vc4_hdmi_connector_init(drm
, hdmi
->encoder
);
579 if (IS_ERR(hdmi
->connector
)) {
580 ret
= PTR_ERR(hdmi
->connector
);
581 goto err_destroy_encoder
;
587 vc4_hdmi_encoder_destroy(hdmi
->encoder
);
589 clk_disable_unprepare(hdmi
->hsm_clock
);
591 clk_disable_unprepare(hdmi
->pixel_clock
);
593 put_device(&hdmi
->ddc
->dev
);
598 static void vc4_hdmi_unbind(struct device
*dev
, struct device
*master
,
601 struct drm_device
*drm
= dev_get_drvdata(master
);
602 struct vc4_dev
*vc4
= drm
->dev_private
;
603 struct vc4_hdmi
*hdmi
= vc4
->hdmi
;
605 vc4_hdmi_connector_destroy(hdmi
->connector
);
606 vc4_hdmi_encoder_destroy(hdmi
->encoder
);
608 clk_disable_unprepare(hdmi
->pixel_clock
);
609 clk_disable_unprepare(hdmi
->hsm_clock
);
610 put_device(&hdmi
->ddc
->dev
);
615 static const struct component_ops vc4_hdmi_ops
= {
616 .bind
= vc4_hdmi_bind
,
617 .unbind
= vc4_hdmi_unbind
,
620 static int vc4_hdmi_dev_probe(struct platform_device
*pdev
)
622 return component_add(&pdev
->dev
, &vc4_hdmi_ops
);
625 static int vc4_hdmi_dev_remove(struct platform_device
*pdev
)
627 component_del(&pdev
->dev
, &vc4_hdmi_ops
);
631 static const struct of_device_id vc4_hdmi_dt_match
[] = {
632 { .compatible
= "brcm,bcm2835-hdmi" },
636 struct platform_driver vc4_hdmi_driver
= {
637 .probe
= vc4_hdmi_dev_probe
,
638 .remove
= vc4_hdmi_dev_remove
,
641 .of_match_table
= vc4_hdmi_dt_match
,