drivers/gpu/drm/vc4/vc4_plane.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 plane module
  11  *
  12  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  13  *
  14  * At atomic modeset check time, we compute the HVS display element
  15  * state that would be necessary for displaying the plane (giving us a
  16  * chance to figure out if a plane configuration is invalid), then at
  17  * atomic flush time the CRTC will ask us to write our element state
  18  * into the region of the HVS that it has allocated for us.
  19  */
  20
  21 #include "vc4_drv.h"
  22 #include "vc4_regs.h"
  23 #include "drm_atomic_helper.h"
  24 #include "drm_fb_cma_helper.h"
  25 #include "drm_plane_helper.h"
  26
  27 enum vc4_scaling_mode {
  28         VC4_SCALING_NONE,
  29         VC4_SCALING_TPZ,
  30         VC4_SCALING_PPF,
  31 };
  32
  33 struct vc4_plane_state {
  34         struct drm_plane_state base;
  35         /* System memory copy of the display list for this element, computed
  36          * at atomic_check time.
  37          */
  38         u32 *dlist;
  39         u32 dlist_size; /* Number of dwords allocated for the display list */
  40         u32 dlist_count; /* Number of used dwords in the display list. */
  41
  42         /* Offset in the dlist to various words, for pageflip or
  43          * cursor updates.
  44          */
  45         u32 pos0_offset;
  46         u32 pos2_offset;
  47         u32 ptr0_offset;
  48
  49         /* Offset where the plane's dlist was last stored in the
  50          * hardware at vc4_crtc_atomic_flush() time.
  51          */
  52         u32 __iomem *hw_dlist;
  53
  54         /* Clipped coordinates of the plane on the display. */
  55         int crtc_x, crtc_y, crtc_w, crtc_h;
  56         /* Clipped area being scanned from in the FB. */
  57         u32 src_x, src_y;
  58
  59         u32 src_w[2], src_h[2];
  60
  61         /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
  62         enum vc4_scaling_mode x_scaling[2], y_scaling[2];
  63         bool is_unity;
  64         bool is_yuv;
  65
  66         /* Offset to start scanning out from the start of the plane's
  67          * BO.
  68          */
  69         u32 offsets[3];
  70
  71         /* Our allocation in LBM for temporary storage during scaling. */
  72         struct drm_mm_node lbm;
  73 };
  74
  75 static inline struct vc4_plane_state *
  76 to_vc4_plane_state(struct drm_plane_state *state)
  77 {
  78         return (struct vc4_plane_state *)state;
  79 }
  80
  81 static const struct hvs_format {
  82         u32 drm; /* DRM_FORMAT_* */
  83         u32 hvs; /* HVS_FORMAT_* */
  84         u32 pixel_order;
  85         bool has_alpha;
  86         bool flip_cbcr;
  87 } hvs_formats[] = {
  88         {
  89                 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  90                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
  91         },
  92         {
  93                 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  94                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
  95         },
  96         {
  97                 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  98                 .pixel_order = HVS_PIXEL_ORDER_XRGB, .has_alpha = false,
  99         },
 100         {
 101                 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
 102                 .pixel_order = HVS_PIXEL_ORDER_XBGR, .has_alpha = false,
 103         },
 104         {
 105                 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
 106                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
 107         },
 108         {
 109                 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
 110                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
 111         },
 112         {
 113                 .drm = DRM_FORMAT_YUV422,
 114                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 115         },
 116         {
 117                 .drm = DRM_FORMAT_YVU422,
 118                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 119                 .flip_cbcr = true,
 120         },
 121         {
 122                 .drm = DRM_FORMAT_YUV420,
 123                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 124         },
 125         {
 126                 .drm = DRM_FORMAT_YVU420,
 127                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 128                 .flip_cbcr = true,
 129         },
 130         {
 131                 .drm = DRM_FORMAT_NV12,
 132                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 133         },
 134         {
 135                 .drm = DRM_FORMAT_NV16,
 136                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 137         },
 138 };
 139
 140 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 141 {
 142         unsigned i;
 143
 144         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 145                 if (hvs_formats[i].drm == drm_format)
 146                         return &hvs_formats[i];
 147         }
 148
 149         return NULL;
 150 }
 151
 152 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 153 {
 154         if (dst > src)
 155                 return VC4_SCALING_PPF;
 156         else if (dst < src)
 157                 return VC4_SCALING_TPZ;
 158         else
 159                 return VC4_SCALING_NONE;
 160 }
 161
 162 static bool plane_enabled(struct drm_plane_state *state)
 163 {
 164         return state->fb && state->crtc;
 165 }
 166
 167 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 168 {
 169         struct vc4_plane_state *vc4_state;
 170
 171         if (WARN_ON(!plane->state))
 172                 return NULL;
 173
 174         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 175         if (!vc4_state)
 176                 return NULL;
 177
 178         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 179
 180         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 181
 182         if (vc4_state->dlist) {
 183                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 184                                            vc4_state->dlist_count * 4,
 185                                            GFP_KERNEL);
 186                 if (!vc4_state->dlist) {
 187                         kfree(vc4_state);
 188                         return NULL;
 189                 }
 190                 vc4_state->dlist_size = vc4_state->dlist_count;
 191         }
 192
 193         return &vc4_state->base;
 194 }
 195
 196 static void vc4_plane_destroy_state(struct drm_plane *plane,
 197                                     struct drm_plane_state *state)
 198 {
 199         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 200         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 201
 202         if (vc4_state->lbm.allocated) {
 203                 unsigned long irqflags;
 204
 205                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 206                 drm_mm_remove_node(&vc4_state->lbm);
 207                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 208         }
 209
 210         kfree(vc4_state->dlist);
 211         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 212         kfree(state);
 213 }
 214
 215 /* Called during init to allocate the plane's atomic state. */
 216 static void vc4_plane_reset(struct drm_plane *plane)
 217 {
 218         struct vc4_plane_state *vc4_state;
 219
 220         WARN_ON(plane->state);
 221
 222         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 223         if (!vc4_state)
 224                 return;
 225
 226         plane->state = &vc4_state->base;
 227         vc4_state->base.plane = plane;
 228 }
 229
 230 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 231 {
 232         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 233                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 234                 u32 *new_dlist = kmalloc(new_size * 4, GFP_KERNEL);
 235
 236                 if (!new_dlist)
 237                         return;
 238                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 239
 240                 kfree(vc4_state->dlist);
 241                 vc4_state->dlist = new_dlist;
 242                 vc4_state->dlist_size = new_size;
 243         }
 244
 245         vc4_state->dlist[vc4_state->dlist_count++] = val;
 246 }
 247
 248 /* Returns the scl0/scl1 field based on whether the dimensions need to
 249  * be up/down/non-scaled.
 250  *
 251  * This is a replication of a table from the spec.
 252  */
 253 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 254 {
 255         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 256
 257         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 258         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 259                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 260         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 261                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 262         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 263                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 264         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 265                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 266         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 267                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 268         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 269                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 270         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 271                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 272         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 273                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 274         default:
 275         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 276                 /* The unity case is independently handled by
 277                  * SCALER_CTL0_UNITY.
 278                  */
 279                 return 0;
 280         }
 281 }
 282
 283 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 284 {
 285         struct drm_plane *plane = state->plane;
 286         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 287         struct drm_framebuffer *fb = state->fb;
 288         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 289         u32 subpixel_src_mask = (1 << 16) - 1;
 290         u32 format = fb->pixel_format;
 291         int num_planes = drm_format_num_planes(format);
 292         u32 h_subsample = 1;
 293         u32 v_subsample = 1;
 294         int i;
 295
 296         for (i = 0; i < num_planes; i++)
 297                 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
 298
 299         /* We don't support subpixel source positioning for scaling. */
 300         if ((state->src_x & subpixel_src_mask) ||
 301             (state->src_y & subpixel_src_mask) ||
 302             (state->src_w & subpixel_src_mask) ||
 303             (state->src_h & subpixel_src_mask)) {
 304                 return -EINVAL;
 305         }
 306
 307         vc4_state->src_x = state->src_x >> 16;
 308         vc4_state->src_y = state->src_y >> 16;
 309         vc4_state->src_w[0] = state->src_w >> 16;
 310         vc4_state->src_h[0] = state->src_h >> 16;
 311
 312         vc4_state->crtc_x = state->crtc_x;
 313         vc4_state->crtc_y = state->crtc_y;
 314         vc4_state->crtc_w = state->crtc_w;
 315         vc4_state->crtc_h = state->crtc_h;
 316
 317         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 318                                                        vc4_state->crtc_w);
 319         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 320                                                        vc4_state->crtc_h);
 321
 322         if (num_planes > 1) {
 323                 vc4_state->is_yuv = true;
 324
 325                 h_subsample = drm_format_horz_chroma_subsampling(format);
 326                 v_subsample = drm_format_vert_chroma_subsampling(format);
 327                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 328                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 329
 330                 vc4_state->x_scaling[1] =
 331                         vc4_get_scaling_mode(vc4_state->src_w[1],
 332                                              vc4_state->crtc_w);
 333                 vc4_state->y_scaling[1] =
 334                         vc4_get_scaling_mode(vc4_state->src_h[1],
 335                                              vc4_state->crtc_h);
 336
 337                 /* YUV conversion requires that scaling be enabled,
 338                  * even on a plane that's otherwise 1:1.  Choose TPZ
 339                  * for simplicity.
 340                  */
 341                 if (vc4_state->x_scaling[0] == VC4_SCALING_NONE)
 342                         vc4_state->x_scaling[0] = VC4_SCALING_TPZ;
 343                 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE)
 344                         vc4_state->y_scaling[0] = VC4_SCALING_TPZ;
 345         }
 346
 347         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 348                                vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
 349                                vc4_state->x_scaling[1] == VC4_SCALING_NONE &&
 350                                vc4_state->y_scaling[1] == VC4_SCALING_NONE);
 351
 352         /* No configuring scaling on the cursor plane, since it gets
 353            non-vblank-synced updates, and scaling requires requires
 354            LBM changes which have to be vblank-synced.
 355          */
 356         if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
 357                 return -EINVAL;
 358
 359         /* Clamp the on-screen start x/y to 0.  The hardware doesn't
 360          * support negative y, and negative x wastes bandwidth.
 361          */
 362         if (vc4_state->crtc_x < 0) {
 363                 for (i = 0; i < num_planes; i++) {
 364                         u32 cpp = drm_format_plane_cpp(fb->pixel_format, i);
 365                         u32 subs = ((i == 0) ? 1 : h_subsample);
 366
 367                         vc4_state->offsets[i] += (cpp *
 368                                                   (-vc4_state->crtc_x) / subs);
 369                 }
 370                 vc4_state->src_w[0] += vc4_state->crtc_x;
 371                 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
 372                 vc4_state->crtc_x = 0;
 373         }
 374
 375         if (vc4_state->crtc_y < 0) {
 376                 for (i = 0; i < num_planes; i++) {
 377                         u32 subs = ((i == 0) ? 1 : v_subsample);
 378
 379                         vc4_state->offsets[i] += (fb->pitches[i] *
 380                                                   (-vc4_state->crtc_y) / subs);
 381                 }
 382                 vc4_state->src_h[0] += vc4_state->crtc_y;
 383                 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
 384                 vc4_state->crtc_y = 0;
 385         }
 386
 387         return 0;
 388 }
 389
 390 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 391 {
 392         u32 scale, recip;
 393
 394         scale = (1 << 16) * src / dst;
 395
 396         /* The specs note that while the reciprocal would be defined
 397          * as (1<<32)/scale, ~0 is close enough.
 398          */
 399         recip = ~0 / scale;
 400
 401         vc4_dlist_write(vc4_state,
 402                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 403                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 404         vc4_dlist_write(vc4_state,
 405                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 406 }
 407
 408 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 409 {
 410         u32 scale = (1 << 16) * src / dst;
 411
 412         vc4_dlist_write(vc4_state,
 413                         SCALER_PPF_AGC |
 414                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 415                         VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
 416 }
 417
 418 static u32 vc4_lbm_size(struct drm_plane_state *state)
 419 {
 420         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 421         /* This is the worst case number.  One of the two sizes will
 422          * be used depending on the scaling configuration.
 423          */
 424         u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
 425         u32 lbm;
 426
 427         if (!vc4_state->is_yuv) {
 428                 if (vc4_state->is_unity)
 429                         return 0;
 430                 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 431                         lbm = pix_per_line * 8;
 432                 else {
 433                         /* In special cases, this multiplier might be 12. */
 434                         lbm = pix_per_line * 16;
 435                 }
 436         } else {
 437                 /* There are cases for this going down to a multiplier
 438                  * of 2, but according to the firmware source, the
 439                  * table in the docs is somewhat wrong.
 440                  */
 441                 lbm = pix_per_line * 16;
 442         }
 443
 444         lbm = roundup(lbm, 32);
 445
 446         return lbm;
 447 }
 448
 449 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 450                                          int channel)
 451 {
 452         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 453
 454         /* Ch0 H-PPF Word 0: Scaling Parameters */
 455         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 456                 vc4_write_ppf(vc4_state,
 457                               vc4_state->src_w[channel], vc4_state->crtc_w);
 458         }
 459
 460         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 461         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 462                 vc4_write_ppf(vc4_state,
 463                               vc4_state->src_h[channel], vc4_state->crtc_h);
 464                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 465         }
 466
 467         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 468         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 469                 vc4_write_tpz(vc4_state,
 470                               vc4_state->src_w[channel], vc4_state->crtc_w);
 471         }
 472
 473         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 474         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 475                 vc4_write_tpz(vc4_state,
 476                               vc4_state->src_h[channel], vc4_state->crtc_h);
 477                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 478         }
 479 }
 480
 481 /* Writes out a full display list for an active plane to the plane's
 482  * private dlist state.
 483  */
 484 static int vc4_plane_mode_set(struct drm_plane *plane,
 485                               struct drm_plane_state *state)
 486 {
 487         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 488         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 489         struct drm_framebuffer *fb = state->fb;
 490         u32 ctl0_offset = vc4_state->dlist_count;
 491         const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
 492         int num_planes = drm_format_num_planes(format->drm);
 493         u32 scl0, scl1;
 494         u32 lbm_size;
 495         unsigned long irqflags;
 496         int ret, i;
 497
 498         ret = vc4_plane_setup_clipping_and_scaling(state);
 499         if (ret)
 500                 return ret;
 501
 502         /* Allocate the LBM memory that the HVS will use for temporary
 503          * storage due to our scaling/format conversion.
 504          */
 505         lbm_size = vc4_lbm_size(state);
 506         if (lbm_size) {
 507                 if (!vc4_state->lbm.allocated) {
 508                         spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 509                         ret = drm_mm_insert_node(&vc4->hvs->lbm_mm,
 510                                                  &vc4_state->lbm,
 511                                                  lbm_size, 32, 0);
 512                         spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 513                 } else {
 514                         WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 515                 }
 516         }
 517
 518         if (ret)
 519                 return ret;
 520
 521         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 522          * and 4:4:4, scl1 should be set to scl0 so both channels of
 523          * the scaler do the same thing.  For YUV, the Y plane needs
 524          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 525          * the scl fields here.
 526          */
 527         if (num_planes == 1) {
 528                 scl0 = vc4_get_scl_field(state, 1);
 529                 scl1 = scl0;
 530         } else {
 531                 scl0 = vc4_get_scl_field(state, 1);
 532                 scl1 = vc4_get_scl_field(state, 0);
 533         }
 534
 535         /* Control word */
 536         vc4_dlist_write(vc4_state,
 537                         SCALER_CTL0_VALID |
 538                         (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 539                         (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 540                         (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
 541                         VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 542                         VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
 543
 544         /* Position Word 0: Image Positions and Alpha Value */
 545         vc4_state->pos0_offset = vc4_state->dlist_count;
 546         vc4_dlist_write(vc4_state,
 547                         VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) |
 548                         VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
 549                         VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
 550
 551         /* Position Word 1: Scaled Image Dimensions. */
 552         if (!vc4_state->is_unity) {
 553                 vc4_dlist_write(vc4_state,
 554                                 VC4_SET_FIELD(vc4_state->crtc_w,
 555                                               SCALER_POS1_SCL_WIDTH) |
 556                                 VC4_SET_FIELD(vc4_state->crtc_h,
 557                                               SCALER_POS1_SCL_HEIGHT));
 558         }
 559
 560         /* Position Word 2: Source Image Size, Alpha Mode */
 561         vc4_state->pos2_offset = vc4_state->dlist_count;
 562         vc4_dlist_write(vc4_state,
 563                         VC4_SET_FIELD(format->has_alpha ?
 564                                       SCALER_POS2_ALPHA_MODE_PIPELINE :
 565                                       SCALER_POS2_ALPHA_MODE_FIXED,
 566                                       SCALER_POS2_ALPHA_MODE) |
 567                         VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
 568                         VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
 569
 570         /* Position Word 3: Context.  Written by the HVS. */
 571         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 572
 573
 574         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
 575          *
 576          * The pointers may be any byte address.
 577          */
 578         vc4_state->ptr0_offset = vc4_state->dlist_count;
 579         if (!format->flip_cbcr) {
 580                 for (i = 0; i < num_planes; i++)
 581                         vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 582         } else {
 583                 WARN_ON_ONCE(num_planes != 3);
 584                 vc4_dlist_write(vc4_state, vc4_state->offsets[0]);
 585                 vc4_dlist_write(vc4_state, vc4_state->offsets[2]);
 586                 vc4_dlist_write(vc4_state, vc4_state->offsets[1]);
 587         }
 588
 589         /* Pointer Context Word 0/1/2: Written by the HVS */
 590         for (i = 0; i < num_planes; i++)
 591                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 592
 593         /* Pitch word 0/1/2 */
 594         for (i = 0; i < num_planes; i++) {
 595                 vc4_dlist_write(vc4_state,
 596                                 VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
 597         }
 598
 599         /* Colorspace conversion words */
 600         if (vc4_state->is_yuv) {
 601                 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
 602                 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
 603                 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
 604         }
 605
 606         if (!vc4_state->is_unity) {
 607                 /* LBM Base Address. */
 608                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 609                     vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 610                         vc4_dlist_write(vc4_state, vc4_state->lbm.start);
 611                 }
 612
 613                 if (num_planes > 1) {
 614                         /* Emit Cb/Cr as channel 0 and Y as channel
 615                          * 1. This matches how we set up scl0/scl1
 616                          * above.
 617                          */
 618                         vc4_write_scaling_parameters(state, 1);
 619                 }
 620                 vc4_write_scaling_parameters(state, 0);
 621
 622                 /* If any PPF setup was done, then all the kernel
 623                  * pointers get uploaded.
 624                  */
 625                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
 626                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
 627                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
 628                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
 629                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
 630                                                    SCALER_PPF_KERNEL_OFFSET);
 631
 632                         /* HPPF plane 0 */
 633                         vc4_dlist_write(vc4_state, kernel);
 634                         /* VPPF plane 0 */
 635                         vc4_dlist_write(vc4_state, kernel);
 636                         /* HPPF plane 1 */
 637                         vc4_dlist_write(vc4_state, kernel);
 638                         /* VPPF plane 1 */
 639                         vc4_dlist_write(vc4_state, kernel);
 640                 }
 641         }
 642
 643         vc4_state->dlist[ctl0_offset] |=
 644                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
 645
 646         return 0;
 647 }
 648
 649 /* If a modeset involves changing the setup of a plane, the atomic
 650  * infrastructure will call this to validate a proposed plane setup.
 651  * However, if a plane isn't getting updated, this (and the
 652  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
 653  * compute the dlist here and have all active plane dlists get updated
 654  * in the CRTC's flush.
 655  */
 656 static int vc4_plane_atomic_check(struct drm_plane *plane,
 657                                   struct drm_plane_state *state)
 658 {
 659         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 660
 661         vc4_state->dlist_count = 0;
 662
 663         if (plane_enabled(state))
 664                 return vc4_plane_mode_set(plane, state);
 665         else
 666                 return 0;
 667 }
 668
 669 static void vc4_plane_atomic_update(struct drm_plane *plane,
 670                                     struct drm_plane_state *old_state)
 671 {
 672         /* No contents here.  Since we don't know where in the CRTC's
 673          * dlist we should be stored, our dlist is uploaded to the
 674          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
 675          * time.
 676          */
 677 }
 678
 679 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
 680 {
 681         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 682         int i;
 683
 684         vc4_state->hw_dlist = dlist;
 685
 686         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
 687         for (i = 0; i < vc4_state->dlist_count; i++)
 688                 writel(vc4_state->dlist[i], &dlist[i]);
 689
 690         return vc4_state->dlist_count;
 691 }
 692
 693 u32 vc4_plane_dlist_size(struct drm_plane_state *state)
 694 {
 695         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 696
 697         return vc4_state->dlist_count;
 698 }
 699
 700 /* Updates the plane to immediately (well, once the FIFO needs
 701  * refilling) scan out from at a new framebuffer.
 702  */
 703 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
 704 {
 705         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 706         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 707         uint32_t addr;
 708
 709         /* We're skipping the address adjustment for negative origin,
 710          * because this is only called on the primary plane.
 711          */
 712         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
 713         addr = bo->paddr + fb->offsets[0];
 714
 715         /* Write the new address into the hardware immediately.  The
 716          * scanout will start from this address as soon as the FIFO
 717          * needs to refill with pixels.
 718          */
 719         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 720
 721         /* Also update the CPU-side dlist copy, so that any later
 722          * atomic updates that don't do a new modeset on our plane
 723          * also use our updated address.
 724          */
 725         vc4_state->dlist[vc4_state->ptr0_offset] = addr;
 726 }
 727
 728 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
 729         .prepare_fb = NULL,
 730         .cleanup_fb = NULL,
 731         .atomic_check = vc4_plane_atomic_check,
 732         .atomic_update = vc4_plane_atomic_update,
 733 };
 734
 735 static void vc4_plane_destroy(struct drm_plane *plane)
 736 {
 737         drm_plane_helper_disable(plane);
 738         drm_plane_cleanup(plane);
 739 }
 740
 741 /* Implements immediate (non-vblank-synced) updates of the cursor
 742  * position, or falls back to the atomic helper otherwise.
 743  */
 744 static int
 745 vc4_update_plane(struct drm_plane *plane,
 746                  struct drm_crtc *crtc,
 747                  struct drm_framebuffer *fb,
 748                  int crtc_x, int crtc_y,
 749                  unsigned int crtc_w, unsigned int crtc_h,
 750                  uint32_t src_x, uint32_t src_y,
 751                  uint32_t src_w, uint32_t src_h)
 752 {
 753         struct drm_plane_state *plane_state;
 754         struct vc4_plane_state *vc4_state;
 755
 756         if (plane != crtc->cursor)
 757                 goto out;
 758
 759         plane_state = plane->state;
 760         vc4_state = to_vc4_plane_state(plane_state);
 761
 762         if (!plane_state)
 763                 goto out;
 764
 765         /* If we're changing the cursor contents, do that in the
 766          * normal vblank-synced atomic path.
 767          */
 768         if (fb != plane_state->fb)
 769                 goto out;
 770
 771         /* No configuring new scaling in the fast path. */
 772         if (crtc_w != plane_state->crtc_w ||
 773             crtc_h != plane_state->crtc_h ||
 774             src_w != plane_state->src_w ||
 775             src_h != plane_state->src_h) {
 776                 goto out;
 777         }
 778
 779         /* Set the cursor's position on the screen.  This is the
 780          * expected change from the drm_mode_cursor_universal()
 781          * helper.
 782          */
 783         plane_state->crtc_x = crtc_x;
 784         plane_state->crtc_y = crtc_y;
 785
 786         /* Allow changing the start position within the cursor BO, if
 787          * that matters.
 788          */
 789         plane_state->src_x = src_x;
 790         plane_state->src_y = src_y;
 791
 792         /* Update the display list based on the new crtc_x/y. */
 793         vc4_plane_atomic_check(plane, plane_state);
 794
 795         /* Note that we can't just call vc4_plane_write_dlist()
 796          * because that would smash the context data that the HVS is
 797          * currently using.
 798          */
 799         writel(vc4_state->dlist[vc4_state->pos0_offset],
 800                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
 801         writel(vc4_state->dlist[vc4_state->pos2_offset],
 802                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
 803         writel(vc4_state->dlist[vc4_state->ptr0_offset],
 804                &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 805
 806         return 0;
 807
 808 out:
 809         return drm_atomic_helper_update_plane(plane, crtc, fb,
 810                                               crtc_x, crtc_y,
 811                                               crtc_w, crtc_h,
 812                                               src_x, src_y,
 813                                               src_w, src_h);
 814 }
 815
 816 static const struct drm_plane_funcs vc4_plane_funcs = {
 817         .update_plane = vc4_update_plane,
 818         .disable_plane = drm_atomic_helper_disable_plane,
 819         .destroy = vc4_plane_destroy,
 820         .set_property = NULL,
 821         .reset = vc4_plane_reset,
 822         .atomic_duplicate_state = vc4_plane_duplicate_state,
 823         .atomic_destroy_state = vc4_plane_destroy_state,
 824 };
 825
 826 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 827                                  enum drm_plane_type type)
 828 {
 829         struct drm_plane *plane = NULL;
 830         struct vc4_plane *vc4_plane;
 831         u32 formats[ARRAY_SIZE(hvs_formats)];
 832         u32 num_formats = 0;
 833         int ret = 0;
 834         unsigned i;
 835
 836         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
 837                                  GFP_KERNEL);
 838         if (!vc4_plane) {
 839                 ret = -ENOMEM;
 840                 goto fail;
 841         }
 842
 843         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 844                 /* Don't allow YUV in cursor planes, since that means
 845                  * tuning on the scaler, which we don't allow for the
 846                  * cursor.
 847                  */
 848                 if (type != DRM_PLANE_TYPE_CURSOR ||
 849                     hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
 850                         formats[num_formats++] = hvs_formats[i].drm;
 851                 }
 852         }
 853         plane = &vc4_plane->base;
 854         ret = drm_universal_plane_init(dev, plane, 0xff,
 855                                        &vc4_plane_funcs,
 856                                        formats, num_formats,
 857                                        type, NULL);
 858
 859         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
 860
 861         return plane;
 862 fail:
 863         if (plane)
 864                 vc4_plane_destroy(plane);
 865
 866         return ERR_PTR(ret);
 867 }