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drm/vmwgfx: Persistent tracking of context bindings
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
1 /**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27 #include <linux/module.h>
28
29 #include <drm/drmP.h>
30 #include "vmwgfx_drv.h"
31 #include <drm/ttm/ttm_placement.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <drm/ttm/ttm_object.h>
34 #include <drm/ttm/ttm_module.h>
35 #include <linux/dma_remapping.h>
36
37 #define VMWGFX_DRIVER_NAME "vmwgfx"
38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39 #define VMWGFX_CHIP_SVGAII 0
40 #define VMW_FB_RESERVATION 0
41
42 #define VMW_MIN_INITIAL_WIDTH 800
43 #define VMW_MIN_INITIAL_HEIGHT 600
44
45
46 /**
47 * Fully encoded drm commands. Might move to vmw_drm.h
48 */
49
50 #define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56 #define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63 #define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66 #define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69 #define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79 #define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82 #define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85 #define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88 #define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
91 #define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
94 #define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
97 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100 #define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
103 #define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
106 #define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109 #define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
115 #define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118 #define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
127 #define DRM_IOCTL_VMW_SYNCCPU \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
129 struct drm_vmw_synccpu_arg)
130
131 /**
132 * The core DRM version of this macro doesn't account for
133 * DRM_COMMAND_BASE.
134 */
135
136 #define VMW_IOCTL_DEF(ioctl, func, flags) \
137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
138
139 /**
140 * Ioctl definitions.
141 */
142
143 static const struct drm_ioctl_desc vmw_ioctls[] = {
144 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
145 DRM_AUTH | DRM_UNLOCKED),
146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
147 DRM_AUTH | DRM_UNLOCKED),
148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
149 DRM_AUTH | DRM_UNLOCKED),
150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
151 vmw_kms_cursor_bypass_ioctl,
152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
153
154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
155 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
157 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
158 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
160
161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
162 DRM_AUTH | DRM_UNLOCKED),
163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
164 DRM_AUTH | DRM_UNLOCKED),
165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
166 DRM_AUTH | DRM_UNLOCKED),
167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
168 DRM_AUTH | DRM_UNLOCKED),
169 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
170 DRM_AUTH | DRM_UNLOCKED),
171 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
172 DRM_AUTH | DRM_UNLOCKED),
173 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
174 DRM_AUTH | DRM_UNLOCKED),
175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176 vmw_fence_obj_signaled_ioctl,
177 DRM_AUTH | DRM_UNLOCKED),
178 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
179 DRM_AUTH | DRM_UNLOCKED),
180 VMW_IOCTL_DEF(VMW_FENCE_EVENT,
181 vmw_fence_event_ioctl,
182 DRM_AUTH | DRM_UNLOCKED),
183 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
184 DRM_AUTH | DRM_UNLOCKED),
185
186 /* these allow direct access to the framebuffers mark as master only */
187 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
188 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
189 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
190 vmw_present_readback_ioctl,
191 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
192 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
193 vmw_kms_update_layout_ioctl,
194 DRM_MASTER | DRM_UNLOCKED),
195 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
196 vmw_shader_define_ioctl,
197 DRM_AUTH | DRM_UNLOCKED),
198 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
199 vmw_shader_destroy_ioctl,
200 DRM_AUTH | DRM_UNLOCKED),
201 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
202 vmw_gb_surface_define_ioctl,
203 DRM_AUTH | DRM_UNLOCKED),
204 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
205 vmw_gb_surface_reference_ioctl,
206 DRM_AUTH | DRM_UNLOCKED),
207 VMW_IOCTL_DEF(VMW_SYNCCPU,
208 vmw_user_dmabuf_synccpu_ioctl,
209 DRM_AUTH | DRM_UNLOCKED),
210 };
211
212 static struct pci_device_id vmw_pci_id_list[] = {
213 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
214 {0, 0, 0}
215 };
216 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
217
218 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
219 static int vmw_force_iommu;
220 static int vmw_restrict_iommu;
221 static int vmw_force_coherent;
222 static int vmw_restrict_dma_mask;
223
224 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
225 static void vmw_master_init(struct vmw_master *);
226 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
227 void *ptr);
228
229 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
230 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
231 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
232 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
233 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
234 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
235 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
236 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
237 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
238 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
239
240
241 static void vmw_print_capabilities(uint32_t capabilities)
242 {
243 DRM_INFO("Capabilities:\n");
244 if (capabilities & SVGA_CAP_RECT_COPY)
245 DRM_INFO(" Rect copy.\n");
246 if (capabilities & SVGA_CAP_CURSOR)
247 DRM_INFO(" Cursor.\n");
248 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
249 DRM_INFO(" Cursor bypass.\n");
250 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
251 DRM_INFO(" Cursor bypass 2.\n");
252 if (capabilities & SVGA_CAP_8BIT_EMULATION)
253 DRM_INFO(" 8bit emulation.\n");
254 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
255 DRM_INFO(" Alpha cursor.\n");
256 if (capabilities & SVGA_CAP_3D)
257 DRM_INFO(" 3D.\n");
258 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
259 DRM_INFO(" Extended Fifo.\n");
260 if (capabilities & SVGA_CAP_MULTIMON)
261 DRM_INFO(" Multimon.\n");
262 if (capabilities & SVGA_CAP_PITCHLOCK)
263 DRM_INFO(" Pitchlock.\n");
264 if (capabilities & SVGA_CAP_IRQMASK)
265 DRM_INFO(" Irq mask.\n");
266 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
267 DRM_INFO(" Display Topology.\n");
268 if (capabilities & SVGA_CAP_GMR)
269 DRM_INFO(" GMR.\n");
270 if (capabilities & SVGA_CAP_TRACES)
271 DRM_INFO(" Traces.\n");
272 if (capabilities & SVGA_CAP_GMR2)
273 DRM_INFO(" GMR2.\n");
274 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
275 DRM_INFO(" Screen Object 2.\n");
276 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
277 DRM_INFO(" Command Buffers.\n");
278 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
279 DRM_INFO(" Command Buffers 2.\n");
280 if (capabilities & SVGA_CAP_GBOBJECTS)
281 DRM_INFO(" Guest Backed Resources.\n");
282 }
283
284
285 /**
286 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
287 * the start of a buffer object.
288 *
289 * @dev_priv: The device private structure.
290 *
291 * This function will idle the buffer using an uninterruptible wait, then
292 * map the first page and initialize a pending occlusion query result structure,
293 * Finally it will unmap the buffer.
294 *
295 * TODO: Since we're only mapping a single page, we should optimize the map
296 * to use kmap_atomic / iomap_atomic.
297 */
298 static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
299 {
300 struct ttm_bo_kmap_obj map;
301 volatile SVGA3dQueryResult *result;
302 bool dummy;
303 int ret;
304 struct ttm_bo_device *bdev = &dev_priv->bdev;
305 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
306
307 ttm_bo_reserve(bo, false, false, false, 0);
308 spin_lock(&bdev->fence_lock);
309 ret = ttm_bo_wait(bo, false, false, false);
310 spin_unlock(&bdev->fence_lock);
311 if (unlikely(ret != 0))
312 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
313 10*HZ);
314
315 ret = ttm_bo_kmap(bo, 0, 1, &map);
316 if (likely(ret == 0)) {
317 result = ttm_kmap_obj_virtual(&map, &dummy);
318 result->totalSize = sizeof(*result);
319 result->state = SVGA3D_QUERYSTATE_PENDING;
320 result->result32 = 0xff;
321 ttm_bo_kunmap(&map);
322 } else
323 DRM_ERROR("Dummy query buffer map failed.\n");
324 ttm_bo_unreserve(bo);
325 }
326
327
328 /**
329 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
330 *
331 * @dev_priv: A device private structure.
332 *
333 * This function creates a small buffer object that holds the query
334 * result for dummy queries emitted as query barriers.
335 * No interruptible waits are done within this function.
336 *
337 * Returns an error if bo creation fails.
338 */
339 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
340 {
341 return ttm_bo_create(&dev_priv->bdev,
342 PAGE_SIZE,
343 ttm_bo_type_device,
344 &vmw_vram_sys_placement,
345 0, false, NULL,
346 &dev_priv->dummy_query_bo);
347 }
348
349
350 static int vmw_request_device(struct vmw_private *dev_priv)
351 {
352 int ret;
353
354 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
355 if (unlikely(ret != 0)) {
356 DRM_ERROR("Unable to initialize FIFO.\n");
357 return ret;
358 }
359 vmw_fence_fifo_up(dev_priv->fman);
360 if (dev_priv->has_mob) {
361 ret = vmw_otables_setup(dev_priv);
362 if (unlikely(ret != 0)) {
363 DRM_ERROR("Unable to initialize "
364 "guest Memory OBjects.\n");
365 goto out_no_mob;
366 }
367 }
368 ret = vmw_dummy_query_bo_create(dev_priv);
369 if (unlikely(ret != 0))
370 goto out_no_query_bo;
371 vmw_dummy_query_bo_prepare(dev_priv);
372
373 return 0;
374
375 out_no_query_bo:
376 if (dev_priv->has_mob)
377 vmw_otables_takedown(dev_priv);
378 out_no_mob:
379 vmw_fence_fifo_down(dev_priv->fman);
380 vmw_fifo_release(dev_priv, &dev_priv->fifo);
381 return ret;
382 }
383
384 static void vmw_release_device(struct vmw_private *dev_priv)
385 {
386 /*
387 * Previous destructions should've released
388 * the pinned bo.
389 */
390
391 BUG_ON(dev_priv->pinned_bo != NULL);
392
393 ttm_bo_unref(&dev_priv->dummy_query_bo);
394 if (dev_priv->has_mob)
395 vmw_otables_takedown(dev_priv);
396 vmw_fence_fifo_down(dev_priv->fman);
397 vmw_fifo_release(dev_priv, &dev_priv->fifo);
398 }
399
400
401 /**
402 * Increase the 3d resource refcount.
403 * If the count was prevously zero, initialize the fifo, switching to svga
404 * mode. Note that the master holds a ref as well, and may request an
405 * explicit switch to svga mode if fb is not running, using @unhide_svga.
406 */
407 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
408 bool unhide_svga)
409 {
410 int ret = 0;
411
412 mutex_lock(&dev_priv->release_mutex);
413 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
414 ret = vmw_request_device(dev_priv);
415 if (unlikely(ret != 0))
416 --dev_priv->num_3d_resources;
417 } else if (unhide_svga) {
418 mutex_lock(&dev_priv->hw_mutex);
419 vmw_write(dev_priv, SVGA_REG_ENABLE,
420 vmw_read(dev_priv, SVGA_REG_ENABLE) &
421 ~SVGA_REG_ENABLE_HIDE);
422 mutex_unlock(&dev_priv->hw_mutex);
423 }
424
425 mutex_unlock(&dev_priv->release_mutex);
426 return ret;
427 }
428
429 /**
430 * Decrease the 3d resource refcount.
431 * If the count reaches zero, disable the fifo, switching to vga mode.
432 * Note that the master holds a refcount as well, and may request an
433 * explicit switch to vga mode when it releases its refcount to account
434 * for the situation of an X server vt switch to VGA with 3d resources
435 * active.
436 */
437 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
438 bool hide_svga)
439 {
440 int32_t n3d;
441
442 mutex_lock(&dev_priv->release_mutex);
443 if (unlikely(--dev_priv->num_3d_resources == 0))
444 vmw_release_device(dev_priv);
445 else if (hide_svga) {
446 mutex_lock(&dev_priv->hw_mutex);
447 vmw_write(dev_priv, SVGA_REG_ENABLE,
448 vmw_read(dev_priv, SVGA_REG_ENABLE) |
449 SVGA_REG_ENABLE_HIDE);
450 mutex_unlock(&dev_priv->hw_mutex);
451 }
452
453 n3d = (int32_t) dev_priv->num_3d_resources;
454 mutex_unlock(&dev_priv->release_mutex);
455
456 BUG_ON(n3d < 0);
457 }
458
459 /**
460 * Sets the initial_[width|height] fields on the given vmw_private.
461 *
462 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
463 * clamping the value to fb_max_[width|height] fields and the
464 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
465 * If the values appear to be invalid, set them to
466 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
467 */
468 static void vmw_get_initial_size(struct vmw_private *dev_priv)
469 {
470 uint32_t width;
471 uint32_t height;
472
473 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
474 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
475
476 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
477 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
478
479 if (width > dev_priv->fb_max_width ||
480 height > dev_priv->fb_max_height) {
481
482 /*
483 * This is a host error and shouldn't occur.
484 */
485
486 width = VMW_MIN_INITIAL_WIDTH;
487 height = VMW_MIN_INITIAL_HEIGHT;
488 }
489
490 dev_priv->initial_width = width;
491 dev_priv->initial_height = height;
492 }
493
494 /**
495 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
496 * system.
497 *
498 * @dev_priv: Pointer to a struct vmw_private
499 *
500 * This functions tries to determine the IOMMU setup and what actions
501 * need to be taken by the driver to make system pages visible to the
502 * device.
503 * If this function decides that DMA is not possible, it returns -EINVAL.
504 * The driver may then try to disable features of the device that require
505 * DMA.
506 */
507 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
508 {
509 static const char *names[vmw_dma_map_max] = {
510 [vmw_dma_phys] = "Using physical TTM page addresses.",
511 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
512 [vmw_dma_map_populate] = "Keeping DMA mappings.",
513 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
514 #ifdef CONFIG_X86
515 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
516
517 #ifdef CONFIG_INTEL_IOMMU
518 if (intel_iommu_enabled) {
519 dev_priv->map_mode = vmw_dma_map_populate;
520 goto out_fixup;
521 }
522 #endif
523
524 if (!(vmw_force_iommu || vmw_force_coherent)) {
525 dev_priv->map_mode = vmw_dma_phys;
526 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
527 return 0;
528 }
529
530 dev_priv->map_mode = vmw_dma_map_populate;
531
532 if (dma_ops->sync_single_for_cpu)
533 dev_priv->map_mode = vmw_dma_alloc_coherent;
534 #ifdef CONFIG_SWIOTLB
535 if (swiotlb_nr_tbl() == 0)
536 dev_priv->map_mode = vmw_dma_map_populate;
537 #endif
538
539 #ifdef CONFIG_INTEL_IOMMU
540 out_fixup:
541 #endif
542 if (dev_priv->map_mode == vmw_dma_map_populate &&
543 vmw_restrict_iommu)
544 dev_priv->map_mode = vmw_dma_map_bind;
545
546 if (vmw_force_coherent)
547 dev_priv->map_mode = vmw_dma_alloc_coherent;
548
549 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
550 /*
551 * No coherent page pool
552 */
553 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
554 return -EINVAL;
555 #endif
556
557 #else /* CONFIG_X86 */
558 dev_priv->map_mode = vmw_dma_map_populate;
559 #endif /* CONFIG_X86 */
560
561 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
562
563 return 0;
564 }
565
566 /**
567 * vmw_dma_masks - set required page- and dma masks
568 *
569 * @dev: Pointer to struct drm-device
570 *
571 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
572 * restriction also for 64-bit systems.
573 */
574 #ifdef CONFIG_INTEL_IOMMU
575 static int vmw_dma_masks(struct vmw_private *dev_priv)
576 {
577 struct drm_device *dev = dev_priv->dev;
578
579 if (intel_iommu_enabled &&
580 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
581 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
582 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
583 }
584 return 0;
585 }
586 #else
587 static int vmw_dma_masks(struct vmw_private *dev_priv)
588 {
589 return 0;
590 }
591 #endif
592
593 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
594 {
595 struct vmw_private *dev_priv;
596 int ret;
597 uint32_t svga_id;
598 enum vmw_res_type i;
599 bool refuse_dma = false;
600
601 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
602 if (unlikely(dev_priv == NULL)) {
603 DRM_ERROR("Failed allocating a device private struct.\n");
604 return -ENOMEM;
605 }
606
607 pci_set_master(dev->pdev);
608
609 dev_priv->dev = dev;
610 dev_priv->vmw_chipset = chipset;
611 dev_priv->last_read_seqno = (uint32_t) -100;
612 mutex_init(&dev_priv->hw_mutex);
613 mutex_init(&dev_priv->cmdbuf_mutex);
614 mutex_init(&dev_priv->release_mutex);
615 mutex_init(&dev_priv->binding_mutex);
616 rwlock_init(&dev_priv->resource_lock);
617
618 for (i = vmw_res_context; i < vmw_res_max; ++i) {
619 idr_init(&dev_priv->res_idr[i]);
620 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
621 }
622
623 mutex_init(&dev_priv->init_mutex);
624 init_waitqueue_head(&dev_priv->fence_queue);
625 init_waitqueue_head(&dev_priv->fifo_queue);
626 dev_priv->fence_queue_waiters = 0;
627 atomic_set(&dev_priv->fifo_queue_waiters, 0);
628
629 dev_priv->used_memory_size = 0;
630
631 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
632 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
633 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
634
635 dev_priv->enable_fb = enable_fbdev;
636
637 mutex_lock(&dev_priv->hw_mutex);
638
639 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
640 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
641 if (svga_id != SVGA_ID_2) {
642 ret = -ENOSYS;
643 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
644 mutex_unlock(&dev_priv->hw_mutex);
645 goto out_err0;
646 }
647
648 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
649 ret = vmw_dma_select_mode(dev_priv);
650 if (unlikely(ret != 0)) {
651 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
652 refuse_dma = true;
653 }
654
655 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
656 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
657 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
658 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
659
660 vmw_get_initial_size(dev_priv);
661
662 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
663 dev_priv->max_gmr_ids =
664 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
665 dev_priv->max_gmr_pages =
666 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
667 dev_priv->memory_size =
668 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
669 dev_priv->memory_size -= dev_priv->vram_size;
670 } else {
671 /*
672 * An arbitrary limit of 512MiB on surface
673 * memory. But all HWV8 hardware supports GMR2.
674 */
675 dev_priv->memory_size = 512*1024*1024;
676 }
677 dev_priv->max_mob_pages = 0;
678 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
679 uint64_t mem_size =
680 vmw_read(dev_priv,
681 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
682
683 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
684 dev_priv->prim_bb_mem =
685 vmw_read(dev_priv,
686 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
687 } else
688 dev_priv->prim_bb_mem = dev_priv->vram_size;
689
690 ret = vmw_dma_masks(dev_priv);
691 if (unlikely(ret != 0))
692 goto out_err0;
693
694 if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
695 dev_priv->prim_bb_mem = dev_priv->vram_size;
696
697 mutex_unlock(&dev_priv->hw_mutex);
698
699 vmw_print_capabilities(dev_priv->capabilities);
700
701 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
702 DRM_INFO("Max GMR ids is %u\n",
703 (unsigned)dev_priv->max_gmr_ids);
704 DRM_INFO("Max number of GMR pages is %u\n",
705 (unsigned)dev_priv->max_gmr_pages);
706 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
707 (unsigned)dev_priv->memory_size / 1024);
708 }
709 DRM_INFO("Maximum display memory size is %u kiB\n",
710 dev_priv->prim_bb_mem / 1024);
711 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
712 dev_priv->vram_start, dev_priv->vram_size / 1024);
713 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
714 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
715
716 ret = vmw_ttm_global_init(dev_priv);
717 if (unlikely(ret != 0))
718 goto out_err0;
719
720
721 vmw_master_init(&dev_priv->fbdev_master);
722 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
723 dev_priv->active_master = &dev_priv->fbdev_master;
724
725
726 ret = ttm_bo_device_init(&dev_priv->bdev,
727 dev_priv->bo_global_ref.ref.object,
728 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
729 false);
730 if (unlikely(ret != 0)) {
731 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
732 goto out_err1;
733 }
734
735 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
736 (dev_priv->vram_size >> PAGE_SHIFT));
737 if (unlikely(ret != 0)) {
738 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
739 goto out_err2;
740 }
741
742 dev_priv->has_gmr = true;
743 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
744 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
745 VMW_PL_GMR) != 0) {
746 DRM_INFO("No GMR memory available. "
747 "Graphics memory resources are very limited.\n");
748 dev_priv->has_gmr = false;
749 }
750
751 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
752 dev_priv->has_mob = true;
753 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
754 VMW_PL_MOB) != 0) {
755 DRM_INFO("No MOB memory available. "
756 "3D will be disabled.\n");
757 dev_priv->has_mob = false;
758 }
759 }
760
761 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
762 dev_priv->mmio_size);
763
764 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
765 dev_priv->mmio_size);
766
767 if (unlikely(dev_priv->mmio_virt == NULL)) {
768 ret = -ENOMEM;
769 DRM_ERROR("Failed mapping MMIO.\n");
770 goto out_err3;
771 }
772
773 /* Need mmio memory to check for fifo pitchlock cap. */
774 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
775 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
776 !vmw_fifo_have_pitchlock(dev_priv)) {
777 ret = -ENOSYS;
778 DRM_ERROR("Hardware has no pitchlock\n");
779 goto out_err4;
780 }
781
782 dev_priv->tdev = ttm_object_device_init
783 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
784
785 if (unlikely(dev_priv->tdev == NULL)) {
786 DRM_ERROR("Unable to initialize TTM object management.\n");
787 ret = -ENOMEM;
788 goto out_err4;
789 }
790
791 dev->dev_private = dev_priv;
792
793 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
794 dev_priv->stealth = (ret != 0);
795 if (dev_priv->stealth) {
796 /**
797 * Request at least the mmio PCI resource.
798 */
799
800 DRM_INFO("It appears like vesafb is loaded. "
801 "Ignore above error if any.\n");
802 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
803 if (unlikely(ret != 0)) {
804 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
805 goto out_no_device;
806 }
807 }
808
809 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
810 ret = drm_irq_install(dev);
811 if (ret != 0) {
812 DRM_ERROR("Failed installing irq: %d\n", ret);
813 goto out_no_irq;
814 }
815 }
816
817 dev_priv->fman = vmw_fence_manager_init(dev_priv);
818 if (unlikely(dev_priv->fman == NULL)) {
819 ret = -ENOMEM;
820 goto out_no_fman;
821 }
822
823 vmw_kms_save_vga(dev_priv);
824
825 /* Start kms and overlay systems, needs fifo. */
826 ret = vmw_kms_init(dev_priv);
827 if (unlikely(ret != 0))
828 goto out_no_kms;
829 vmw_overlay_init(dev_priv);
830
831 if (dev_priv->enable_fb) {
832 ret = vmw_3d_resource_inc(dev_priv, true);
833 if (unlikely(ret != 0))
834 goto out_no_fifo;
835 vmw_fb_init(dev_priv);
836 }
837
838 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
839 register_pm_notifier(&dev_priv->pm_nb);
840
841 return 0;
842
843 out_no_fifo:
844 vmw_overlay_close(dev_priv);
845 vmw_kms_close(dev_priv);
846 out_no_kms:
847 vmw_kms_restore_vga(dev_priv);
848 vmw_fence_manager_takedown(dev_priv->fman);
849 out_no_fman:
850 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
851 drm_irq_uninstall(dev_priv->dev);
852 out_no_irq:
853 if (dev_priv->stealth)
854 pci_release_region(dev->pdev, 2);
855 else
856 pci_release_regions(dev->pdev);
857 out_no_device:
858 ttm_object_device_release(&dev_priv->tdev);
859 out_err4:
860 iounmap(dev_priv->mmio_virt);
861 out_err3:
862 arch_phys_wc_del(dev_priv->mmio_mtrr);
863 if (dev_priv->has_mob)
864 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
865 if (dev_priv->has_gmr)
866 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
867 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
868 out_err2:
869 (void)ttm_bo_device_release(&dev_priv->bdev);
870 out_err1:
871 vmw_ttm_global_release(dev_priv);
872 out_err0:
873 for (i = vmw_res_context; i < vmw_res_max; ++i)
874 idr_destroy(&dev_priv->res_idr[i]);
875
876 kfree(dev_priv);
877 return ret;
878 }
879
880 static int vmw_driver_unload(struct drm_device *dev)
881 {
882 struct vmw_private *dev_priv = vmw_priv(dev);
883 enum vmw_res_type i;
884
885 unregister_pm_notifier(&dev_priv->pm_nb);
886
887 if (dev_priv->ctx.res_ht_initialized)
888 drm_ht_remove(&dev_priv->ctx.res_ht);
889 if (dev_priv->ctx.cmd_bounce)
890 vfree(dev_priv->ctx.cmd_bounce);
891 if (dev_priv->enable_fb) {
892 vmw_fb_close(dev_priv);
893 vmw_kms_restore_vga(dev_priv);
894 vmw_3d_resource_dec(dev_priv, false);
895 }
896 vmw_kms_close(dev_priv);
897 vmw_overlay_close(dev_priv);
898 vmw_fence_manager_takedown(dev_priv->fman);
899 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
900 drm_irq_uninstall(dev_priv->dev);
901 if (dev_priv->stealth)
902 pci_release_region(dev->pdev, 2);
903 else
904 pci_release_regions(dev->pdev);
905
906 ttm_object_device_release(&dev_priv->tdev);
907 iounmap(dev_priv->mmio_virt);
908 arch_phys_wc_del(dev_priv->mmio_mtrr);
909 if (dev_priv->has_mob)
910 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
911 if (dev_priv->has_gmr)
912 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
913 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
914 (void)ttm_bo_device_release(&dev_priv->bdev);
915 vmw_ttm_global_release(dev_priv);
916
917 for (i = vmw_res_context; i < vmw_res_max; ++i)
918 idr_destroy(&dev_priv->res_idr[i]);
919
920 kfree(dev_priv);
921
922 return 0;
923 }
924
925 static void vmw_preclose(struct drm_device *dev,
926 struct drm_file *file_priv)
927 {
928 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
929 struct vmw_private *dev_priv = vmw_priv(dev);
930
931 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
932 }
933
934 static void vmw_postclose(struct drm_device *dev,
935 struct drm_file *file_priv)
936 {
937 struct vmw_fpriv *vmw_fp;
938
939 vmw_fp = vmw_fpriv(file_priv);
940
941 if (vmw_fp->locked_master) {
942 struct vmw_master *vmaster =
943 vmw_master(vmw_fp->locked_master);
944
945 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
946 ttm_vt_unlock(&vmaster->lock);
947 drm_master_put(&vmw_fp->locked_master);
948 }
949
950 ttm_object_file_release(&vmw_fp->tfile);
951 kfree(vmw_fp);
952 }
953
954 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
955 {
956 struct vmw_private *dev_priv = vmw_priv(dev);
957 struct vmw_fpriv *vmw_fp;
958 int ret = -ENOMEM;
959
960 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
961 if (unlikely(vmw_fp == NULL))
962 return ret;
963
964 INIT_LIST_HEAD(&vmw_fp->fence_events);
965 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
966 if (unlikely(vmw_fp->tfile == NULL))
967 goto out_no_tfile;
968
969 file_priv->driver_priv = vmw_fp;
970 dev_priv->bdev.dev_mapping = dev->dev_mapping;
971
972 return 0;
973
974 out_no_tfile:
975 kfree(vmw_fp);
976 return ret;
977 }
978
979 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
980 unsigned long arg)
981 {
982 struct drm_file *file_priv = filp->private_data;
983 struct drm_device *dev = file_priv->minor->dev;
984 unsigned int nr = DRM_IOCTL_NR(cmd);
985
986 /*
987 * Do extra checking on driver private ioctls.
988 */
989
990 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
991 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
992 const struct drm_ioctl_desc *ioctl =
993 &vmw_ioctls[nr - DRM_COMMAND_BASE];
994
995 if (unlikely(ioctl->cmd_drv != cmd)) {
996 DRM_ERROR("Invalid command format, ioctl %d\n",
997 nr - DRM_COMMAND_BASE);
998 return -EINVAL;
999 }
1000 }
1001
1002 return drm_ioctl(filp, cmd, arg);
1003 }
1004
1005 static void vmw_lastclose(struct drm_device *dev)
1006 {
1007 struct drm_crtc *crtc;
1008 struct drm_mode_set set;
1009 int ret;
1010
1011 set.x = 0;
1012 set.y = 0;
1013 set.fb = NULL;
1014 set.mode = NULL;
1015 set.connectors = NULL;
1016 set.num_connectors = 0;
1017
1018 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1019 set.crtc = crtc;
1020 ret = drm_mode_set_config_internal(&set);
1021 WARN_ON(ret != 0);
1022 }
1023
1024 }
1025
1026 static void vmw_master_init(struct vmw_master *vmaster)
1027 {
1028 ttm_lock_init(&vmaster->lock);
1029 INIT_LIST_HEAD(&vmaster->fb_surf);
1030 mutex_init(&vmaster->fb_surf_mutex);
1031 }
1032
1033 static int vmw_master_create(struct drm_device *dev,
1034 struct drm_master *master)
1035 {
1036 struct vmw_master *vmaster;
1037
1038 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1039 if (unlikely(vmaster == NULL))
1040 return -ENOMEM;
1041
1042 vmw_master_init(vmaster);
1043 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1044 master->driver_priv = vmaster;
1045
1046 return 0;
1047 }
1048
1049 static void vmw_master_destroy(struct drm_device *dev,
1050 struct drm_master *master)
1051 {
1052 struct vmw_master *vmaster = vmw_master(master);
1053
1054 master->driver_priv = NULL;
1055 kfree(vmaster);
1056 }
1057
1058
1059 static int vmw_master_set(struct drm_device *dev,
1060 struct drm_file *file_priv,
1061 bool from_open)
1062 {
1063 struct vmw_private *dev_priv = vmw_priv(dev);
1064 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1065 struct vmw_master *active = dev_priv->active_master;
1066 struct vmw_master *vmaster = vmw_master(file_priv->master);
1067 int ret = 0;
1068
1069 if (!dev_priv->enable_fb) {
1070 ret = vmw_3d_resource_inc(dev_priv, true);
1071 if (unlikely(ret != 0))
1072 return ret;
1073 vmw_kms_save_vga(dev_priv);
1074 mutex_lock(&dev_priv->hw_mutex);
1075 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1076 mutex_unlock(&dev_priv->hw_mutex);
1077 }
1078
1079 if (active) {
1080 BUG_ON(active != &dev_priv->fbdev_master);
1081 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1082 if (unlikely(ret != 0))
1083 goto out_no_active_lock;
1084
1085 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1086 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1087 if (unlikely(ret != 0)) {
1088 DRM_ERROR("Unable to clean VRAM on "
1089 "master drop.\n");
1090 }
1091
1092 dev_priv->active_master = NULL;
1093 }
1094
1095 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1096 if (!from_open) {
1097 ttm_vt_unlock(&vmaster->lock);
1098 BUG_ON(vmw_fp->locked_master != file_priv->master);
1099 drm_master_put(&vmw_fp->locked_master);
1100 }
1101
1102 dev_priv->active_master = vmaster;
1103
1104 return 0;
1105
1106 out_no_active_lock:
1107 if (!dev_priv->enable_fb) {
1108 vmw_kms_restore_vga(dev_priv);
1109 vmw_3d_resource_dec(dev_priv, true);
1110 mutex_lock(&dev_priv->hw_mutex);
1111 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1112 mutex_unlock(&dev_priv->hw_mutex);
1113 }
1114 return ret;
1115 }
1116
1117 static void vmw_master_drop(struct drm_device *dev,
1118 struct drm_file *file_priv,
1119 bool from_release)
1120 {
1121 struct vmw_private *dev_priv = vmw_priv(dev);
1122 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1123 struct vmw_master *vmaster = vmw_master(file_priv->master);
1124 int ret;
1125
1126 /**
1127 * Make sure the master doesn't disappear while we have
1128 * it locked.
1129 */
1130
1131 vmw_fp->locked_master = drm_master_get(file_priv->master);
1132 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1133 if (unlikely((ret != 0))) {
1134 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1135 drm_master_put(&vmw_fp->locked_master);
1136 }
1137
1138 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1139 vmw_execbuf_release_pinned_bo(dev_priv);
1140
1141 if (!dev_priv->enable_fb) {
1142 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1143 if (unlikely(ret != 0))
1144 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1145 vmw_kms_restore_vga(dev_priv);
1146 vmw_3d_resource_dec(dev_priv, true);
1147 mutex_lock(&dev_priv->hw_mutex);
1148 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1149 mutex_unlock(&dev_priv->hw_mutex);
1150 }
1151
1152 dev_priv->active_master = &dev_priv->fbdev_master;
1153 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1154 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1155
1156 if (dev_priv->enable_fb)
1157 vmw_fb_on(dev_priv);
1158 }
1159
1160
1161 static void vmw_remove(struct pci_dev *pdev)
1162 {
1163 struct drm_device *dev = pci_get_drvdata(pdev);
1164
1165 drm_put_dev(dev);
1166 }
1167
1168 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1169 void *ptr)
1170 {
1171 struct vmw_private *dev_priv =
1172 container_of(nb, struct vmw_private, pm_nb);
1173 struct vmw_master *vmaster = dev_priv->active_master;
1174
1175 switch (val) {
1176 case PM_HIBERNATION_PREPARE:
1177 case PM_SUSPEND_PREPARE:
1178 ttm_suspend_lock(&vmaster->lock);
1179
1180 /**
1181 * This empties VRAM and unbinds all GMR bindings.
1182 * Buffer contents is moved to swappable memory.
1183 */
1184 vmw_execbuf_release_pinned_bo(dev_priv);
1185 vmw_resource_evict_all(dev_priv);
1186 ttm_bo_swapout_all(&dev_priv->bdev);
1187
1188 break;
1189 case PM_POST_HIBERNATION:
1190 case PM_POST_SUSPEND:
1191 case PM_POST_RESTORE:
1192 ttm_suspend_unlock(&vmaster->lock);
1193
1194 break;
1195 case PM_RESTORE_PREPARE:
1196 break;
1197 default:
1198 break;
1199 }
1200 return 0;
1201 }
1202
1203 /**
1204 * These might not be needed with the virtual SVGA device.
1205 */
1206
1207 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1208 {
1209 struct drm_device *dev = pci_get_drvdata(pdev);
1210 struct vmw_private *dev_priv = vmw_priv(dev);
1211
1212 if (dev_priv->num_3d_resources != 0) {
1213 DRM_INFO("Can't suspend or hibernate "
1214 "while 3D resources are active.\n");
1215 return -EBUSY;
1216 }
1217
1218 pci_save_state(pdev);
1219 pci_disable_device(pdev);
1220 pci_set_power_state(pdev, PCI_D3hot);
1221 return 0;
1222 }
1223
1224 static int vmw_pci_resume(struct pci_dev *pdev)
1225 {
1226 pci_set_power_state(pdev, PCI_D0);
1227 pci_restore_state(pdev);
1228 return pci_enable_device(pdev);
1229 }
1230
1231 static int vmw_pm_suspend(struct device *kdev)
1232 {
1233 struct pci_dev *pdev = to_pci_dev(kdev);
1234 struct pm_message dummy;
1235
1236 dummy.event = 0;
1237
1238 return vmw_pci_suspend(pdev, dummy);
1239 }
1240
1241 static int vmw_pm_resume(struct device *kdev)
1242 {
1243 struct pci_dev *pdev = to_pci_dev(kdev);
1244
1245 return vmw_pci_resume(pdev);
1246 }
1247
1248 static int vmw_pm_prepare(struct device *kdev)
1249 {
1250 struct pci_dev *pdev = to_pci_dev(kdev);
1251 struct drm_device *dev = pci_get_drvdata(pdev);
1252 struct vmw_private *dev_priv = vmw_priv(dev);
1253
1254 /**
1255 * Release 3d reference held by fbdev and potentially
1256 * stop fifo.
1257 */
1258 dev_priv->suspended = true;
1259 if (dev_priv->enable_fb)
1260 vmw_3d_resource_dec(dev_priv, true);
1261
1262 if (dev_priv->num_3d_resources != 0) {
1263
1264 DRM_INFO("Can't suspend or hibernate "
1265 "while 3D resources are active.\n");
1266
1267 if (dev_priv->enable_fb)
1268 vmw_3d_resource_inc(dev_priv, true);
1269 dev_priv->suspended = false;
1270 return -EBUSY;
1271 }
1272
1273 return 0;
1274 }
1275
1276 static void vmw_pm_complete(struct device *kdev)
1277 {
1278 struct pci_dev *pdev = to_pci_dev(kdev);
1279 struct drm_device *dev = pci_get_drvdata(pdev);
1280 struct vmw_private *dev_priv = vmw_priv(dev);
1281
1282 mutex_lock(&dev_priv->hw_mutex);
1283 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1284 (void) vmw_read(dev_priv, SVGA_REG_ID);
1285 mutex_unlock(&dev_priv->hw_mutex);
1286
1287 /**
1288 * Reclaim 3d reference held by fbdev and potentially
1289 * start fifo.
1290 */
1291 if (dev_priv->enable_fb)
1292 vmw_3d_resource_inc(dev_priv, false);
1293
1294 dev_priv->suspended = false;
1295 }
1296
1297 static const struct dev_pm_ops vmw_pm_ops = {
1298 .prepare = vmw_pm_prepare,
1299 .complete = vmw_pm_complete,
1300 .suspend = vmw_pm_suspend,
1301 .resume = vmw_pm_resume,
1302 };
1303
1304 static const struct file_operations vmwgfx_driver_fops = {
1305 .owner = THIS_MODULE,
1306 .open = drm_open,
1307 .release = drm_release,
1308 .unlocked_ioctl = vmw_unlocked_ioctl,
1309 .mmap = vmw_mmap,
1310 .poll = vmw_fops_poll,
1311 .read = vmw_fops_read,
1312 #if defined(CONFIG_COMPAT)
1313 .compat_ioctl = drm_compat_ioctl,
1314 #endif
1315 .llseek = noop_llseek,
1316 };
1317
1318 static struct drm_driver driver = {
1319 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1320 DRIVER_MODESET | DRIVER_PRIME,
1321 .load = vmw_driver_load,
1322 .unload = vmw_driver_unload,
1323 .lastclose = vmw_lastclose,
1324 .irq_preinstall = vmw_irq_preinstall,
1325 .irq_postinstall = vmw_irq_postinstall,
1326 .irq_uninstall = vmw_irq_uninstall,
1327 .irq_handler = vmw_irq_handler,
1328 .get_vblank_counter = vmw_get_vblank_counter,
1329 .enable_vblank = vmw_enable_vblank,
1330 .disable_vblank = vmw_disable_vblank,
1331 .ioctls = vmw_ioctls,
1332 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1333 .master_create = vmw_master_create,
1334 .master_destroy = vmw_master_destroy,
1335 .master_set = vmw_master_set,
1336 .master_drop = vmw_master_drop,
1337 .open = vmw_driver_open,
1338 .preclose = vmw_preclose,
1339 .postclose = vmw_postclose,
1340
1341 .dumb_create = vmw_dumb_create,
1342 .dumb_map_offset = vmw_dumb_map_offset,
1343 .dumb_destroy = vmw_dumb_destroy,
1344
1345 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1346 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1347
1348 .fops = &vmwgfx_driver_fops,
1349 .name = VMWGFX_DRIVER_NAME,
1350 .desc = VMWGFX_DRIVER_DESC,
1351 .date = VMWGFX_DRIVER_DATE,
1352 .major = VMWGFX_DRIVER_MAJOR,
1353 .minor = VMWGFX_DRIVER_MINOR,
1354 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1355 };
1356
1357 static struct pci_driver vmw_pci_driver = {
1358 .name = VMWGFX_DRIVER_NAME,
1359 .id_table = vmw_pci_id_list,
1360 .probe = vmw_probe,
1361 .remove = vmw_remove,
1362 .driver = {
1363 .pm = &vmw_pm_ops
1364 }
1365 };
1366
1367 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1368 {
1369 return drm_get_pci_dev(pdev, ent, &driver);
1370 }
1371
1372 static int __init vmwgfx_init(void)
1373 {
1374 int ret;
1375 ret = drm_pci_init(&driver, &vmw_pci_driver);
1376 if (ret)
1377 DRM_ERROR("Failed initializing DRM.\n");
1378 return ret;
1379 }
1380
1381 static void __exit vmwgfx_exit(void)
1382 {
1383 drm_pci_exit(&driver, &vmw_pci_driver);
1384 }
1385
1386 module_init(vmwgfx_init);
1387 module_exit(vmwgfx_exit);
1388
1389 MODULE_AUTHOR("VMware Inc. and others");
1390 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1391 MODULE_LICENSE("GPL and additional rights");
1392 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1393 __stringify(VMWGFX_DRIVER_MINOR) "."
1394 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1395 "0");
Linux kernel - Deliverables
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