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irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro
[deliverable/linux.git] / drivers / hwmon / dme1737.c
1 /*
2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
3 * and SCH5127 Super-I/O chips integrated hardware monitoring
4 * features.
5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
6 *
7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very
10 * similar hardware monitoring capabilities but differ in the way they can be
11 * accessed.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/slab.h>
33 #include <linux/jiffies.h>
34 #include <linux/i2c.h>
35 #include <linux/platform_device.h>
36 #include <linux/hwmon.h>
37 #include <linux/hwmon-sysfs.h>
38 #include <linux/hwmon-vid.h>
39 #include <linux/err.h>
40 #include <linux/mutex.h>
41 #include <linux/acpi.h>
42 #include <linux/io.h>
43
44 /* ISA device, if found */
45 static struct platform_device *pdev;
46
47 /* Module load parameters */
48 static bool force_start;
49 module_param(force_start, bool, 0);
50 MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
51
52 static unsigned short force_id;
53 module_param(force_id, ushort, 0);
54 MODULE_PARM_DESC(force_id, "Override the detected device ID");
55
56 static bool probe_all_addr;
57 module_param(probe_all_addr, bool, 0);
58 MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC "
59 "addresses");
60
61 /* Addresses to scan */
62 static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
63
64 enum chips { dme1737, sch5027, sch311x, sch5127 };
65
66 /* ---------------------------------------------------------------------
67 * Registers
68 *
69 * The sensors are defined as follows:
70 *
71 * Voltages Temperatures
72 * -------- ------------
73 * in0 +5VTR (+5V stdby) temp1 Remote diode 1
74 * in1 Vccp (proc core) temp2 Internal temp
75 * in2 VCC (internal +3.3V) temp3 Remote diode 2
76 * in3 +5V
77 * in4 +12V
78 * in5 VTR (+3.3V stby)
79 * in6 Vbat
80 * in7 Vtrip (sch5127 only)
81 *
82 * --------------------------------------------------------------------- */
83
84 /* Voltages (in) numbered 0-7 (ix) */
85 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
86 (ix) < 7 ? 0x94 + (ix) : \
87 0x1f)
88 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
89 : 0x91 + (ix) * 2)
90 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
91 : 0x92 + (ix) * 2)
92
93 /* Temperatures (temp) numbered 0-2 (ix) */
94 #define DME1737_REG_TEMP(ix) (0x25 + (ix))
95 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
96 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
97 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
98 : 0x1c + (ix))
99
100 /*
101 * Voltage and temperature LSBs
102 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
103 * IN_TEMP_LSB(0) = [in5, in6]
104 * IN_TEMP_LSB(1) = [temp3, temp1]
105 * IN_TEMP_LSB(2) = [in4, temp2]
106 * IN_TEMP_LSB(3) = [in3, in0]
107 * IN_TEMP_LSB(4) = [in2, in1]
108 * IN_TEMP_LSB(5) = [res, in7]
109 */
110 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
111 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
112 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
113 static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
114 static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
115
116 /* Fans numbered 0-5 (ix) */
117 #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
118 : 0xa1 + (ix) * 2)
119 #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
120 : 0xa5 + (ix) * 2)
121 #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
122 : 0xb2 + (ix))
123 #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
124
125 /* PWMs numbered 0-2, 4-5 (ix) */
126 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
127 : 0xa1 + (ix))
128 #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
129 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
130 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
131 : 0xa3 + (ix))
132 /*
133 * The layout of the ramp rate registers is different from the other pwm
134 * registers. The bits for the 3 PWMs are stored in 2 registers:
135 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
136 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
137 */
138 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
139
140 /* Thermal zones 0-2 */
141 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
142 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
143 /*
144 * The layout of the hysteresis registers is different from the other zone
145 * registers. The bits for the 3 zones are stored in 2 registers:
146 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
147 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES]
148 */
149 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
150
151 /*
152 * Alarm registers and bit mapping
153 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
154 * alarm value [0, ALARM3, ALARM2, ALARM1].
155 */
156 #define DME1737_REG_ALARM1 0x41
157 #define DME1737_REG_ALARM2 0x42
158 #define DME1737_REG_ALARM3 0x83
159 static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18};
160 static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
161 static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
162
163 /* Miscellaneous registers */
164 #define DME1737_REG_DEVICE 0x3d
165 #define DME1737_REG_COMPANY 0x3e
166 #define DME1737_REG_VERSTEP 0x3f
167 #define DME1737_REG_CONFIG 0x40
168 #define DME1737_REG_CONFIG2 0x7f
169 #define DME1737_REG_VID 0x43
170 #define DME1737_REG_TACH_PWM 0x81
171
172 /* ---------------------------------------------------------------------
173 * Misc defines
174 * --------------------------------------------------------------------- */
175
176 /* Chip identification */
177 #define DME1737_COMPANY_SMSC 0x5c
178 #define DME1737_VERSTEP 0x88
179 #define DME1737_VERSTEP_MASK 0xf8
180 #define SCH311X_DEVICE 0x8c
181 #define SCH5027_VERSTEP 0x69
182 #define SCH5127_DEVICE 0x8e
183
184 /* Device ID values (global configuration register index 0x20) */
185 #define DME1737_ID_1 0x77
186 #define DME1737_ID_2 0x78
187 #define SCH3112_ID 0x7c
188 #define SCH3114_ID 0x7d
189 #define SCH3116_ID 0x7f
190 #define SCH5027_ID 0x89
191 #define SCH5127_ID 0x86
192
193 /* Length of ISA address segment */
194 #define DME1737_EXTENT 2
195
196 /* chip-dependent features */
197 #define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */
198 #define HAS_VID (1 << 1) /* bit 1 */
199 #define HAS_ZONE3 (1 << 2) /* bit 2 */
200 #define HAS_ZONE_HYST (1 << 3) /* bit 3 */
201 #define HAS_PWM_MIN (1 << 4) /* bit 4 */
202 #define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */
203 #define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */
204 #define HAS_IN7 (1 << 17) /* bit 17 */
205
206 /* ---------------------------------------------------------------------
207 * Data structures and manipulation thereof
208 * --------------------------------------------------------------------- */
209
210 struct dme1737_data {
211 struct i2c_client *client; /* for I2C devices only */
212 struct device *hwmon_dev;
213 const char *name;
214 unsigned int addr; /* for ISA devices only */
215
216 struct mutex update_lock;
217 int valid; /* !=0 if following fields are valid */
218 unsigned long last_update; /* in jiffies */
219 unsigned long last_vbat; /* in jiffies */
220 enum chips type;
221 const int *in_nominal; /* pointer to IN_NOMINAL array */
222
223 u8 vid;
224 u8 pwm_rr_en;
225 u32 has_features;
226
227 /* Register values */
228 u16 in[8];
229 u8 in_min[8];
230 u8 in_max[8];
231 s16 temp[3];
232 s8 temp_min[3];
233 s8 temp_max[3];
234 s8 temp_offset[3];
235 u8 config;
236 u8 config2;
237 u8 vrm;
238 u16 fan[6];
239 u16 fan_min[6];
240 u8 fan_max[2];
241 u8 fan_opt[6];
242 u8 pwm[6];
243 u8 pwm_min[3];
244 u8 pwm_config[3];
245 u8 pwm_acz[3];
246 u8 pwm_freq[6];
247 u8 pwm_rr[2];
248 u8 zone_low[3];
249 u8 zone_abs[3];
250 u8 zone_hyst[2];
251 u32 alarms;
252 };
253
254 /* Nominal voltage values */
255 static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
256 3300};
257 static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
258 3300};
259 static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
260 3300};
261 static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
262 3300, 1500};
263 #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
264 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
265 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
266 IN_NOMINAL_DME1737)
267
268 /*
269 * Voltage input
270 * Voltage inputs have 16 bits resolution, limit values have 8 bits
271 * resolution.
272 */
273 static inline int IN_FROM_REG(int reg, int nominal, int res)
274 {
275 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
276 }
277
278 static inline int IN_TO_REG(int val, int nominal)
279 {
280 return clamp_val((val * 192 + nominal / 2) / nominal, 0, 255);
281 }
282
283 /*
284 * Temperature input
285 * The register values represent temperatures in 2's complement notation from
286 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
287 * values have 8 bits resolution.
288 */
289 static inline int TEMP_FROM_REG(int reg, int res)
290 {
291 return (reg * 1000) >> (res - 8);
292 }
293
294 static inline int TEMP_TO_REG(int val)
295 {
296 return clamp_val((val < 0 ? val - 500 : val + 500) / 1000, -128, 127);
297 }
298
299 /* Temperature range */
300 static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
301 10000, 13333, 16000, 20000, 26666, 32000,
302 40000, 53333, 80000};
303
304 static inline int TEMP_RANGE_FROM_REG(int reg)
305 {
306 return TEMP_RANGE[(reg >> 4) & 0x0f];
307 }
308
309 static int TEMP_RANGE_TO_REG(int val, int reg)
310 {
311 int i;
312
313 for (i = 15; i > 0; i--) {
314 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
315 break;
316 }
317
318 return (reg & 0x0f) | (i << 4);
319 }
320
321 /*
322 * Temperature hysteresis
323 * Register layout:
324 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
325 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
326 */
327 static inline int TEMP_HYST_FROM_REG(int reg, int ix)
328 {
329 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
330 }
331
332 static inline int TEMP_HYST_TO_REG(int val, int ix, int reg)
333 {
334 int hyst = clamp_val((val + 500) / 1000, 0, 15);
335
336 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
337 }
338
339 /* Fan input RPM */
340 static inline int FAN_FROM_REG(int reg, int tpc)
341 {
342 if (tpc)
343 return tpc * reg;
344 else
345 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
346 }
347
348 static inline int FAN_TO_REG(int val, int tpc)
349 {
350 if (tpc) {
351 return clamp_val(val / tpc, 0, 0xffff);
352 } else {
353 return (val <= 0) ? 0xffff :
354 clamp_val(90000 * 60 / val, 0, 0xfffe);
355 }
356 }
357
358 /*
359 * Fan TPC (tach pulse count)
360 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
361 * is configured in legacy (non-tpc) mode
362 */
363 static inline int FAN_TPC_FROM_REG(int reg)
364 {
365 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
366 }
367
368 /*
369 * Fan type
370 * The type of a fan is expressed in number of pulses-per-revolution that it
371 * emits
372 */
373 static inline int FAN_TYPE_FROM_REG(int reg)
374 {
375 int edge = (reg >> 1) & 0x03;
376
377 return (edge > 0) ? 1 << (edge - 1) : 0;
378 }
379
380 static inline int FAN_TYPE_TO_REG(int val, int reg)
381 {
382 int edge = (val == 4) ? 3 : val;
383
384 return (reg & 0xf9) | (edge << 1);
385 }
386
387 /* Fan max RPM */
388 static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
389 0x11, 0x0f, 0x0e};
390
391 static int FAN_MAX_FROM_REG(int reg)
392 {
393 int i;
394
395 for (i = 10; i > 0; i--) {
396 if (reg == FAN_MAX[i])
397 break;
398 }
399
400 return 1000 + i * 500;
401 }
402
403 static int FAN_MAX_TO_REG(int val)
404 {
405 int i;
406
407 for (i = 10; i > 0; i--) {
408 if (val > (1000 + (i - 1) * 500))
409 break;
410 }
411
412 return FAN_MAX[i];
413 }
414
415 /*
416 * PWM enable
417 * Register to enable mapping:
418 * 000: 2 fan on zone 1 auto
419 * 001: 2 fan on zone 2 auto
420 * 010: 2 fan on zone 3 auto
421 * 011: 0 fan full on
422 * 100: -1 fan disabled
423 * 101: 2 fan on hottest of zones 2,3 auto
424 * 110: 2 fan on hottest of zones 1,2,3 auto
425 * 111: 1 fan in manual mode
426 */
427 static inline int PWM_EN_FROM_REG(int reg)
428 {
429 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
430
431 return en[(reg >> 5) & 0x07];
432 }
433
434 static inline int PWM_EN_TO_REG(int val, int reg)
435 {
436 int en = (val == 1) ? 7 : 3;
437
438 return (reg & 0x1f) | ((en & 0x07) << 5);
439 }
440
441 /*
442 * PWM auto channels zone
443 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
444 * corresponding to zone x+1):
445 * 000: 001 fan on zone 1 auto
446 * 001: 010 fan on zone 2 auto
447 * 010: 100 fan on zone 3 auto
448 * 011: 000 fan full on
449 * 100: 000 fan disabled
450 * 101: 110 fan on hottest of zones 2,3 auto
451 * 110: 111 fan on hottest of zones 1,2,3 auto
452 * 111: 000 fan in manual mode
453 */
454 static inline int PWM_ACZ_FROM_REG(int reg)
455 {
456 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
457
458 return acz[(reg >> 5) & 0x07];
459 }
460
461 static inline int PWM_ACZ_TO_REG(int val, int reg)
462 {
463 int acz = (val == 4) ? 2 : val - 1;
464
465 return (reg & 0x1f) | ((acz & 0x07) << 5);
466 }
467
468 /* PWM frequency */
469 static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
470 15000, 20000, 30000, 25000, 0, 0, 0, 0};
471
472 static inline int PWM_FREQ_FROM_REG(int reg)
473 {
474 return PWM_FREQ[reg & 0x0f];
475 }
476
477 static int PWM_FREQ_TO_REG(int val, int reg)
478 {
479 int i;
480
481 /* the first two cases are special - stupid chip design! */
482 if (val > 27500) {
483 i = 10;
484 } else if (val > 22500) {
485 i = 11;
486 } else {
487 for (i = 9; i > 0; i--) {
488 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
489 break;
490 }
491 }
492
493 return (reg & 0xf0) | i;
494 }
495
496 /*
497 * PWM ramp rate
498 * Register layout:
499 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
500 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
501 */
502 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
503
504 static inline int PWM_RR_FROM_REG(int reg, int ix)
505 {
506 int rr = (ix == 1) ? reg >> 4 : reg;
507
508 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
509 }
510
511 static int PWM_RR_TO_REG(int val, int ix, int reg)
512 {
513 int i;
514
515 for (i = 0; i < 7; i++) {
516 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
517 break;
518 }
519
520 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
521 }
522
523 /* PWM ramp rate enable */
524 static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
525 {
526 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
527 }
528
529 static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg)
530 {
531 int en = (ix == 1) ? 0x80 : 0x08;
532
533 return val ? reg | en : reg & ~en;
534 }
535
536 /*
537 * PWM min/off
538 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
539 * the register layout).
540 */
541 static inline int PWM_OFF_FROM_REG(int reg, int ix)
542 {
543 return (reg >> (ix + 5)) & 0x01;
544 }
545
546 static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
547 {
548 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
549 }
550
551 /* ---------------------------------------------------------------------
552 * Device I/O access
553 *
554 * ISA access is performed through an index/data register pair and needs to
555 * be protected by a mutex during runtime (not required for initialization).
556 * We use data->update_lock for this and need to ensure that we acquire it
557 * before calling dme1737_read or dme1737_write.
558 * --------------------------------------------------------------------- */
559
560 static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
561 {
562 struct i2c_client *client = data->client;
563 s32 val;
564
565 if (client) { /* I2C device */
566 val = i2c_smbus_read_byte_data(client, reg);
567
568 if (val < 0) {
569 dev_warn(&client->dev, "Read from register "
570 "0x%02x failed! Please report to the driver "
571 "maintainer.\n", reg);
572 }
573 } else { /* ISA device */
574 outb(reg, data->addr);
575 val = inb(data->addr + 1);
576 }
577
578 return val;
579 }
580
581 static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
582 {
583 struct i2c_client *client = data->client;
584 s32 res = 0;
585
586 if (client) { /* I2C device */
587 res = i2c_smbus_write_byte_data(client, reg, val);
588
589 if (res < 0) {
590 dev_warn(&client->dev, "Write to register "
591 "0x%02x failed! Please report to the driver "
592 "maintainer.\n", reg);
593 }
594 } else { /* ISA device */
595 outb(reg, data->addr);
596 outb(val, data->addr + 1);
597 }
598
599 return res;
600 }
601
602 static struct dme1737_data *dme1737_update_device(struct device *dev)
603 {
604 struct dme1737_data *data = dev_get_drvdata(dev);
605 int ix;
606 u8 lsb[6];
607
608 mutex_lock(&data->update_lock);
609
610 /* Enable a Vbat monitoring cycle every 10 mins */
611 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
612 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
613 DME1737_REG_CONFIG) | 0x10);
614 data->last_vbat = jiffies;
615 }
616
617 /* Sample register contents every 1 sec */
618 if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
619 if (data->has_features & HAS_VID) {
620 data->vid = dme1737_read(data, DME1737_REG_VID) &
621 0x3f;
622 }
623
624 /* In (voltage) registers */
625 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
626 /*
627 * Voltage inputs are stored as 16 bit values even
628 * though they have only 12 bits resolution. This is
629 * to make it consistent with the temp inputs.
630 */
631 if (ix == 7 && !(data->has_features & HAS_IN7))
632 continue;
633 data->in[ix] = dme1737_read(data,
634 DME1737_REG_IN(ix)) << 8;
635 data->in_min[ix] = dme1737_read(data,
636 DME1737_REG_IN_MIN(ix));
637 data->in_max[ix] = dme1737_read(data,
638 DME1737_REG_IN_MAX(ix));
639 }
640
641 /* Temp registers */
642 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
643 /*
644 * Temp inputs are stored as 16 bit values even
645 * though they have only 12 bits resolution. This is
646 * to take advantage of implicit conversions between
647 * register values (2's complement) and temp values
648 * (signed decimal).
649 */
650 data->temp[ix] = dme1737_read(data,
651 DME1737_REG_TEMP(ix)) << 8;
652 data->temp_min[ix] = dme1737_read(data,
653 DME1737_REG_TEMP_MIN(ix));
654 data->temp_max[ix] = dme1737_read(data,
655 DME1737_REG_TEMP_MAX(ix));
656 if (data->has_features & HAS_TEMP_OFFSET) {
657 data->temp_offset[ix] = dme1737_read(data,
658 DME1737_REG_TEMP_OFFSET(ix));
659 }
660 }
661
662 /*
663 * In and temp LSB registers
664 * The LSBs are latched when the MSBs are read, so the order in
665 * which the registers are read (MSB first, then LSB) is
666 * important!
667 */
668 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
669 if (ix == 5 && !(data->has_features & HAS_IN7))
670 continue;
671 lsb[ix] = dme1737_read(data,
672 DME1737_REG_IN_TEMP_LSB(ix));
673 }
674 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
675 if (ix == 7 && !(data->has_features & HAS_IN7))
676 continue;
677 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
678 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
679 }
680 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
681 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
682 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
683 }
684
685 /* Fan registers */
686 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
687 /*
688 * Skip reading registers if optional fans are not
689 * present
690 */
691 if (!(data->has_features & HAS_FAN(ix)))
692 continue;
693 data->fan[ix] = dme1737_read(data,
694 DME1737_REG_FAN(ix));
695 data->fan[ix] |= dme1737_read(data,
696 DME1737_REG_FAN(ix) + 1) << 8;
697 data->fan_min[ix] = dme1737_read(data,
698 DME1737_REG_FAN_MIN(ix));
699 data->fan_min[ix] |= dme1737_read(data,
700 DME1737_REG_FAN_MIN(ix) + 1) << 8;
701 data->fan_opt[ix] = dme1737_read(data,
702 DME1737_REG_FAN_OPT(ix));
703 /* fan_max exists only for fan[5-6] */
704 if (ix > 3) {
705 data->fan_max[ix - 4] = dme1737_read(data,
706 DME1737_REG_FAN_MAX(ix));
707 }
708 }
709
710 /* PWM registers */
711 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
712 /*
713 * Skip reading registers if optional PWMs are not
714 * present
715 */
716 if (!(data->has_features & HAS_PWM(ix)))
717 continue;
718 data->pwm[ix] = dme1737_read(data,
719 DME1737_REG_PWM(ix));
720 data->pwm_freq[ix] = dme1737_read(data,
721 DME1737_REG_PWM_FREQ(ix));
722 /* pwm_config and pwm_min exist only for pwm[1-3] */
723 if (ix < 3) {
724 data->pwm_config[ix] = dme1737_read(data,
725 DME1737_REG_PWM_CONFIG(ix));
726 data->pwm_min[ix] = dme1737_read(data,
727 DME1737_REG_PWM_MIN(ix));
728 }
729 }
730 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
731 data->pwm_rr[ix] = dme1737_read(data,
732 DME1737_REG_PWM_RR(ix));
733 }
734
735 /* Thermal zone registers */
736 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
737 /* Skip reading registers if zone3 is not present */
738 if ((ix == 2) && !(data->has_features & HAS_ZONE3))
739 continue;
740 /* sch5127 zone2 registers are special */
741 if ((ix == 1) && (data->type == sch5127)) {
742 data->zone_low[1] = dme1737_read(data,
743 DME1737_REG_ZONE_LOW(2));
744 data->zone_abs[1] = dme1737_read(data,
745 DME1737_REG_ZONE_ABS(2));
746 } else {
747 data->zone_low[ix] = dme1737_read(data,
748 DME1737_REG_ZONE_LOW(ix));
749 data->zone_abs[ix] = dme1737_read(data,
750 DME1737_REG_ZONE_ABS(ix));
751 }
752 }
753 if (data->has_features & HAS_ZONE_HYST) {
754 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
755 data->zone_hyst[ix] = dme1737_read(data,
756 DME1737_REG_ZONE_HYST(ix));
757 }
758 }
759
760 /* Alarm registers */
761 data->alarms = dme1737_read(data,
762 DME1737_REG_ALARM1);
763 /*
764 * Bit 7 tells us if the other alarm registers are non-zero and
765 * therefore also need to be read
766 */
767 if (data->alarms & 0x80) {
768 data->alarms |= dme1737_read(data,
769 DME1737_REG_ALARM2) << 8;
770 data->alarms |= dme1737_read(data,
771 DME1737_REG_ALARM3) << 16;
772 }
773
774 /*
775 * The ISA chips require explicit clearing of alarm bits.
776 * Don't worry, an alarm will come back if the condition
777 * that causes it still exists
778 */
779 if (!data->client) {
780 if (data->alarms & 0xff0000)
781 dme1737_write(data, DME1737_REG_ALARM3, 0xff);
782 if (data->alarms & 0xff00)
783 dme1737_write(data, DME1737_REG_ALARM2, 0xff);
784 if (data->alarms & 0xff)
785 dme1737_write(data, DME1737_REG_ALARM1, 0xff);
786 }
787
788 data->last_update = jiffies;
789 data->valid = 1;
790 }
791
792 mutex_unlock(&data->update_lock);
793
794 return data;
795 }
796
797 /* ---------------------------------------------------------------------
798 * Voltage sysfs attributes
799 * ix = [0-7]
800 * --------------------------------------------------------------------- */
801
802 #define SYS_IN_INPUT 0
803 #define SYS_IN_MIN 1
804 #define SYS_IN_MAX 2
805 #define SYS_IN_ALARM 3
806
807 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
808 char *buf)
809 {
810 struct dme1737_data *data = dme1737_update_device(dev);
811 struct sensor_device_attribute_2
812 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
813 int ix = sensor_attr_2->index;
814 int fn = sensor_attr_2->nr;
815 int res;
816
817 switch (fn) {
818 case SYS_IN_INPUT:
819 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
820 break;
821 case SYS_IN_MIN:
822 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
823 break;
824 case SYS_IN_MAX:
825 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
826 break;
827 case SYS_IN_ALARM:
828 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
829 break;
830 default:
831 res = 0;
832 dev_dbg(dev, "Unknown function %d.\n", fn);
833 }
834
835 return sprintf(buf, "%d\n", res);
836 }
837
838 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
839 const char *buf, size_t count)
840 {
841 struct dme1737_data *data = dev_get_drvdata(dev);
842 struct sensor_device_attribute_2
843 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
844 int ix = sensor_attr_2->index;
845 int fn = sensor_attr_2->nr;
846 long val;
847 int err;
848
849 err = kstrtol(buf, 10, &val);
850 if (err)
851 return err;
852
853 mutex_lock(&data->update_lock);
854 switch (fn) {
855 case SYS_IN_MIN:
856 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
857 dme1737_write(data, DME1737_REG_IN_MIN(ix),
858 data->in_min[ix]);
859 break;
860 case SYS_IN_MAX:
861 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
862 dme1737_write(data, DME1737_REG_IN_MAX(ix),
863 data->in_max[ix]);
864 break;
865 default:
866 dev_dbg(dev, "Unknown function %d.\n", fn);
867 }
868 mutex_unlock(&data->update_lock);
869
870 return count;
871 }
872
873 /* ---------------------------------------------------------------------
874 * Temperature sysfs attributes
875 * ix = [0-2]
876 * --------------------------------------------------------------------- */
877
878 #define SYS_TEMP_INPUT 0
879 #define SYS_TEMP_MIN 1
880 #define SYS_TEMP_MAX 2
881 #define SYS_TEMP_OFFSET 3
882 #define SYS_TEMP_ALARM 4
883 #define SYS_TEMP_FAULT 5
884
885 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
886 char *buf)
887 {
888 struct dme1737_data *data = dme1737_update_device(dev);
889 struct sensor_device_attribute_2
890 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
891 int ix = sensor_attr_2->index;
892 int fn = sensor_attr_2->nr;
893 int res;
894
895 switch (fn) {
896 case SYS_TEMP_INPUT:
897 res = TEMP_FROM_REG(data->temp[ix], 16);
898 break;
899 case SYS_TEMP_MIN:
900 res = TEMP_FROM_REG(data->temp_min[ix], 8);
901 break;
902 case SYS_TEMP_MAX:
903 res = TEMP_FROM_REG(data->temp_max[ix], 8);
904 break;
905 case SYS_TEMP_OFFSET:
906 res = TEMP_FROM_REG(data->temp_offset[ix], 8);
907 break;
908 case SYS_TEMP_ALARM:
909 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
910 break;
911 case SYS_TEMP_FAULT:
912 res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
913 break;
914 default:
915 res = 0;
916 dev_dbg(dev, "Unknown function %d.\n", fn);
917 }
918
919 return sprintf(buf, "%d\n", res);
920 }
921
922 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
923 const char *buf, size_t count)
924 {
925 struct dme1737_data *data = dev_get_drvdata(dev);
926 struct sensor_device_attribute_2
927 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
928 int ix = sensor_attr_2->index;
929 int fn = sensor_attr_2->nr;
930 long val;
931 int err;
932
933 err = kstrtol(buf, 10, &val);
934 if (err)
935 return err;
936
937 mutex_lock(&data->update_lock);
938 switch (fn) {
939 case SYS_TEMP_MIN:
940 data->temp_min[ix] = TEMP_TO_REG(val);
941 dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
942 data->temp_min[ix]);
943 break;
944 case SYS_TEMP_MAX:
945 data->temp_max[ix] = TEMP_TO_REG(val);
946 dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
947 data->temp_max[ix]);
948 break;
949 case SYS_TEMP_OFFSET:
950 data->temp_offset[ix] = TEMP_TO_REG(val);
951 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
952 data->temp_offset[ix]);
953 break;
954 default:
955 dev_dbg(dev, "Unknown function %d.\n", fn);
956 }
957 mutex_unlock(&data->update_lock);
958
959 return count;
960 }
961
962 /* ---------------------------------------------------------------------
963 * Zone sysfs attributes
964 * ix = [0-2]
965 * --------------------------------------------------------------------- */
966
967 #define SYS_ZONE_AUTO_CHANNELS_TEMP 0
968 #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
969 #define SYS_ZONE_AUTO_POINT1_TEMP 2
970 #define SYS_ZONE_AUTO_POINT2_TEMP 3
971 #define SYS_ZONE_AUTO_POINT3_TEMP 4
972
973 static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
974 char *buf)
975 {
976 struct dme1737_data *data = dme1737_update_device(dev);
977 struct sensor_device_attribute_2
978 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
979 int ix = sensor_attr_2->index;
980 int fn = sensor_attr_2->nr;
981 int res;
982
983 switch (fn) {
984 case SYS_ZONE_AUTO_CHANNELS_TEMP:
985 /* check config2 for non-standard temp-to-zone mapping */
986 if ((ix == 1) && (data->config2 & 0x02))
987 res = 4;
988 else
989 res = 1 << ix;
990 break;
991 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
992 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
993 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
994 break;
995 case SYS_ZONE_AUTO_POINT1_TEMP:
996 res = TEMP_FROM_REG(data->zone_low[ix], 8);
997 break;
998 case SYS_ZONE_AUTO_POINT2_TEMP:
999 /* pwm_freq holds the temp range bits in the upper nibble */
1000 res = TEMP_FROM_REG(data->zone_low[ix], 8) +
1001 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
1002 break;
1003 case SYS_ZONE_AUTO_POINT3_TEMP:
1004 res = TEMP_FROM_REG(data->zone_abs[ix], 8);
1005 break;
1006 default:
1007 res = 0;
1008 dev_dbg(dev, "Unknown function %d.\n", fn);
1009 }
1010
1011 return sprintf(buf, "%d\n", res);
1012 }
1013
1014 static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
1015 const char *buf, size_t count)
1016 {
1017 struct dme1737_data *data = dev_get_drvdata(dev);
1018 struct sensor_device_attribute_2
1019 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1020 int ix = sensor_attr_2->index;
1021 int fn = sensor_attr_2->nr;
1022 long val;
1023 int err;
1024
1025 err = kstrtol(buf, 10, &val);
1026 if (err)
1027 return err;
1028
1029 mutex_lock(&data->update_lock);
1030 switch (fn) {
1031 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
1032 /* Refresh the cache */
1033 data->zone_low[ix] = dme1737_read(data,
1034 DME1737_REG_ZONE_LOW(ix));
1035 /* Modify the temp hyst value */
1036 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(
1037 TEMP_FROM_REG(data->zone_low[ix], 8) -
1038 val, ix, dme1737_read(data,
1039 DME1737_REG_ZONE_HYST(ix == 2)));
1040 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
1041 data->zone_hyst[ix == 2]);
1042 break;
1043 case SYS_ZONE_AUTO_POINT1_TEMP:
1044 data->zone_low[ix] = TEMP_TO_REG(val);
1045 dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
1046 data->zone_low[ix]);
1047 break;
1048 case SYS_ZONE_AUTO_POINT2_TEMP:
1049 /* Refresh the cache */
1050 data->zone_low[ix] = dme1737_read(data,
1051 DME1737_REG_ZONE_LOW(ix));
1052 /*
1053 * Modify the temp range value (which is stored in the upper
1054 * nibble of the pwm_freq register)
1055 */
1056 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1057 TEMP_FROM_REG(data->zone_low[ix], 8),
1058 dme1737_read(data,
1059 DME1737_REG_PWM_FREQ(ix)));
1060 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
1061 data->pwm_freq[ix]);
1062 break;
1063 case SYS_ZONE_AUTO_POINT3_TEMP:
1064 data->zone_abs[ix] = TEMP_TO_REG(val);
1065 dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
1066 data->zone_abs[ix]);
1067 break;
1068 default:
1069 dev_dbg(dev, "Unknown function %d.\n", fn);
1070 }
1071 mutex_unlock(&data->update_lock);
1072
1073 return count;
1074 }
1075
1076 /* ---------------------------------------------------------------------
1077 * Fan sysfs attributes
1078 * ix = [0-5]
1079 * --------------------------------------------------------------------- */
1080
1081 #define SYS_FAN_INPUT 0
1082 #define SYS_FAN_MIN 1
1083 #define SYS_FAN_MAX 2
1084 #define SYS_FAN_ALARM 3
1085 #define SYS_FAN_TYPE 4
1086
1087 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1088 char *buf)
1089 {
1090 struct dme1737_data *data = dme1737_update_device(dev);
1091 struct sensor_device_attribute_2
1092 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1093 int ix = sensor_attr_2->index;
1094 int fn = sensor_attr_2->nr;
1095 int res;
1096
1097 switch (fn) {
1098 case SYS_FAN_INPUT:
1099 res = FAN_FROM_REG(data->fan[ix],
1100 ix < 4 ? 0 :
1101 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1102 break;
1103 case SYS_FAN_MIN:
1104 res = FAN_FROM_REG(data->fan_min[ix],
1105 ix < 4 ? 0 :
1106 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1107 break;
1108 case SYS_FAN_MAX:
1109 /* only valid for fan[5-6] */
1110 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
1111 break;
1112 case SYS_FAN_ALARM:
1113 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
1114 break;
1115 case SYS_FAN_TYPE:
1116 /* only valid for fan[1-4] */
1117 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
1118 break;
1119 default:
1120 res = 0;
1121 dev_dbg(dev, "Unknown function %d.\n", fn);
1122 }
1123
1124 return sprintf(buf, "%d\n", res);
1125 }
1126
1127 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1128 const char *buf, size_t count)
1129 {
1130 struct dme1737_data *data = dev_get_drvdata(dev);
1131 struct sensor_device_attribute_2
1132 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1133 int ix = sensor_attr_2->index;
1134 int fn = sensor_attr_2->nr;
1135 long val;
1136 int err;
1137
1138 err = kstrtol(buf, 10, &val);
1139 if (err)
1140 return err;
1141
1142 mutex_lock(&data->update_lock);
1143 switch (fn) {
1144 case SYS_FAN_MIN:
1145 if (ix < 4) {
1146 data->fan_min[ix] = FAN_TO_REG(val, 0);
1147 } else {
1148 /* Refresh the cache */
1149 data->fan_opt[ix] = dme1737_read(data,
1150 DME1737_REG_FAN_OPT(ix));
1151 /* Modify the fan min value */
1152 data->fan_min[ix] = FAN_TO_REG(val,
1153 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1154 }
1155 dme1737_write(data, DME1737_REG_FAN_MIN(ix),
1156 data->fan_min[ix] & 0xff);
1157 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
1158 data->fan_min[ix] >> 8);
1159 break;
1160 case SYS_FAN_MAX:
1161 /* Only valid for fan[5-6] */
1162 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
1163 dme1737_write(data, DME1737_REG_FAN_MAX(ix),
1164 data->fan_max[ix - 4]);
1165 break;
1166 case SYS_FAN_TYPE:
1167 /* Only valid for fan[1-4] */
1168 if (!(val == 1 || val == 2 || val == 4)) {
1169 count = -EINVAL;
1170 dev_warn(dev, "Fan type value %ld not "
1171 "supported. Choose one of 1, 2, or 4.\n",
1172 val);
1173 goto exit;
1174 }
1175 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
1176 DME1737_REG_FAN_OPT(ix)));
1177 dme1737_write(data, DME1737_REG_FAN_OPT(ix),
1178 data->fan_opt[ix]);
1179 break;
1180 default:
1181 dev_dbg(dev, "Unknown function %d.\n", fn);
1182 }
1183 exit:
1184 mutex_unlock(&data->update_lock);
1185
1186 return count;
1187 }
1188
1189 /* ---------------------------------------------------------------------
1190 * PWM sysfs attributes
1191 * ix = [0-4]
1192 * --------------------------------------------------------------------- */
1193
1194 #define SYS_PWM 0
1195 #define SYS_PWM_FREQ 1
1196 #define SYS_PWM_ENABLE 2
1197 #define SYS_PWM_RAMP_RATE 3
1198 #define SYS_PWM_AUTO_CHANNELS_ZONE 4
1199 #define SYS_PWM_AUTO_PWM_MIN 5
1200 #define SYS_PWM_AUTO_POINT1_PWM 6
1201 #define SYS_PWM_AUTO_POINT2_PWM 7
1202
1203 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1204 char *buf)
1205 {
1206 struct dme1737_data *data = dme1737_update_device(dev);
1207 struct sensor_device_attribute_2
1208 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1209 int ix = sensor_attr_2->index;
1210 int fn = sensor_attr_2->nr;
1211 int res;
1212
1213 switch (fn) {
1214 case SYS_PWM:
1215 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0)
1216 res = 255;
1217 else
1218 res = data->pwm[ix];
1219 break;
1220 case SYS_PWM_FREQ:
1221 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1222 break;
1223 case SYS_PWM_ENABLE:
1224 if (ix >= 3)
1225 res = 1; /* pwm[5-6] hard-wired to manual mode */
1226 else
1227 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
1228 break;
1229 case SYS_PWM_RAMP_RATE:
1230 /* Only valid for pwm[1-3] */
1231 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
1232 break;
1233 case SYS_PWM_AUTO_CHANNELS_ZONE:
1234 /* Only valid for pwm[1-3] */
1235 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2)
1236 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
1237 else
1238 res = data->pwm_acz[ix];
1239 break;
1240 case SYS_PWM_AUTO_PWM_MIN:
1241 /* Only valid for pwm[1-3] */
1242 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix))
1243 res = data->pwm_min[ix];
1244 else
1245 res = 0;
1246 break;
1247 case SYS_PWM_AUTO_POINT1_PWM:
1248 /* Only valid for pwm[1-3] */
1249 res = data->pwm_min[ix];
1250 break;
1251 case SYS_PWM_AUTO_POINT2_PWM:
1252 /* Only valid for pwm[1-3] */
1253 res = 255; /* hard-wired */
1254 break;
1255 default:
1256 res = 0;
1257 dev_dbg(dev, "Unknown function %d.\n", fn);
1258 }
1259
1260 return sprintf(buf, "%d\n", res);
1261 }
1262
1263 static struct attribute *dme1737_pwm_chmod_attr[];
1264 static void dme1737_chmod_file(struct device*, struct attribute*, umode_t);
1265
1266 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1267 const char *buf, size_t count)
1268 {
1269 struct dme1737_data *data = dev_get_drvdata(dev);
1270 struct sensor_device_attribute_2
1271 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1272 int ix = sensor_attr_2->index;
1273 int fn = sensor_attr_2->nr;
1274 long val;
1275 int err;
1276
1277 err = kstrtol(buf, 10, &val);
1278 if (err)
1279 return err;
1280
1281 mutex_lock(&data->update_lock);
1282 switch (fn) {
1283 case SYS_PWM:
1284 data->pwm[ix] = clamp_val(val, 0, 255);
1285 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
1286 break;
1287 case SYS_PWM_FREQ:
1288 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
1289 DME1737_REG_PWM_FREQ(ix)));
1290 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
1291 data->pwm_freq[ix]);
1292 break;
1293 case SYS_PWM_ENABLE:
1294 /* Only valid for pwm[1-3] */
1295 if (val < 0 || val > 2) {
1296 count = -EINVAL;
1297 dev_warn(dev, "PWM enable %ld not "
1298 "supported. Choose one of 0, 1, or 2.\n",
1299 val);
1300 goto exit;
1301 }
1302 /* Refresh the cache */
1303 data->pwm_config[ix] = dme1737_read(data,
1304 DME1737_REG_PWM_CONFIG(ix));
1305 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
1306 /* Bail out if no change */
1307 goto exit;
1308 }
1309 /* Do some housekeeping if we are currently in auto mode */
1310 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1311 /* Save the current zone channel assignment */
1312 data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
1313 data->pwm_config[ix]);
1314 /* Save the current ramp rate state and disable it */
1315 data->pwm_rr[ix > 0] = dme1737_read(data,
1316 DME1737_REG_PWM_RR(ix > 0));
1317 data->pwm_rr_en &= ~(1 << ix);
1318 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
1319 data->pwm_rr_en |= (1 << ix);
1320 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
1321 data->pwm_rr[ix > 0]);
1322 dme1737_write(data,
1323 DME1737_REG_PWM_RR(ix > 0),
1324 data->pwm_rr[ix > 0]);
1325 }
1326 }
1327 /* Set the new PWM mode */
1328 switch (val) {
1329 case 0:
1330 /* Change permissions of pwm[ix] to read-only */
1331 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1332 S_IRUGO);
1333 /* Turn fan fully on */
1334 data->pwm_config[ix] = PWM_EN_TO_REG(0,
1335 data->pwm_config[ix]);
1336 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1337 data->pwm_config[ix]);
1338 break;
1339 case 1:
1340 /* Turn on manual mode */
1341 data->pwm_config[ix] = PWM_EN_TO_REG(1,
1342 data->pwm_config[ix]);
1343 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1344 data->pwm_config[ix]);
1345 /* Change permissions of pwm[ix] to read-writeable */
1346 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1347 S_IRUGO | S_IWUSR);
1348 break;
1349 case 2:
1350 /* Change permissions of pwm[ix] to read-only */
1351 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1352 S_IRUGO);
1353 /*
1354 * Turn on auto mode using the saved zone channel
1355 * assignment
1356 */
1357 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1358 data->pwm_acz[ix],
1359 data->pwm_config[ix]);
1360 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1361 data->pwm_config[ix]);
1362 /* Enable PWM ramp rate if previously enabled */
1363 if (data->pwm_rr_en & (1 << ix)) {
1364 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
1365 dme1737_read(data,
1366 DME1737_REG_PWM_RR(ix > 0)));
1367 dme1737_write(data,
1368 DME1737_REG_PWM_RR(ix > 0),
1369 data->pwm_rr[ix > 0]);
1370 }
1371 break;
1372 }
1373 break;
1374 case SYS_PWM_RAMP_RATE:
1375 /* Only valid for pwm[1-3] */
1376 /* Refresh the cache */
1377 data->pwm_config[ix] = dme1737_read(data,
1378 DME1737_REG_PWM_CONFIG(ix));
1379 data->pwm_rr[ix > 0] = dme1737_read(data,
1380 DME1737_REG_PWM_RR(ix > 0));
1381 /* Set the ramp rate value */
1382 if (val > 0) {
1383 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1384 data->pwm_rr[ix > 0]);
1385 }
1386 /*
1387 * Enable/disable the feature only if the associated PWM
1388 * output is in automatic mode.
1389 */
1390 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1391 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1392 data->pwm_rr[ix > 0]);
1393 }
1394 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
1395 data->pwm_rr[ix > 0]);
1396 break;
1397 case SYS_PWM_AUTO_CHANNELS_ZONE:
1398 /* Only valid for pwm[1-3] */
1399 if (!(val == 1 || val == 2 || val == 4 ||
1400 val == 6 || val == 7)) {
1401 count = -EINVAL;
1402 dev_warn(dev, "PWM auto channels zone %ld "
1403 "not supported. Choose one of 1, 2, 4, 6, "
1404 "or 7.\n", val);
1405 goto exit;
1406 }
1407 /* Refresh the cache */
1408 data->pwm_config[ix] = dme1737_read(data,
1409 DME1737_REG_PWM_CONFIG(ix));
1410 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1411 /*
1412 * PWM is already in auto mode so update the temp
1413 * channel assignment
1414 */
1415 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1416 data->pwm_config[ix]);
1417 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1418 data->pwm_config[ix]);
1419 } else {
1420 /*
1421 * PWM is not in auto mode so we save the temp
1422 * channel assignment for later use
1423 */
1424 data->pwm_acz[ix] = val;
1425 }
1426 break;
1427 case SYS_PWM_AUTO_PWM_MIN:
1428 /* Only valid for pwm[1-3] */
1429 /* Refresh the cache */
1430 data->pwm_min[ix] = dme1737_read(data,
1431 DME1737_REG_PWM_MIN(ix));
1432 /*
1433 * There are only 2 values supported for the auto_pwm_min
1434 * value: 0 or auto_point1_pwm. So if the temperature drops
1435 * below the auto_point1_temp_hyst value, the fan either turns
1436 * off or runs at auto_point1_pwm duty-cycle.
1437 */
1438 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1439 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
1440 dme1737_read(data,
1441 DME1737_REG_PWM_RR(0)));
1442 } else {
1443 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
1444 dme1737_read(data,
1445 DME1737_REG_PWM_RR(0)));
1446 }
1447 dme1737_write(data, DME1737_REG_PWM_RR(0),
1448 data->pwm_rr[0]);
1449 break;
1450 case SYS_PWM_AUTO_POINT1_PWM:
1451 /* Only valid for pwm[1-3] */
1452 data->pwm_min[ix] = clamp_val(val, 0, 255);
1453 dme1737_write(data, DME1737_REG_PWM_MIN(ix),
1454 data->pwm_min[ix]);
1455 break;
1456 default:
1457 dev_dbg(dev, "Unknown function %d.\n", fn);
1458 }
1459 exit:
1460 mutex_unlock(&data->update_lock);
1461
1462 return count;
1463 }
1464
1465 /* ---------------------------------------------------------------------
1466 * Miscellaneous sysfs attributes
1467 * --------------------------------------------------------------------- */
1468
1469 static ssize_t show_vrm(struct device *dev, struct device_attribute *attr,
1470 char *buf)
1471 {
1472 struct i2c_client *client = to_i2c_client(dev);
1473 struct dme1737_data *data = i2c_get_clientdata(client);
1474
1475 return sprintf(buf, "%d\n", data->vrm);
1476 }
1477
1478 static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1479 const char *buf, size_t count)
1480 {
1481 struct dme1737_data *data = dev_get_drvdata(dev);
1482 long val;
1483 int err;
1484
1485 err = kstrtol(buf, 10, &val);
1486 if (err)
1487 return err;
1488
1489 data->vrm = val;
1490 return count;
1491 }
1492
1493 static ssize_t show_vid(struct device *dev, struct device_attribute *attr,
1494 char *buf)
1495 {
1496 struct dme1737_data *data = dme1737_update_device(dev);
1497
1498 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1499 }
1500
1501 static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1502 char *buf)
1503 {
1504 struct dme1737_data *data = dev_get_drvdata(dev);
1505
1506 return sprintf(buf, "%s\n", data->name);
1507 }
1508
1509 /* ---------------------------------------------------------------------
1510 * Sysfs device attribute defines and structs
1511 * --------------------------------------------------------------------- */
1512
1513 /* Voltages 0-7 */
1514
1515 #define SENSOR_DEVICE_ATTR_IN(ix) \
1516 static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
1517 show_in, NULL, SYS_IN_INPUT, ix); \
1518 static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
1519 show_in, set_in, SYS_IN_MIN, ix); \
1520 static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
1521 show_in, set_in, SYS_IN_MAX, ix); \
1522 static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
1523 show_in, NULL, SYS_IN_ALARM, ix)
1524
1525 SENSOR_DEVICE_ATTR_IN(0);
1526 SENSOR_DEVICE_ATTR_IN(1);
1527 SENSOR_DEVICE_ATTR_IN(2);
1528 SENSOR_DEVICE_ATTR_IN(3);
1529 SENSOR_DEVICE_ATTR_IN(4);
1530 SENSOR_DEVICE_ATTR_IN(5);
1531 SENSOR_DEVICE_ATTR_IN(6);
1532 SENSOR_DEVICE_ATTR_IN(7);
1533
1534 /* Temperatures 1-3 */
1535
1536 #define SENSOR_DEVICE_ATTR_TEMP(ix) \
1537 static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
1538 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
1539 static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
1540 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
1541 static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
1542 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
1543 static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
1544 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
1545 static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
1546 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
1547 static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
1548 show_temp, NULL, SYS_TEMP_FAULT, ix-1)
1549
1550 SENSOR_DEVICE_ATTR_TEMP(1);
1551 SENSOR_DEVICE_ATTR_TEMP(2);
1552 SENSOR_DEVICE_ATTR_TEMP(3);
1553
1554 /* Zones 1-3 */
1555
1556 #define SENSOR_DEVICE_ATTR_ZONE(ix) \
1557 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
1558 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
1559 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
1560 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
1561 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
1562 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
1563 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
1564 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
1565 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
1566 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
1567
1568 SENSOR_DEVICE_ATTR_ZONE(1);
1569 SENSOR_DEVICE_ATTR_ZONE(2);
1570 SENSOR_DEVICE_ATTR_ZONE(3);
1571
1572 /* Fans 1-4 */
1573
1574 #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
1575 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1576 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1577 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1578 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1579 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1580 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1581 static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
1582 show_fan, set_fan, SYS_FAN_TYPE, ix-1)
1583
1584 SENSOR_DEVICE_ATTR_FAN_1TO4(1);
1585 SENSOR_DEVICE_ATTR_FAN_1TO4(2);
1586 SENSOR_DEVICE_ATTR_FAN_1TO4(3);
1587 SENSOR_DEVICE_ATTR_FAN_1TO4(4);
1588
1589 /* Fans 5-6 */
1590
1591 #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
1592 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1593 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1594 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1595 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1596 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1597 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1598 static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
1599 show_fan, set_fan, SYS_FAN_MAX, ix-1)
1600
1601 SENSOR_DEVICE_ATTR_FAN_5TO6(5);
1602 SENSOR_DEVICE_ATTR_FAN_5TO6(6);
1603
1604 /* PWMs 1-3 */
1605
1606 #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
1607 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1608 show_pwm, set_pwm, SYS_PWM, ix-1); \
1609 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1610 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1611 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1612 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
1613 static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
1614 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
1615 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
1616 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
1617 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
1618 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
1619 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
1620 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
1621 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
1622 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
1623
1624 SENSOR_DEVICE_ATTR_PWM_1TO3(1);
1625 SENSOR_DEVICE_ATTR_PWM_1TO3(2);
1626 SENSOR_DEVICE_ATTR_PWM_1TO3(3);
1627
1628 /* PWMs 5-6 */
1629
1630 #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
1631 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1632 show_pwm, set_pwm, SYS_PWM, ix-1); \
1633 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1634 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1635 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1636 show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
1637
1638 SENSOR_DEVICE_ATTR_PWM_5TO6(5);
1639 SENSOR_DEVICE_ATTR_PWM_5TO6(6);
1640
1641 /* Misc */
1642
1643 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1644 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1645 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
1646
1647 /*
1648 * This struct holds all the attributes that are always present and need to be
1649 * created unconditionally. The attributes that need modification of their
1650 * permissions are created read-only and write permissions are added or removed
1651 * on the fly when required
1652 */
1653 static struct attribute *dme1737_attr[] = {
1654 /* Voltages */
1655 &sensor_dev_attr_in0_input.dev_attr.attr,
1656 &sensor_dev_attr_in0_min.dev_attr.attr,
1657 &sensor_dev_attr_in0_max.dev_attr.attr,
1658 &sensor_dev_attr_in0_alarm.dev_attr.attr,
1659 &sensor_dev_attr_in1_input.dev_attr.attr,
1660 &sensor_dev_attr_in1_min.dev_attr.attr,
1661 &sensor_dev_attr_in1_max.dev_attr.attr,
1662 &sensor_dev_attr_in1_alarm.dev_attr.attr,
1663 &sensor_dev_attr_in2_input.dev_attr.attr,
1664 &sensor_dev_attr_in2_min.dev_attr.attr,
1665 &sensor_dev_attr_in2_max.dev_attr.attr,
1666 &sensor_dev_attr_in2_alarm.dev_attr.attr,
1667 &sensor_dev_attr_in3_input.dev_attr.attr,
1668 &sensor_dev_attr_in3_min.dev_attr.attr,
1669 &sensor_dev_attr_in3_max.dev_attr.attr,
1670 &sensor_dev_attr_in3_alarm.dev_attr.attr,
1671 &sensor_dev_attr_in4_input.dev_attr.attr,
1672 &sensor_dev_attr_in4_min.dev_attr.attr,
1673 &sensor_dev_attr_in4_max.dev_attr.attr,
1674 &sensor_dev_attr_in4_alarm.dev_attr.attr,
1675 &sensor_dev_attr_in5_input.dev_attr.attr,
1676 &sensor_dev_attr_in5_min.dev_attr.attr,
1677 &sensor_dev_attr_in5_max.dev_attr.attr,
1678 &sensor_dev_attr_in5_alarm.dev_attr.attr,
1679 &sensor_dev_attr_in6_input.dev_attr.attr,
1680 &sensor_dev_attr_in6_min.dev_attr.attr,
1681 &sensor_dev_attr_in6_max.dev_attr.attr,
1682 &sensor_dev_attr_in6_alarm.dev_attr.attr,
1683 /* Temperatures */
1684 &sensor_dev_attr_temp1_input.dev_attr.attr,
1685 &sensor_dev_attr_temp1_min.dev_attr.attr,
1686 &sensor_dev_attr_temp1_max.dev_attr.attr,
1687 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
1688 &sensor_dev_attr_temp1_fault.dev_attr.attr,
1689 &sensor_dev_attr_temp2_input.dev_attr.attr,
1690 &sensor_dev_attr_temp2_min.dev_attr.attr,
1691 &sensor_dev_attr_temp2_max.dev_attr.attr,
1692 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
1693 &sensor_dev_attr_temp2_fault.dev_attr.attr,
1694 &sensor_dev_attr_temp3_input.dev_attr.attr,
1695 &sensor_dev_attr_temp3_min.dev_attr.attr,
1696 &sensor_dev_attr_temp3_max.dev_attr.attr,
1697 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1698 &sensor_dev_attr_temp3_fault.dev_attr.attr,
1699 /* Zones */
1700 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1701 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1702 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1703 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
1704 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1705 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1706 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1707 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
1708 NULL
1709 };
1710
1711 static const struct attribute_group dme1737_group = {
1712 .attrs = dme1737_attr,
1713 };
1714
1715 /*
1716 * The following struct holds temp offset attributes, which are not available
1717 * in all chips. The following chips support them:
1718 * DME1737, SCH311x
1719 */
1720 static struct attribute *dme1737_temp_offset_attr[] = {
1721 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1722 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1723 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1724 NULL
1725 };
1726
1727 static const struct attribute_group dme1737_temp_offset_group = {
1728 .attrs = dme1737_temp_offset_attr,
1729 };
1730
1731 /*
1732 * The following struct holds VID related attributes, which are not available
1733 * in all chips. The following chips support them:
1734 * DME1737
1735 */
1736 static struct attribute *dme1737_vid_attr[] = {
1737 &dev_attr_vrm.attr,
1738 &dev_attr_cpu0_vid.attr,
1739 NULL
1740 };
1741
1742 static const struct attribute_group dme1737_vid_group = {
1743 .attrs = dme1737_vid_attr,
1744 };
1745
1746 /*
1747 * The following struct holds temp zone 3 related attributes, which are not
1748 * available in all chips. The following chips support them:
1749 * DME1737, SCH311x, SCH5027
1750 */
1751 static struct attribute *dme1737_zone3_attr[] = {
1752 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1753 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1754 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1755 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
1756 NULL
1757 };
1758
1759 static const struct attribute_group dme1737_zone3_group = {
1760 .attrs = dme1737_zone3_attr,
1761 };
1762
1763
1764 /*
1765 * The following struct holds temp zone hysteresis related attributes, which
1766 * are not available in all chips. The following chips support them:
1767 * DME1737, SCH311x
1768 */
1769 static struct attribute *dme1737_zone_hyst_attr[] = {
1770 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1771 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1772 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
1773 NULL
1774 };
1775
1776 static const struct attribute_group dme1737_zone_hyst_group = {
1777 .attrs = dme1737_zone_hyst_attr,
1778 };
1779
1780 /*
1781 * The following struct holds voltage in7 related attributes, which
1782 * are not available in all chips. The following chips support them:
1783 * SCH5127
1784 */
1785 static struct attribute *dme1737_in7_attr[] = {
1786 &sensor_dev_attr_in7_input.dev_attr.attr,
1787 &sensor_dev_attr_in7_min.dev_attr.attr,
1788 &sensor_dev_attr_in7_max.dev_attr.attr,
1789 &sensor_dev_attr_in7_alarm.dev_attr.attr,
1790 NULL
1791 };
1792
1793 static const struct attribute_group dme1737_in7_group = {
1794 .attrs = dme1737_in7_attr,
1795 };
1796
1797 /*
1798 * The following structs hold the PWM attributes, some of which are optional.
1799 * Their creation depends on the chip configuration which is determined during
1800 * module load.
1801 */
1802 static struct attribute *dme1737_pwm1_attr[] = {
1803 &sensor_dev_attr_pwm1.dev_attr.attr,
1804 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1805 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1806 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1807 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1808 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1809 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1810 NULL
1811 };
1812 static struct attribute *dme1737_pwm2_attr[] = {
1813 &sensor_dev_attr_pwm2.dev_attr.attr,
1814 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1815 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1816 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1817 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1818 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1819 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1820 NULL
1821 };
1822 static struct attribute *dme1737_pwm3_attr[] = {
1823 &sensor_dev_attr_pwm3.dev_attr.attr,
1824 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1825 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1826 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1827 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1828 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1829 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1830 NULL
1831 };
1832 static struct attribute *dme1737_pwm5_attr[] = {
1833 &sensor_dev_attr_pwm5.dev_attr.attr,
1834 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1835 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
1836 NULL
1837 };
1838 static struct attribute *dme1737_pwm6_attr[] = {
1839 &sensor_dev_attr_pwm6.dev_attr.attr,
1840 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1841 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
1842 NULL
1843 };
1844
1845 static const struct attribute_group dme1737_pwm_group[] = {
1846 { .attrs = dme1737_pwm1_attr },
1847 { .attrs = dme1737_pwm2_attr },
1848 { .attrs = dme1737_pwm3_attr },
1849 { .attrs = NULL },
1850 { .attrs = dme1737_pwm5_attr },
1851 { .attrs = dme1737_pwm6_attr },
1852 };
1853
1854 /*
1855 * The following struct holds auto PWM min attributes, which are not available
1856 * in all chips. Their creation depends on the chip type which is determined
1857 * during module load.
1858 */
1859 static struct attribute *dme1737_auto_pwm_min_attr[] = {
1860 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1861 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1862 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1863 };
1864
1865 /*
1866 * The following structs hold the fan attributes, some of which are optional.
1867 * Their creation depends on the chip configuration which is determined during
1868 * module load.
1869 */
1870 static struct attribute *dme1737_fan1_attr[] = {
1871 &sensor_dev_attr_fan1_input.dev_attr.attr,
1872 &sensor_dev_attr_fan1_min.dev_attr.attr,
1873 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1874 &sensor_dev_attr_fan1_type.dev_attr.attr,
1875 NULL
1876 };
1877 static struct attribute *dme1737_fan2_attr[] = {
1878 &sensor_dev_attr_fan2_input.dev_attr.attr,
1879 &sensor_dev_attr_fan2_min.dev_attr.attr,
1880 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1881 &sensor_dev_attr_fan2_type.dev_attr.attr,
1882 NULL
1883 };
1884 static struct attribute *dme1737_fan3_attr[] = {
1885 &sensor_dev_attr_fan3_input.dev_attr.attr,
1886 &sensor_dev_attr_fan3_min.dev_attr.attr,
1887 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1888 &sensor_dev_attr_fan3_type.dev_attr.attr,
1889 NULL
1890 };
1891 static struct attribute *dme1737_fan4_attr[] = {
1892 &sensor_dev_attr_fan4_input.dev_attr.attr,
1893 &sensor_dev_attr_fan4_min.dev_attr.attr,
1894 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1895 &sensor_dev_attr_fan4_type.dev_attr.attr,
1896 NULL
1897 };
1898 static struct attribute *dme1737_fan5_attr[] = {
1899 &sensor_dev_attr_fan5_input.dev_attr.attr,
1900 &sensor_dev_attr_fan5_min.dev_attr.attr,
1901 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1902 &sensor_dev_attr_fan5_max.dev_attr.attr,
1903 NULL
1904 };
1905 static struct attribute *dme1737_fan6_attr[] = {
1906 &sensor_dev_attr_fan6_input.dev_attr.attr,
1907 &sensor_dev_attr_fan6_min.dev_attr.attr,
1908 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
1909 &sensor_dev_attr_fan6_max.dev_attr.attr,
1910 NULL
1911 };
1912
1913 static const struct attribute_group dme1737_fan_group[] = {
1914 { .attrs = dme1737_fan1_attr },
1915 { .attrs = dme1737_fan2_attr },
1916 { .attrs = dme1737_fan3_attr },
1917 { .attrs = dme1737_fan4_attr },
1918 { .attrs = dme1737_fan5_attr },
1919 { .attrs = dme1737_fan6_attr },
1920 };
1921
1922 /*
1923 * The permissions of the following zone attributes are changed to read-
1924 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1925 */
1926 static struct attribute *dme1737_zone_chmod_attr[] = {
1927 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1928 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1929 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1930 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1931 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1932 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1933 NULL
1934 };
1935
1936 static const struct attribute_group dme1737_zone_chmod_group = {
1937 .attrs = dme1737_zone_chmod_attr,
1938 };
1939
1940
1941 /*
1942 * The permissions of the following zone 3 attributes are changed to read-
1943 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1944 */
1945 static struct attribute *dme1737_zone3_chmod_attr[] = {
1946 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1947 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1948 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1949 NULL
1950 };
1951
1952 static const struct attribute_group dme1737_zone3_chmod_group = {
1953 .attrs = dme1737_zone3_chmod_attr,
1954 };
1955
1956 /*
1957 * The permissions of the following PWM attributes are changed to read-
1958 * writeable if the chip is *not* locked and the respective PWM is available.
1959 * Otherwise they stay read-only.
1960 */
1961 static struct attribute *dme1737_pwm1_chmod_attr[] = {
1962 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1963 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1964 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1965 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1966 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1967 NULL
1968 };
1969 static struct attribute *dme1737_pwm2_chmod_attr[] = {
1970 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1971 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1972 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1973 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1974 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1975 NULL
1976 };
1977 static struct attribute *dme1737_pwm3_chmod_attr[] = {
1978 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1979 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1980 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1981 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1982 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1983 NULL
1984 };
1985 static struct attribute *dme1737_pwm5_chmod_attr[] = {
1986 &sensor_dev_attr_pwm5.dev_attr.attr,
1987 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1988 NULL
1989 };
1990 static struct attribute *dme1737_pwm6_chmod_attr[] = {
1991 &sensor_dev_attr_pwm6.dev_attr.attr,
1992 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1993 NULL
1994 };
1995
1996 static const struct attribute_group dme1737_pwm_chmod_group[] = {
1997 { .attrs = dme1737_pwm1_chmod_attr },
1998 { .attrs = dme1737_pwm2_chmod_attr },
1999 { .attrs = dme1737_pwm3_chmod_attr },
2000 { .attrs = NULL },
2001 { .attrs = dme1737_pwm5_chmod_attr },
2002 { .attrs = dme1737_pwm6_chmod_attr },
2003 };
2004
2005 /*
2006 * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
2007 * chip is not locked. Otherwise they are read-only.
2008 */
2009 static struct attribute *dme1737_pwm_chmod_attr[] = {
2010 &sensor_dev_attr_pwm1.dev_attr.attr,
2011 &sensor_dev_attr_pwm2.dev_attr.attr,
2012 &sensor_dev_attr_pwm3.dev_attr.attr,
2013 };
2014
2015 /* ---------------------------------------------------------------------
2016 * Super-IO functions
2017 * --------------------------------------------------------------------- */
2018
2019 static inline void dme1737_sio_enter(int sio_cip)
2020 {
2021 outb(0x55, sio_cip);
2022 }
2023
2024 static inline void dme1737_sio_exit(int sio_cip)
2025 {
2026 outb(0xaa, sio_cip);
2027 }
2028
2029 static inline int dme1737_sio_inb(int sio_cip, int reg)
2030 {
2031 outb(reg, sio_cip);
2032 return inb(sio_cip + 1);
2033 }
2034
2035 static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
2036 {
2037 outb(reg, sio_cip);
2038 outb(val, sio_cip + 1);
2039 }
2040
2041 /* ---------------------------------------------------------------------
2042 * Device initialization
2043 * --------------------------------------------------------------------- */
2044
2045 static int dme1737_i2c_get_features(int, struct dme1737_data*);
2046
2047 static void dme1737_chmod_file(struct device *dev,
2048 struct attribute *attr, umode_t mode)
2049 {
2050 if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
2051 dev_warn(dev, "Failed to change permissions of %s.\n",
2052 attr->name);
2053 }
2054 }
2055
2056 static void dme1737_chmod_group(struct device *dev,
2057 const struct attribute_group *group,
2058 umode_t mode)
2059 {
2060 struct attribute **attr;
2061
2062 for (attr = group->attrs; *attr; attr++)
2063 dme1737_chmod_file(dev, *attr, mode);
2064 }
2065
2066 static void dme1737_remove_files(struct device *dev)
2067 {
2068 struct dme1737_data *data = dev_get_drvdata(dev);
2069 int ix;
2070
2071 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
2072 if (data->has_features & HAS_FAN(ix)) {
2073 sysfs_remove_group(&dev->kobj,
2074 &dme1737_fan_group[ix]);
2075 }
2076 }
2077
2078 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
2079 if (data->has_features & HAS_PWM(ix)) {
2080 sysfs_remove_group(&dev->kobj,
2081 &dme1737_pwm_group[ix]);
2082 if ((data->has_features & HAS_PWM_MIN) && ix < 3) {
2083 sysfs_remove_file(&dev->kobj,
2084 dme1737_auto_pwm_min_attr[ix]);
2085 }
2086 }
2087 }
2088
2089 if (data->has_features & HAS_TEMP_OFFSET)
2090 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
2091 if (data->has_features & HAS_VID)
2092 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
2093 if (data->has_features & HAS_ZONE3)
2094 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
2095 if (data->has_features & HAS_ZONE_HYST)
2096 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
2097 if (data->has_features & HAS_IN7)
2098 sysfs_remove_group(&dev->kobj, &dme1737_in7_group);
2099 sysfs_remove_group(&dev->kobj, &dme1737_group);
2100
2101 if (!data->client)
2102 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
2103 }
2104
2105 static int dme1737_create_files(struct device *dev)
2106 {
2107 struct dme1737_data *data = dev_get_drvdata(dev);
2108 int err, ix;
2109
2110 /* Create a name attribute for ISA devices */
2111 if (!data->client) {
2112 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr);
2113 if (err)
2114 goto exit;
2115 }
2116
2117 /* Create standard sysfs attributes */
2118 err = sysfs_create_group(&dev->kobj, &dme1737_group);
2119 if (err)
2120 goto exit_remove;
2121
2122 /* Create chip-dependent sysfs attributes */
2123 if (data->has_features & HAS_TEMP_OFFSET) {
2124 err = sysfs_create_group(&dev->kobj,
2125 &dme1737_temp_offset_group);
2126 if (err)
2127 goto exit_remove;
2128 }
2129 if (data->has_features & HAS_VID) {
2130 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group);
2131 if (err)
2132 goto exit_remove;
2133 }
2134 if (data->has_features & HAS_ZONE3) {
2135 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group);
2136 if (err)
2137 goto exit_remove;
2138 }
2139 if (data->has_features & HAS_ZONE_HYST) {
2140 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group);
2141 if (err)
2142 goto exit_remove;
2143 }
2144 if (data->has_features & HAS_IN7) {
2145 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group);
2146 if (err)
2147 goto exit_remove;
2148 }
2149
2150 /* Create fan sysfs attributes */
2151 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
2152 if (data->has_features & HAS_FAN(ix)) {
2153 err = sysfs_create_group(&dev->kobj,
2154 &dme1737_fan_group[ix]);
2155 if (err)
2156 goto exit_remove;
2157 }
2158 }
2159
2160 /* Create PWM sysfs attributes */
2161 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
2162 if (data->has_features & HAS_PWM(ix)) {
2163 err = sysfs_create_group(&dev->kobj,
2164 &dme1737_pwm_group[ix]);
2165 if (err)
2166 goto exit_remove;
2167 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) {
2168 err = sysfs_create_file(&dev->kobj,
2169 dme1737_auto_pwm_min_attr[ix]);
2170 if (err)
2171 goto exit_remove;
2172 }
2173 }
2174 }
2175
2176 /*
2177 * Inform if the device is locked. Otherwise change the permissions of
2178 * selected attributes from read-only to read-writeable.
2179 */
2180 if (data->config & 0x02) {
2181 dev_info(dev, "Device is locked. Some attributes "
2182 "will be read-only.\n");
2183 } else {
2184 /* Change permissions of zone sysfs attributes */
2185 dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
2186 S_IRUGO | S_IWUSR);
2187
2188 /* Change permissions of chip-dependent sysfs attributes */
2189 if (data->has_features & HAS_TEMP_OFFSET) {
2190 dme1737_chmod_group(dev, &dme1737_temp_offset_group,
2191 S_IRUGO | S_IWUSR);
2192 }
2193 if (data->has_features & HAS_ZONE3) {
2194 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group,
2195 S_IRUGO | S_IWUSR);
2196 }
2197 if (data->has_features & HAS_ZONE_HYST) {
2198 dme1737_chmod_group(dev, &dme1737_zone_hyst_group,
2199 S_IRUGO | S_IWUSR);
2200 }
2201
2202 /* Change permissions of PWM sysfs attributes */
2203 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
2204 if (data->has_features & HAS_PWM(ix)) {
2205 dme1737_chmod_group(dev,
2206 &dme1737_pwm_chmod_group[ix],
2207 S_IRUGO | S_IWUSR);
2208 if ((data->has_features & HAS_PWM_MIN) &&
2209 ix < 3) {
2210 dme1737_chmod_file(dev,
2211 dme1737_auto_pwm_min_attr[ix],
2212 S_IRUGO | S_IWUSR);
2213 }
2214 }
2215 }
2216
2217 /* Change permissions of pwm[1-3] if in manual mode */
2218 for (ix = 0; ix < 3; ix++) {
2219 if ((data->has_features & HAS_PWM(ix)) &&
2220 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
2221 dme1737_chmod_file(dev,
2222 dme1737_pwm_chmod_attr[ix],
2223 S_IRUGO | S_IWUSR);
2224 }
2225 }
2226 }
2227
2228 return 0;
2229
2230 exit_remove:
2231 dme1737_remove_files(dev);
2232 exit:
2233 return err;
2234 }
2235
2236 static int dme1737_init_device(struct device *dev)
2237 {
2238 struct dme1737_data *data = dev_get_drvdata(dev);
2239 struct i2c_client *client = data->client;
2240 int ix;
2241 u8 reg;
2242
2243 /* Point to the right nominal voltages array */
2244 data->in_nominal = IN_NOMINAL(data->type);
2245
2246 data->config = dme1737_read(data, DME1737_REG_CONFIG);
2247 /* Inform if part is not monitoring/started */
2248 if (!(data->config & 0x01)) {
2249 if (!force_start) {
2250 dev_err(dev, "Device is not monitoring. "
2251 "Use the force_start load parameter to "
2252 "override.\n");
2253 return -EFAULT;
2254 }
2255
2256 /* Force monitoring */
2257 data->config |= 0x01;
2258 dme1737_write(data, DME1737_REG_CONFIG, data->config);
2259 }
2260 /* Inform if part is not ready */
2261 if (!(data->config & 0x04)) {
2262 dev_err(dev, "Device is not ready.\n");
2263 return -EFAULT;
2264 }
2265
2266 /*
2267 * Determine which optional fan and pwm features are enabled (only
2268 * valid for I2C devices)
2269 */
2270 if (client) { /* I2C chip */
2271 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
2272 /* Check if optional fan3 input is enabled */
2273 if (data->config2 & 0x04)
2274 data->has_features |= HAS_FAN(2);
2275
2276 /*
2277 * Fan4 and pwm3 are only available if the client's I2C address
2278 * is the default 0x2e. Otherwise the I/Os associated with
2279 * these functions are used for addr enable/select.
2280 */
2281 if (client->addr == 0x2e)
2282 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
2283
2284 /*
2285 * Determine which of the optional fan[5-6] and pwm[5-6]
2286 * features are enabled. For this, we need to query the runtime
2287 * registers through the Super-IO LPC interface. Try both
2288 * config ports 0x2e and 0x4e.
2289 */
2290 if (dme1737_i2c_get_features(0x2e, data) &&
2291 dme1737_i2c_get_features(0x4e, data)) {
2292 dev_warn(dev, "Failed to query Super-IO for optional "
2293 "features.\n");
2294 }
2295 }
2296
2297 /* Fan[1-2] and pwm[1-2] are present in all chips */
2298 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1);
2299
2300 /* Chip-dependent features */
2301 switch (data->type) {
2302 case dme1737:
2303 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 |
2304 HAS_ZONE_HYST | HAS_PWM_MIN;
2305 break;
2306 case sch311x:
2307 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 |
2308 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2);
2309 break;
2310 case sch5027:
2311 data->has_features |= HAS_ZONE3;
2312 break;
2313 case sch5127:
2314 data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7;
2315 break;
2316 default:
2317 break;
2318 }
2319
2320 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, "
2321 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
2322 (data->has_features & HAS_PWM(2)) ? "yes" : "no",
2323 (data->has_features & HAS_PWM(4)) ? "yes" : "no",
2324 (data->has_features & HAS_PWM(5)) ? "yes" : "no",
2325 (data->has_features & HAS_FAN(2)) ? "yes" : "no",
2326 (data->has_features & HAS_FAN(3)) ? "yes" : "no",
2327 (data->has_features & HAS_FAN(4)) ? "yes" : "no",
2328 (data->has_features & HAS_FAN(5)) ? "yes" : "no");
2329
2330 reg = dme1737_read(data, DME1737_REG_TACH_PWM);
2331 /* Inform if fan-to-pwm mapping differs from the default */
2332 if (client && reg != 0xa4) { /* I2C chip */
2333 dev_warn(dev, "Non-standard fan to pwm mapping: "
2334 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, "
2335 "fan4->pwm%d. Please report to the driver "
2336 "maintainer.\n",
2337 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2338 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1);
2339 } else if (!client && reg != 0x24) { /* ISA chip */
2340 dev_warn(dev, "Non-standard fan to pwm mapping: "
2341 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. "
2342 "Please report to the driver maintainer.\n",
2343 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2344 ((reg >> 4) & 0x03) + 1);
2345 }
2346
2347 /*
2348 * Switch pwm[1-3] to manual mode if they are currently disabled and
2349 * set the duty-cycles to 0% (which is identical to the PWMs being
2350 * disabled).
2351 */
2352 if (!(data->config & 0x02)) {
2353 for (ix = 0; ix < 3; ix++) {
2354 data->pwm_config[ix] = dme1737_read(data,
2355 DME1737_REG_PWM_CONFIG(ix));
2356 if ((data->has_features & HAS_PWM(ix)) &&
2357 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
2358 dev_info(dev, "Switching pwm%d to "
2359 "manual mode.\n", ix + 1);
2360 data->pwm_config[ix] = PWM_EN_TO_REG(1,
2361 data->pwm_config[ix]);
2362 dme1737_write(data, DME1737_REG_PWM(ix), 0);
2363 dme1737_write(data,
2364 DME1737_REG_PWM_CONFIG(ix),
2365 data->pwm_config[ix]);
2366 }
2367 }
2368 }
2369
2370 /* Initialize the default PWM auto channels zone (acz) assignments */
2371 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
2372 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
2373 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2374
2375 /* Set VRM */
2376 if (data->has_features & HAS_VID)
2377 data->vrm = vid_which_vrm();
2378
2379 return 0;
2380 }
2381
2382 /* ---------------------------------------------------------------------
2383 * I2C device detection and registration
2384 * --------------------------------------------------------------------- */
2385
2386 static struct i2c_driver dme1737_i2c_driver;
2387
2388 static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2389 {
2390 int err = 0, reg;
2391 u16 addr;
2392
2393 dme1737_sio_enter(sio_cip);
2394
2395 /*
2396 * Check device ID
2397 * We currently know about two kinds of DME1737 and SCH5027.
2398 */
2399 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2400 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2401 reg == SCH5027_ID)) {
2402 err = -ENODEV;
2403 goto exit;
2404 }
2405
2406 /* Select logical device A (runtime registers) */
2407 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2408
2409 /* Get the base address of the runtime registers */
2410 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2411 dme1737_sio_inb(sio_cip, 0x61);
2412 if (!addr) {
2413 err = -ENODEV;
2414 goto exit;
2415 }
2416
2417 /*
2418 * Read the runtime registers to determine which optional features
2419 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
2420 * to '10' if the respective feature is enabled.
2421 */
2422 if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */
2423 data->has_features |= HAS_FAN(5);
2424 if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */
2425 data->has_features |= HAS_PWM(5);
2426 if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */
2427 data->has_features |= HAS_FAN(4);
2428 if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */
2429 data->has_features |= HAS_PWM(4);
2430
2431 exit:
2432 dme1737_sio_exit(sio_cip);
2433
2434 return err;
2435 }
2436
2437 /* Return 0 if detection is successful, -ENODEV otherwise */
2438 static int dme1737_i2c_detect(struct i2c_client *client,
2439 struct i2c_board_info *info)
2440 {
2441 struct i2c_adapter *adapter = client->adapter;
2442 struct device *dev = &adapter->dev;
2443 u8 company, verstep = 0;
2444 const char *name;
2445
2446 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2447 return -ENODEV;
2448
2449 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2450 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
2451
2452 if (company == DME1737_COMPANY_SMSC &&
2453 verstep == SCH5027_VERSTEP) {
2454 name = "sch5027";
2455 } else if (company == DME1737_COMPANY_SMSC &&
2456 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
2457 name = "dme1737";
2458 } else {
2459 return -ENODEV;
2460 }
2461
2462 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
2463 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737",
2464 client->addr, verstep);
2465 strlcpy(info->type, name, I2C_NAME_SIZE);
2466
2467 return 0;
2468 }
2469
2470 static int dme1737_i2c_probe(struct i2c_client *client,
2471 const struct i2c_device_id *id)
2472 {
2473 struct dme1737_data *data;
2474 struct device *dev = &client->dev;
2475 int err;
2476
2477 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2478 if (!data)
2479 return -ENOMEM;
2480
2481 i2c_set_clientdata(client, data);
2482 data->type = id->driver_data;
2483 data->client = client;
2484 data->name = client->name;
2485 mutex_init(&data->update_lock);
2486
2487 /* Initialize the DME1737 chip */
2488 err = dme1737_init_device(dev);
2489 if (err) {
2490 dev_err(dev, "Failed to initialize device.\n");
2491 return err;
2492 }
2493
2494 /* Create sysfs files */
2495 err = dme1737_create_files(dev);
2496 if (err) {
2497 dev_err(dev, "Failed to create sysfs files.\n");
2498 return err;
2499 }
2500
2501 /* Register device */
2502 data->hwmon_dev = hwmon_device_register(dev);
2503 if (IS_ERR(data->hwmon_dev)) {
2504 dev_err(dev, "Failed to register device.\n");
2505 err = PTR_ERR(data->hwmon_dev);
2506 goto exit_remove;
2507 }
2508
2509 return 0;
2510
2511 exit_remove:
2512 dme1737_remove_files(dev);
2513 return err;
2514 }
2515
2516 static int dme1737_i2c_remove(struct i2c_client *client)
2517 {
2518 struct dme1737_data *data = i2c_get_clientdata(client);
2519
2520 hwmon_device_unregister(data->hwmon_dev);
2521 dme1737_remove_files(&client->dev);
2522
2523 return 0;
2524 }
2525
2526 static const struct i2c_device_id dme1737_id[] = {
2527 { "dme1737", dme1737 },
2528 { "sch5027", sch5027 },
2529 { }
2530 };
2531 MODULE_DEVICE_TABLE(i2c, dme1737_id);
2532
2533 static struct i2c_driver dme1737_i2c_driver = {
2534 .class = I2C_CLASS_HWMON,
2535 .driver = {
2536 .name = "dme1737",
2537 },
2538 .probe = dme1737_i2c_probe,
2539 .remove = dme1737_i2c_remove,
2540 .id_table = dme1737_id,
2541 .detect = dme1737_i2c_detect,
2542 .address_list = normal_i2c,
2543 };
2544
2545 /* ---------------------------------------------------------------------
2546 * ISA device detection and registration
2547 * --------------------------------------------------------------------- */
2548
2549 static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2550 {
2551 int err = 0, reg;
2552 unsigned short base_addr;
2553
2554 dme1737_sio_enter(sio_cip);
2555
2556 /*
2557 * Check device ID
2558 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127
2559 */
2560 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2561 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2562 reg == SCH5127_ID)) {
2563 err = -ENODEV;
2564 goto exit;
2565 }
2566
2567 /* Select logical device A (runtime registers) */
2568 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2569
2570 /* Get the base address of the runtime registers */
2571 base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2572 dme1737_sio_inb(sio_cip, 0x61);
2573 if (!base_addr) {
2574 pr_err("Base address not set\n");
2575 err = -ENODEV;
2576 goto exit;
2577 }
2578
2579 /*
2580 * Access to the hwmon registers is through an index/data register
2581 * pair located at offset 0x70/0x71.
2582 */
2583 *addr = base_addr + 0x70;
2584
2585 exit:
2586 dme1737_sio_exit(sio_cip);
2587 return err;
2588 }
2589
2590 static int __init dme1737_isa_device_add(unsigned short addr)
2591 {
2592 struct resource res = {
2593 .start = addr,
2594 .end = addr + DME1737_EXTENT - 1,
2595 .name = "dme1737",
2596 .flags = IORESOURCE_IO,
2597 };
2598 int err;
2599
2600 err = acpi_check_resource_conflict(&res);
2601 if (err)
2602 goto exit;
2603
2604 pdev = platform_device_alloc("dme1737", addr);
2605 if (!pdev) {
2606 pr_err("Failed to allocate device\n");
2607 err = -ENOMEM;
2608 goto exit;
2609 }
2610
2611 err = platform_device_add_resources(pdev, &res, 1);
2612 if (err) {
2613 pr_err("Failed to add device resource (err = %d)\n", err);
2614 goto exit_device_put;
2615 }
2616
2617 err = platform_device_add(pdev);
2618 if (err) {
2619 pr_err("Failed to add device (err = %d)\n", err);
2620 goto exit_device_put;
2621 }
2622
2623 return 0;
2624
2625 exit_device_put:
2626 platform_device_put(pdev);
2627 pdev = NULL;
2628 exit:
2629 return err;
2630 }
2631
2632 static int dme1737_isa_probe(struct platform_device *pdev)
2633 {
2634 u8 company, device;
2635 struct resource *res;
2636 struct dme1737_data *data;
2637 struct device *dev = &pdev->dev;
2638 int err;
2639
2640 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2641 if (!devm_request_region(dev, res->start, DME1737_EXTENT, "dme1737")) {
2642 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
2643 (unsigned short)res->start,
2644 (unsigned short)res->start + DME1737_EXTENT - 1);
2645 return -EBUSY;
2646 }
2647
2648 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2649 if (!data)
2650 return -ENOMEM;
2651
2652 data->addr = res->start;
2653 platform_set_drvdata(pdev, data);
2654
2655 /* Skip chip detection if module is loaded with force_id parameter */
2656 switch (force_id) {
2657 case SCH3112_ID:
2658 case SCH3114_ID:
2659 case SCH3116_ID:
2660 data->type = sch311x;
2661 break;
2662 case SCH5127_ID:
2663 data->type = sch5127;
2664 break;
2665 default:
2666 company = dme1737_read(data, DME1737_REG_COMPANY);
2667 device = dme1737_read(data, DME1737_REG_DEVICE);
2668
2669 if ((company == DME1737_COMPANY_SMSC) &&
2670 (device == SCH311X_DEVICE)) {
2671 data->type = sch311x;
2672 } else if ((company == DME1737_COMPANY_SMSC) &&
2673 (device == SCH5127_DEVICE)) {
2674 data->type = sch5127;
2675 } else {
2676 return -ENODEV;
2677 }
2678 }
2679
2680 if (data->type == sch5127)
2681 data->name = "sch5127";
2682 else
2683 data->name = "sch311x";
2684
2685 /* Initialize the mutex */
2686 mutex_init(&data->update_lock);
2687
2688 dev_info(dev, "Found a %s chip at 0x%04x\n",
2689 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr);
2690
2691 /* Initialize the chip */
2692 err = dme1737_init_device(dev);
2693 if (err) {
2694 dev_err(dev, "Failed to initialize device.\n");
2695 return err;
2696 }
2697
2698 /* Create sysfs files */
2699 err = dme1737_create_files(dev);
2700 if (err) {
2701 dev_err(dev, "Failed to create sysfs files.\n");
2702 return err;
2703 }
2704
2705 /* Register device */
2706 data->hwmon_dev = hwmon_device_register(dev);
2707 if (IS_ERR(data->hwmon_dev)) {
2708 dev_err(dev, "Failed to register device.\n");
2709 err = PTR_ERR(data->hwmon_dev);
2710 goto exit_remove_files;
2711 }
2712
2713 return 0;
2714
2715 exit_remove_files:
2716 dme1737_remove_files(dev);
2717 return err;
2718 }
2719
2720 static int dme1737_isa_remove(struct platform_device *pdev)
2721 {
2722 struct dme1737_data *data = platform_get_drvdata(pdev);
2723
2724 hwmon_device_unregister(data->hwmon_dev);
2725 dme1737_remove_files(&pdev->dev);
2726
2727 return 0;
2728 }
2729
2730 static struct platform_driver dme1737_isa_driver = {
2731 .driver = {
2732 .owner = THIS_MODULE,
2733 .name = "dme1737",
2734 },
2735 .probe = dme1737_isa_probe,
2736 .remove = dme1737_isa_remove,
2737 };
2738
2739 /* ---------------------------------------------------------------------
2740 * Module initialization and cleanup
2741 * --------------------------------------------------------------------- */
2742
2743 static int __init dme1737_init(void)
2744 {
2745 int err;
2746 unsigned short addr;
2747
2748 err = i2c_add_driver(&dme1737_i2c_driver);
2749 if (err)
2750 goto exit;
2751
2752 if (dme1737_isa_detect(0x2e, &addr) &&
2753 dme1737_isa_detect(0x4e, &addr) &&
2754 (!probe_all_addr ||
2755 (dme1737_isa_detect(0x162e, &addr) &&
2756 dme1737_isa_detect(0x164e, &addr)))) {
2757 /* Return 0 if we didn't find an ISA device */
2758 return 0;
2759 }
2760
2761 err = platform_driver_register(&dme1737_isa_driver);
2762 if (err)
2763 goto exit_del_i2c_driver;
2764
2765 /* Sets global pdev as a side effect */
2766 err = dme1737_isa_device_add(addr);
2767 if (err)
2768 goto exit_del_isa_driver;
2769
2770 return 0;
2771
2772 exit_del_isa_driver:
2773 platform_driver_unregister(&dme1737_isa_driver);
2774 exit_del_i2c_driver:
2775 i2c_del_driver(&dme1737_i2c_driver);
2776 exit:
2777 return err;
2778 }
2779
2780 static void __exit dme1737_exit(void)
2781 {
2782 if (pdev) {
2783 platform_device_unregister(pdev);
2784 platform_driver_unregister(&dme1737_isa_driver);
2785 }
2786
2787 i2c_del_driver(&dme1737_i2c_driver);
2788 }
2789
2790 MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
2791 MODULE_DESCRIPTION("DME1737 sensors");
2792 MODULE_LICENSE("GPL");
2793
2794 module_init(dme1737_init);
2795 module_exit(dme1737_exit);
Linux kernel - Deliverables
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