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Merge tag 'for-linus-3.11-merge-window-part-1' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / hwmon / dme1737.c
1 /*
2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
3 * and SCH5127 Super-I/O chips integrated hardware monitoring
4 * features.
5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
6 *
7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very
10 * similar hardware monitoring capabilities but differ in the way they can be
11 * accessed.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/slab.h>
33 #include <linux/jiffies.h>
34 #include <linux/i2c.h>
35 #include <linux/platform_device.h>
36 #include <linux/hwmon.h>
37 #include <linux/hwmon-sysfs.h>
38 #include <linux/hwmon-vid.h>
39 #include <linux/err.h>
40 #include <linux/mutex.h>
41 #include <linux/acpi.h>
42 #include <linux/io.h>
43
44 /* ISA device, if found */
45 static struct platform_device *pdev;
46
47 /* Module load parameters */
48 static bool force_start;
49 module_param(force_start, bool, 0);
50 MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
51
52 static unsigned short force_id;
53 module_param(force_id, ushort, 0);
54 MODULE_PARM_DESC(force_id, "Override the detected device ID");
55
56 static bool probe_all_addr;
57 module_param(probe_all_addr, bool, 0);
58 MODULE_PARM_DESC(probe_all_addr,
59 "Include probing of non-standard LPC addresses");
60
61 /* Addresses to scan */
62 static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
63
64 enum chips { dme1737, sch5027, sch311x, sch5127 };
65
66 #define DO_REPORT "Please report to the driver maintainer."
67
68 /* ---------------------------------------------------------------------
69 * Registers
70 *
71 * The sensors are defined as follows:
72 *
73 * Voltages Temperatures
74 * -------- ------------
75 * in0 +5VTR (+5V stdby) temp1 Remote diode 1
76 * in1 Vccp (proc core) temp2 Internal temp
77 * in2 VCC (internal +3.3V) temp3 Remote diode 2
78 * in3 +5V
79 * in4 +12V
80 * in5 VTR (+3.3V stby)
81 * in6 Vbat
82 * in7 Vtrip (sch5127 only)
83 *
84 * --------------------------------------------------------------------- */
85
86 /* Voltages (in) numbered 0-7 (ix) */
87 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
88 (ix) < 7 ? 0x94 + (ix) : \
89 0x1f)
90 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
91 : 0x91 + (ix) * 2)
92 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
93 : 0x92 + (ix) * 2)
94
95 /* Temperatures (temp) numbered 0-2 (ix) */
96 #define DME1737_REG_TEMP(ix) (0x25 + (ix))
97 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
98 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
99 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
100 : 0x1c + (ix))
101
102 /*
103 * Voltage and temperature LSBs
104 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
105 * IN_TEMP_LSB(0) = [in5, in6]
106 * IN_TEMP_LSB(1) = [temp3, temp1]
107 * IN_TEMP_LSB(2) = [in4, temp2]
108 * IN_TEMP_LSB(3) = [in3, in0]
109 * IN_TEMP_LSB(4) = [in2, in1]
110 * IN_TEMP_LSB(5) = [res, in7]
111 */
112 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
113 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
114 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
115 static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
116 static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
117
118 /* Fans numbered 0-5 (ix) */
119 #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
120 : 0xa1 + (ix) * 2)
121 #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
122 : 0xa5 + (ix) * 2)
123 #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
124 : 0xb2 + (ix))
125 #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
126
127 /* PWMs numbered 0-2, 4-5 (ix) */
128 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
129 : 0xa1 + (ix))
130 #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
131 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
132 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
133 : 0xa3 + (ix))
134 /*
135 * The layout of the ramp rate registers is different from the other pwm
136 * registers. The bits for the 3 PWMs are stored in 2 registers:
137 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
138 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
139 */
140 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
141
142 /* Thermal zones 0-2 */
143 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
144 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
145 /*
146 * The layout of the hysteresis registers is different from the other zone
147 * registers. The bits for the 3 zones are stored in 2 registers:
148 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
149 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES]
150 */
151 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
152
153 /*
154 * Alarm registers and bit mapping
155 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
156 * alarm value [0, ALARM3, ALARM2, ALARM1].
157 */
158 #define DME1737_REG_ALARM1 0x41
159 #define DME1737_REG_ALARM2 0x42
160 #define DME1737_REG_ALARM3 0x83
161 static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18};
162 static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
163 static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
164
165 /* Miscellaneous registers */
166 #define DME1737_REG_DEVICE 0x3d
167 #define DME1737_REG_COMPANY 0x3e
168 #define DME1737_REG_VERSTEP 0x3f
169 #define DME1737_REG_CONFIG 0x40
170 #define DME1737_REG_CONFIG2 0x7f
171 #define DME1737_REG_VID 0x43
172 #define DME1737_REG_TACH_PWM 0x81
173
174 /* ---------------------------------------------------------------------
175 * Misc defines
176 * --------------------------------------------------------------------- */
177
178 /* Chip identification */
179 #define DME1737_COMPANY_SMSC 0x5c
180 #define DME1737_VERSTEP 0x88
181 #define DME1737_VERSTEP_MASK 0xf8
182 #define SCH311X_DEVICE 0x8c
183 #define SCH5027_VERSTEP 0x69
184 #define SCH5127_DEVICE 0x8e
185
186 /* Device ID values (global configuration register index 0x20) */
187 #define DME1737_ID_1 0x77
188 #define DME1737_ID_2 0x78
189 #define SCH3112_ID 0x7c
190 #define SCH3114_ID 0x7d
191 #define SCH3116_ID 0x7f
192 #define SCH5027_ID 0x89
193 #define SCH5127_ID 0x86
194
195 /* Length of ISA address segment */
196 #define DME1737_EXTENT 2
197
198 /* chip-dependent features */
199 #define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */
200 #define HAS_VID (1 << 1) /* bit 1 */
201 #define HAS_ZONE3 (1 << 2) /* bit 2 */
202 #define HAS_ZONE_HYST (1 << 3) /* bit 3 */
203 #define HAS_PWM_MIN (1 << 4) /* bit 4 */
204 #define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */
205 #define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */
206 #define HAS_IN7 (1 << 17) /* bit 17 */
207
208 /* ---------------------------------------------------------------------
209 * Data structures and manipulation thereof
210 * --------------------------------------------------------------------- */
211
212 struct dme1737_data {
213 struct i2c_client *client; /* for I2C devices only */
214 struct device *hwmon_dev;
215 const char *name;
216 unsigned int addr; /* for ISA devices only */
217
218 struct mutex update_lock;
219 int valid; /* !=0 if following fields are valid */
220 unsigned long last_update; /* in jiffies */
221 unsigned long last_vbat; /* in jiffies */
222 enum chips type;
223 const int *in_nominal; /* pointer to IN_NOMINAL array */
224
225 u8 vid;
226 u8 pwm_rr_en;
227 u32 has_features;
228
229 /* Register values */
230 u16 in[8];
231 u8 in_min[8];
232 u8 in_max[8];
233 s16 temp[3];
234 s8 temp_min[3];
235 s8 temp_max[3];
236 s8 temp_offset[3];
237 u8 config;
238 u8 config2;
239 u8 vrm;
240 u16 fan[6];
241 u16 fan_min[6];
242 u8 fan_max[2];
243 u8 fan_opt[6];
244 u8 pwm[6];
245 u8 pwm_min[3];
246 u8 pwm_config[3];
247 u8 pwm_acz[3];
248 u8 pwm_freq[6];
249 u8 pwm_rr[2];
250 u8 zone_low[3];
251 u8 zone_abs[3];
252 u8 zone_hyst[2];
253 u32 alarms;
254 };
255
256 /* Nominal voltage values */
257 static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
258 3300};
259 static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
260 3300};
261 static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
262 3300};
263 static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
264 3300, 1500};
265 #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
266 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
267 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
268 IN_NOMINAL_DME1737)
269
270 /*
271 * Voltage input
272 * Voltage inputs have 16 bits resolution, limit values have 8 bits
273 * resolution.
274 */
275 static inline int IN_FROM_REG(int reg, int nominal, int res)
276 {
277 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
278 }
279
280 static inline int IN_TO_REG(int val, int nominal)
281 {
282 return clamp_val((val * 192 + nominal / 2) / nominal, 0, 255);
283 }
284
285 /*
286 * Temperature input
287 * The register values represent temperatures in 2's complement notation from
288 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
289 * values have 8 bits resolution.
290 */
291 static inline int TEMP_FROM_REG(int reg, int res)
292 {
293 return (reg * 1000) >> (res - 8);
294 }
295
296 static inline int TEMP_TO_REG(int val)
297 {
298 return clamp_val((val < 0 ? val - 500 : val + 500) / 1000, -128, 127);
299 }
300
301 /* Temperature range */
302 static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
303 10000, 13333, 16000, 20000, 26666, 32000,
304 40000, 53333, 80000};
305
306 static inline int TEMP_RANGE_FROM_REG(int reg)
307 {
308 return TEMP_RANGE[(reg >> 4) & 0x0f];
309 }
310
311 static int TEMP_RANGE_TO_REG(int val, int reg)
312 {
313 int i;
314
315 for (i = 15; i > 0; i--) {
316 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
317 break;
318 }
319
320 return (reg & 0x0f) | (i << 4);
321 }
322
323 /*
324 * Temperature hysteresis
325 * Register layout:
326 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
327 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
328 */
329 static inline int TEMP_HYST_FROM_REG(int reg, int ix)
330 {
331 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
332 }
333
334 static inline int TEMP_HYST_TO_REG(int val, int ix, int reg)
335 {
336 int hyst = clamp_val((val + 500) / 1000, 0, 15);
337
338 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
339 }
340
341 /* Fan input RPM */
342 static inline int FAN_FROM_REG(int reg, int tpc)
343 {
344 if (tpc)
345 return tpc * reg;
346 else
347 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
348 }
349
350 static inline int FAN_TO_REG(int val, int tpc)
351 {
352 if (tpc) {
353 return clamp_val(val / tpc, 0, 0xffff);
354 } else {
355 return (val <= 0) ? 0xffff :
356 clamp_val(90000 * 60 / val, 0, 0xfffe);
357 }
358 }
359
360 /*
361 * Fan TPC (tach pulse count)
362 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
363 * is configured in legacy (non-tpc) mode
364 */
365 static inline int FAN_TPC_FROM_REG(int reg)
366 {
367 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
368 }
369
370 /*
371 * Fan type
372 * The type of a fan is expressed in number of pulses-per-revolution that it
373 * emits
374 */
375 static inline int FAN_TYPE_FROM_REG(int reg)
376 {
377 int edge = (reg >> 1) & 0x03;
378
379 return (edge > 0) ? 1 << (edge - 1) : 0;
380 }
381
382 static inline int FAN_TYPE_TO_REG(int val, int reg)
383 {
384 int edge = (val == 4) ? 3 : val;
385
386 return (reg & 0xf9) | (edge << 1);
387 }
388
389 /* Fan max RPM */
390 static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
391 0x11, 0x0f, 0x0e};
392
393 static int FAN_MAX_FROM_REG(int reg)
394 {
395 int i;
396
397 for (i = 10; i > 0; i--) {
398 if (reg == FAN_MAX[i])
399 break;
400 }
401
402 return 1000 + i * 500;
403 }
404
405 static int FAN_MAX_TO_REG(int val)
406 {
407 int i;
408
409 for (i = 10; i > 0; i--) {
410 if (val > (1000 + (i - 1) * 500))
411 break;
412 }
413
414 return FAN_MAX[i];
415 }
416
417 /*
418 * PWM enable
419 * Register to enable mapping:
420 * 000: 2 fan on zone 1 auto
421 * 001: 2 fan on zone 2 auto
422 * 010: 2 fan on zone 3 auto
423 * 011: 0 fan full on
424 * 100: -1 fan disabled
425 * 101: 2 fan on hottest of zones 2,3 auto
426 * 110: 2 fan on hottest of zones 1,2,3 auto
427 * 111: 1 fan in manual mode
428 */
429 static inline int PWM_EN_FROM_REG(int reg)
430 {
431 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
432
433 return en[(reg >> 5) & 0x07];
434 }
435
436 static inline int PWM_EN_TO_REG(int val, int reg)
437 {
438 int en = (val == 1) ? 7 : 3;
439
440 return (reg & 0x1f) | ((en & 0x07) << 5);
441 }
442
443 /*
444 * PWM auto channels zone
445 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
446 * corresponding to zone x+1):
447 * 000: 001 fan on zone 1 auto
448 * 001: 010 fan on zone 2 auto
449 * 010: 100 fan on zone 3 auto
450 * 011: 000 fan full on
451 * 100: 000 fan disabled
452 * 101: 110 fan on hottest of zones 2,3 auto
453 * 110: 111 fan on hottest of zones 1,2,3 auto
454 * 111: 000 fan in manual mode
455 */
456 static inline int PWM_ACZ_FROM_REG(int reg)
457 {
458 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
459
460 return acz[(reg >> 5) & 0x07];
461 }
462
463 static inline int PWM_ACZ_TO_REG(int val, int reg)
464 {
465 int acz = (val == 4) ? 2 : val - 1;
466
467 return (reg & 0x1f) | ((acz & 0x07) << 5);
468 }
469
470 /* PWM frequency */
471 static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
472 15000, 20000, 30000, 25000, 0, 0, 0, 0};
473
474 static inline int PWM_FREQ_FROM_REG(int reg)
475 {
476 return PWM_FREQ[reg & 0x0f];
477 }
478
479 static int PWM_FREQ_TO_REG(int val, int reg)
480 {
481 int i;
482
483 /* the first two cases are special - stupid chip design! */
484 if (val > 27500) {
485 i = 10;
486 } else if (val > 22500) {
487 i = 11;
488 } else {
489 for (i = 9; i > 0; i--) {
490 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
491 break;
492 }
493 }
494
495 return (reg & 0xf0) | i;
496 }
497
498 /*
499 * PWM ramp rate
500 * Register layout:
501 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
502 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
503 */
504 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
505
506 static inline int PWM_RR_FROM_REG(int reg, int ix)
507 {
508 int rr = (ix == 1) ? reg >> 4 : reg;
509
510 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
511 }
512
513 static int PWM_RR_TO_REG(int val, int ix, int reg)
514 {
515 int i;
516
517 for (i = 0; i < 7; i++) {
518 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
519 break;
520 }
521
522 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
523 }
524
525 /* PWM ramp rate enable */
526 static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
527 {
528 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
529 }
530
531 static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg)
532 {
533 int en = (ix == 1) ? 0x80 : 0x08;
534
535 return val ? reg | en : reg & ~en;
536 }
537
538 /*
539 * PWM min/off
540 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
541 * the register layout).
542 */
543 static inline int PWM_OFF_FROM_REG(int reg, int ix)
544 {
545 return (reg >> (ix + 5)) & 0x01;
546 }
547
548 static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
549 {
550 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
551 }
552
553 /* ---------------------------------------------------------------------
554 * Device I/O access
555 *
556 * ISA access is performed through an index/data register pair and needs to
557 * be protected by a mutex during runtime (not required for initialization).
558 * We use data->update_lock for this and need to ensure that we acquire it
559 * before calling dme1737_read or dme1737_write.
560 * --------------------------------------------------------------------- */
561
562 static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
563 {
564 struct i2c_client *client = data->client;
565 s32 val;
566
567 if (client) { /* I2C device */
568 val = i2c_smbus_read_byte_data(client, reg);
569
570 if (val < 0) {
571 dev_warn(&client->dev,
572 "Read from register 0x%02x failed! %s\n",
573 reg, DO_REPORT);
574 }
575 } else { /* ISA device */
576 outb(reg, data->addr);
577 val = inb(data->addr + 1);
578 }
579
580 return val;
581 }
582
583 static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
584 {
585 struct i2c_client *client = data->client;
586 s32 res = 0;
587
588 if (client) { /* I2C device */
589 res = i2c_smbus_write_byte_data(client, reg, val);
590
591 if (res < 0) {
592 dev_warn(&client->dev,
593 "Write to register 0x%02x failed! %s\n",
594 reg, DO_REPORT);
595 }
596 } else { /* ISA device */
597 outb(reg, data->addr);
598 outb(val, data->addr + 1);
599 }
600
601 return res;
602 }
603
604 static struct dme1737_data *dme1737_update_device(struct device *dev)
605 {
606 struct dme1737_data *data = dev_get_drvdata(dev);
607 int ix;
608 u8 lsb[6];
609
610 mutex_lock(&data->update_lock);
611
612 /* Enable a Vbat monitoring cycle every 10 mins */
613 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
614 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
615 DME1737_REG_CONFIG) | 0x10);
616 data->last_vbat = jiffies;
617 }
618
619 /* Sample register contents every 1 sec */
620 if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
621 if (data->has_features & HAS_VID) {
622 data->vid = dme1737_read(data, DME1737_REG_VID) &
623 0x3f;
624 }
625
626 /* In (voltage) registers */
627 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
628 /*
629 * Voltage inputs are stored as 16 bit values even
630 * though they have only 12 bits resolution. This is
631 * to make it consistent with the temp inputs.
632 */
633 if (ix == 7 && !(data->has_features & HAS_IN7))
634 continue;
635 data->in[ix] = dme1737_read(data,
636 DME1737_REG_IN(ix)) << 8;
637 data->in_min[ix] = dme1737_read(data,
638 DME1737_REG_IN_MIN(ix));
639 data->in_max[ix] = dme1737_read(data,
640 DME1737_REG_IN_MAX(ix));
641 }
642
643 /* Temp registers */
644 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
645 /*
646 * Temp inputs are stored as 16 bit values even
647 * though they have only 12 bits resolution. This is
648 * to take advantage of implicit conversions between
649 * register values (2's complement) and temp values
650 * (signed decimal).
651 */
652 data->temp[ix] = dme1737_read(data,
653 DME1737_REG_TEMP(ix)) << 8;
654 data->temp_min[ix] = dme1737_read(data,
655 DME1737_REG_TEMP_MIN(ix));
656 data->temp_max[ix] = dme1737_read(data,
657 DME1737_REG_TEMP_MAX(ix));
658 if (data->has_features & HAS_TEMP_OFFSET) {
659 data->temp_offset[ix] = dme1737_read(data,
660 DME1737_REG_TEMP_OFFSET(ix));
661 }
662 }
663
664 /*
665 * In and temp LSB registers
666 * The LSBs are latched when the MSBs are read, so the order in
667 * which the registers are read (MSB first, then LSB) is
668 * important!
669 */
670 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
671 if (ix == 5 && !(data->has_features & HAS_IN7))
672 continue;
673 lsb[ix] = dme1737_read(data,
674 DME1737_REG_IN_TEMP_LSB(ix));
675 }
676 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
677 if (ix == 7 && !(data->has_features & HAS_IN7))
678 continue;
679 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
680 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
681 }
682 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
683 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
684 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
685 }
686
687 /* Fan registers */
688 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
689 /*
690 * Skip reading registers if optional fans are not
691 * present
692 */
693 if (!(data->has_features & HAS_FAN(ix)))
694 continue;
695 data->fan[ix] = dme1737_read(data,
696 DME1737_REG_FAN(ix));
697 data->fan[ix] |= dme1737_read(data,
698 DME1737_REG_FAN(ix) + 1) << 8;
699 data->fan_min[ix] = dme1737_read(data,
700 DME1737_REG_FAN_MIN(ix));
701 data->fan_min[ix] |= dme1737_read(data,
702 DME1737_REG_FAN_MIN(ix) + 1) << 8;
703 data->fan_opt[ix] = dme1737_read(data,
704 DME1737_REG_FAN_OPT(ix));
705 /* fan_max exists only for fan[5-6] */
706 if (ix > 3) {
707 data->fan_max[ix - 4] = dme1737_read(data,
708 DME1737_REG_FAN_MAX(ix));
709 }
710 }
711
712 /* PWM registers */
713 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
714 /*
715 * Skip reading registers if optional PWMs are not
716 * present
717 */
718 if (!(data->has_features & HAS_PWM(ix)))
719 continue;
720 data->pwm[ix] = dme1737_read(data,
721 DME1737_REG_PWM(ix));
722 data->pwm_freq[ix] = dme1737_read(data,
723 DME1737_REG_PWM_FREQ(ix));
724 /* pwm_config and pwm_min exist only for pwm[1-3] */
725 if (ix < 3) {
726 data->pwm_config[ix] = dme1737_read(data,
727 DME1737_REG_PWM_CONFIG(ix));
728 data->pwm_min[ix] = dme1737_read(data,
729 DME1737_REG_PWM_MIN(ix));
730 }
731 }
732 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
733 data->pwm_rr[ix] = dme1737_read(data,
734 DME1737_REG_PWM_RR(ix));
735 }
736
737 /* Thermal zone registers */
738 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
739 /* Skip reading registers if zone3 is not present */
740 if ((ix == 2) && !(data->has_features & HAS_ZONE3))
741 continue;
742 /* sch5127 zone2 registers are special */
743 if ((ix == 1) && (data->type == sch5127)) {
744 data->zone_low[1] = dme1737_read(data,
745 DME1737_REG_ZONE_LOW(2));
746 data->zone_abs[1] = dme1737_read(data,
747 DME1737_REG_ZONE_ABS(2));
748 } else {
749 data->zone_low[ix] = dme1737_read(data,
750 DME1737_REG_ZONE_LOW(ix));
751 data->zone_abs[ix] = dme1737_read(data,
752 DME1737_REG_ZONE_ABS(ix));
753 }
754 }
755 if (data->has_features & HAS_ZONE_HYST) {
756 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
757 data->zone_hyst[ix] = dme1737_read(data,
758 DME1737_REG_ZONE_HYST(ix));
759 }
760 }
761
762 /* Alarm registers */
763 data->alarms = dme1737_read(data,
764 DME1737_REG_ALARM1);
765 /*
766 * Bit 7 tells us if the other alarm registers are non-zero and
767 * therefore also need to be read
768 */
769 if (data->alarms & 0x80) {
770 data->alarms |= dme1737_read(data,
771 DME1737_REG_ALARM2) << 8;
772 data->alarms |= dme1737_read(data,
773 DME1737_REG_ALARM3) << 16;
774 }
775
776 /*
777 * The ISA chips require explicit clearing of alarm bits.
778 * Don't worry, an alarm will come back if the condition
779 * that causes it still exists
780 */
781 if (!data->client) {
782 if (data->alarms & 0xff0000)
783 dme1737_write(data, DME1737_REG_ALARM3, 0xff);
784 if (data->alarms & 0xff00)
785 dme1737_write(data, DME1737_REG_ALARM2, 0xff);
786 if (data->alarms & 0xff)
787 dme1737_write(data, DME1737_REG_ALARM1, 0xff);
788 }
789
790 data->last_update = jiffies;
791 data->valid = 1;
792 }
793
794 mutex_unlock(&data->update_lock);
795
796 return data;
797 }
798
799 /* ---------------------------------------------------------------------
800 * Voltage sysfs attributes
801 * ix = [0-7]
802 * --------------------------------------------------------------------- */
803
804 #define SYS_IN_INPUT 0
805 #define SYS_IN_MIN 1
806 #define SYS_IN_MAX 2
807 #define SYS_IN_ALARM 3
808
809 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
810 char *buf)
811 {
812 struct dme1737_data *data = dme1737_update_device(dev);
813 struct sensor_device_attribute_2
814 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
815 int ix = sensor_attr_2->index;
816 int fn = sensor_attr_2->nr;
817 int res;
818
819 switch (fn) {
820 case SYS_IN_INPUT:
821 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
822 break;
823 case SYS_IN_MIN:
824 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
825 break;
826 case SYS_IN_MAX:
827 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
828 break;
829 case SYS_IN_ALARM:
830 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
831 break;
832 default:
833 res = 0;
834 dev_dbg(dev, "Unknown function %d.\n", fn);
835 }
836
837 return sprintf(buf, "%d\n", res);
838 }
839
840 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
841 const char *buf, size_t count)
842 {
843 struct dme1737_data *data = dev_get_drvdata(dev);
844 struct sensor_device_attribute_2
845 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
846 int ix = sensor_attr_2->index;
847 int fn = sensor_attr_2->nr;
848 long val;
849 int err;
850
851 err = kstrtol(buf, 10, &val);
852 if (err)
853 return err;
854
855 mutex_lock(&data->update_lock);
856 switch (fn) {
857 case SYS_IN_MIN:
858 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
859 dme1737_write(data, DME1737_REG_IN_MIN(ix),
860 data->in_min[ix]);
861 break;
862 case SYS_IN_MAX:
863 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
864 dme1737_write(data, DME1737_REG_IN_MAX(ix),
865 data->in_max[ix]);
866 break;
867 default:
868 dev_dbg(dev, "Unknown function %d.\n", fn);
869 }
870 mutex_unlock(&data->update_lock);
871
872 return count;
873 }
874
875 /* ---------------------------------------------------------------------
876 * Temperature sysfs attributes
877 * ix = [0-2]
878 * --------------------------------------------------------------------- */
879
880 #define SYS_TEMP_INPUT 0
881 #define SYS_TEMP_MIN 1
882 #define SYS_TEMP_MAX 2
883 #define SYS_TEMP_OFFSET 3
884 #define SYS_TEMP_ALARM 4
885 #define SYS_TEMP_FAULT 5
886
887 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
888 char *buf)
889 {
890 struct dme1737_data *data = dme1737_update_device(dev);
891 struct sensor_device_attribute_2
892 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
893 int ix = sensor_attr_2->index;
894 int fn = sensor_attr_2->nr;
895 int res;
896
897 switch (fn) {
898 case SYS_TEMP_INPUT:
899 res = TEMP_FROM_REG(data->temp[ix], 16);
900 break;
901 case SYS_TEMP_MIN:
902 res = TEMP_FROM_REG(data->temp_min[ix], 8);
903 break;
904 case SYS_TEMP_MAX:
905 res = TEMP_FROM_REG(data->temp_max[ix], 8);
906 break;
907 case SYS_TEMP_OFFSET:
908 res = TEMP_FROM_REG(data->temp_offset[ix], 8);
909 break;
910 case SYS_TEMP_ALARM:
911 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
912 break;
913 case SYS_TEMP_FAULT:
914 res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
915 break;
916 default:
917 res = 0;
918 dev_dbg(dev, "Unknown function %d.\n", fn);
919 }
920
921 return sprintf(buf, "%d\n", res);
922 }
923
924 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
925 const char *buf, size_t count)
926 {
927 struct dme1737_data *data = dev_get_drvdata(dev);
928 struct sensor_device_attribute_2
929 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
930 int ix = sensor_attr_2->index;
931 int fn = sensor_attr_2->nr;
932 long val;
933 int err;
934
935 err = kstrtol(buf, 10, &val);
936 if (err)
937 return err;
938
939 mutex_lock(&data->update_lock);
940 switch (fn) {
941 case SYS_TEMP_MIN:
942 data->temp_min[ix] = TEMP_TO_REG(val);
943 dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
944 data->temp_min[ix]);
945 break;
946 case SYS_TEMP_MAX:
947 data->temp_max[ix] = TEMP_TO_REG(val);
948 dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
949 data->temp_max[ix]);
950 break;
951 case SYS_TEMP_OFFSET:
952 data->temp_offset[ix] = TEMP_TO_REG(val);
953 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
954 data->temp_offset[ix]);
955 break;
956 default:
957 dev_dbg(dev, "Unknown function %d.\n", fn);
958 }
959 mutex_unlock(&data->update_lock);
960
961 return count;
962 }
963
964 /* ---------------------------------------------------------------------
965 * Zone sysfs attributes
966 * ix = [0-2]
967 * --------------------------------------------------------------------- */
968
969 #define SYS_ZONE_AUTO_CHANNELS_TEMP 0
970 #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
971 #define SYS_ZONE_AUTO_POINT1_TEMP 2
972 #define SYS_ZONE_AUTO_POINT2_TEMP 3
973 #define SYS_ZONE_AUTO_POINT3_TEMP 4
974
975 static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
976 char *buf)
977 {
978 struct dme1737_data *data = dme1737_update_device(dev);
979 struct sensor_device_attribute_2
980 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
981 int ix = sensor_attr_2->index;
982 int fn = sensor_attr_2->nr;
983 int res;
984
985 switch (fn) {
986 case SYS_ZONE_AUTO_CHANNELS_TEMP:
987 /* check config2 for non-standard temp-to-zone mapping */
988 if ((ix == 1) && (data->config2 & 0x02))
989 res = 4;
990 else
991 res = 1 << ix;
992 break;
993 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
994 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
995 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
996 break;
997 case SYS_ZONE_AUTO_POINT1_TEMP:
998 res = TEMP_FROM_REG(data->zone_low[ix], 8);
999 break;
1000 case SYS_ZONE_AUTO_POINT2_TEMP:
1001 /* pwm_freq holds the temp range bits in the upper nibble */
1002 res = TEMP_FROM_REG(data->zone_low[ix], 8) +
1003 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
1004 break;
1005 case SYS_ZONE_AUTO_POINT3_TEMP:
1006 res = TEMP_FROM_REG(data->zone_abs[ix], 8);
1007 break;
1008 default:
1009 res = 0;
1010 dev_dbg(dev, "Unknown function %d.\n", fn);
1011 }
1012
1013 return sprintf(buf, "%d\n", res);
1014 }
1015
1016 static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
1017 const char *buf, size_t count)
1018 {
1019 struct dme1737_data *data = dev_get_drvdata(dev);
1020 struct sensor_device_attribute_2
1021 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1022 int ix = sensor_attr_2->index;
1023 int fn = sensor_attr_2->nr;
1024 long val;
1025 int err;
1026
1027 err = kstrtol(buf, 10, &val);
1028 if (err)
1029 return err;
1030
1031 mutex_lock(&data->update_lock);
1032 switch (fn) {
1033 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
1034 /* Refresh the cache */
1035 data->zone_low[ix] = dme1737_read(data,
1036 DME1737_REG_ZONE_LOW(ix));
1037 /* Modify the temp hyst value */
1038 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(
1039 TEMP_FROM_REG(data->zone_low[ix], 8) -
1040 val, ix, dme1737_read(data,
1041 DME1737_REG_ZONE_HYST(ix == 2)));
1042 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
1043 data->zone_hyst[ix == 2]);
1044 break;
1045 case SYS_ZONE_AUTO_POINT1_TEMP:
1046 data->zone_low[ix] = TEMP_TO_REG(val);
1047 dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
1048 data->zone_low[ix]);
1049 break;
1050 case SYS_ZONE_AUTO_POINT2_TEMP:
1051 /* Refresh the cache */
1052 data->zone_low[ix] = dme1737_read(data,
1053 DME1737_REG_ZONE_LOW(ix));
1054 /*
1055 * Modify the temp range value (which is stored in the upper
1056 * nibble of the pwm_freq register)
1057 */
1058 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1059 TEMP_FROM_REG(data->zone_low[ix], 8),
1060 dme1737_read(data,
1061 DME1737_REG_PWM_FREQ(ix)));
1062 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
1063 data->pwm_freq[ix]);
1064 break;
1065 case SYS_ZONE_AUTO_POINT3_TEMP:
1066 data->zone_abs[ix] = TEMP_TO_REG(val);
1067 dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
1068 data->zone_abs[ix]);
1069 break;
1070 default:
1071 dev_dbg(dev, "Unknown function %d.\n", fn);
1072 }
1073 mutex_unlock(&data->update_lock);
1074
1075 return count;
1076 }
1077
1078 /* ---------------------------------------------------------------------
1079 * Fan sysfs attributes
1080 * ix = [0-5]
1081 * --------------------------------------------------------------------- */
1082
1083 #define SYS_FAN_INPUT 0
1084 #define SYS_FAN_MIN 1
1085 #define SYS_FAN_MAX 2
1086 #define SYS_FAN_ALARM 3
1087 #define SYS_FAN_TYPE 4
1088
1089 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1090 char *buf)
1091 {
1092 struct dme1737_data *data = dme1737_update_device(dev);
1093 struct sensor_device_attribute_2
1094 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1095 int ix = sensor_attr_2->index;
1096 int fn = sensor_attr_2->nr;
1097 int res;
1098
1099 switch (fn) {
1100 case SYS_FAN_INPUT:
1101 res = FAN_FROM_REG(data->fan[ix],
1102 ix < 4 ? 0 :
1103 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1104 break;
1105 case SYS_FAN_MIN:
1106 res = FAN_FROM_REG(data->fan_min[ix],
1107 ix < 4 ? 0 :
1108 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1109 break;
1110 case SYS_FAN_MAX:
1111 /* only valid for fan[5-6] */
1112 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
1113 break;
1114 case SYS_FAN_ALARM:
1115 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
1116 break;
1117 case SYS_FAN_TYPE:
1118 /* only valid for fan[1-4] */
1119 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
1120 break;
1121 default:
1122 res = 0;
1123 dev_dbg(dev, "Unknown function %d.\n", fn);
1124 }
1125
1126 return sprintf(buf, "%d\n", res);
1127 }
1128
1129 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1130 const char *buf, size_t count)
1131 {
1132 struct dme1737_data *data = dev_get_drvdata(dev);
1133 struct sensor_device_attribute_2
1134 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1135 int ix = sensor_attr_2->index;
1136 int fn = sensor_attr_2->nr;
1137 long val;
1138 int err;
1139
1140 err = kstrtol(buf, 10, &val);
1141 if (err)
1142 return err;
1143
1144 mutex_lock(&data->update_lock);
1145 switch (fn) {
1146 case SYS_FAN_MIN:
1147 if (ix < 4) {
1148 data->fan_min[ix] = FAN_TO_REG(val, 0);
1149 } else {
1150 /* Refresh the cache */
1151 data->fan_opt[ix] = dme1737_read(data,
1152 DME1737_REG_FAN_OPT(ix));
1153 /* Modify the fan min value */
1154 data->fan_min[ix] = FAN_TO_REG(val,
1155 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1156 }
1157 dme1737_write(data, DME1737_REG_FAN_MIN(ix),
1158 data->fan_min[ix] & 0xff);
1159 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
1160 data->fan_min[ix] >> 8);
1161 break;
1162 case SYS_FAN_MAX:
1163 /* Only valid for fan[5-6] */
1164 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
1165 dme1737_write(data, DME1737_REG_FAN_MAX(ix),
1166 data->fan_max[ix - 4]);
1167 break;
1168 case SYS_FAN_TYPE:
1169 /* Only valid for fan[1-4] */
1170 if (!(val == 1 || val == 2 || val == 4)) {
1171 count = -EINVAL;
1172 dev_warn(dev,
1173 "Fan type value %ld not supported. Choose one of 1, 2, or 4.\n",
1174 val);
1175 goto exit;
1176 }
1177 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
1178 DME1737_REG_FAN_OPT(ix)));
1179 dme1737_write(data, DME1737_REG_FAN_OPT(ix),
1180 data->fan_opt[ix]);
1181 break;
1182 default:
1183 dev_dbg(dev, "Unknown function %d.\n", fn);
1184 }
1185 exit:
1186 mutex_unlock(&data->update_lock);
1187
1188 return count;
1189 }
1190
1191 /* ---------------------------------------------------------------------
1192 * PWM sysfs attributes
1193 * ix = [0-4]
1194 * --------------------------------------------------------------------- */
1195
1196 #define SYS_PWM 0
1197 #define SYS_PWM_FREQ 1
1198 #define SYS_PWM_ENABLE 2
1199 #define SYS_PWM_RAMP_RATE 3
1200 #define SYS_PWM_AUTO_CHANNELS_ZONE 4
1201 #define SYS_PWM_AUTO_PWM_MIN 5
1202 #define SYS_PWM_AUTO_POINT1_PWM 6
1203 #define SYS_PWM_AUTO_POINT2_PWM 7
1204
1205 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1206 char *buf)
1207 {
1208 struct dme1737_data *data = dme1737_update_device(dev);
1209 struct sensor_device_attribute_2
1210 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1211 int ix = sensor_attr_2->index;
1212 int fn = sensor_attr_2->nr;
1213 int res;
1214
1215 switch (fn) {
1216 case SYS_PWM:
1217 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0)
1218 res = 255;
1219 else
1220 res = data->pwm[ix];
1221 break;
1222 case SYS_PWM_FREQ:
1223 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1224 break;
1225 case SYS_PWM_ENABLE:
1226 if (ix >= 3)
1227 res = 1; /* pwm[5-6] hard-wired to manual mode */
1228 else
1229 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
1230 break;
1231 case SYS_PWM_RAMP_RATE:
1232 /* Only valid for pwm[1-3] */
1233 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
1234 break;
1235 case SYS_PWM_AUTO_CHANNELS_ZONE:
1236 /* Only valid for pwm[1-3] */
1237 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2)
1238 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
1239 else
1240 res = data->pwm_acz[ix];
1241 break;
1242 case SYS_PWM_AUTO_PWM_MIN:
1243 /* Only valid for pwm[1-3] */
1244 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix))
1245 res = data->pwm_min[ix];
1246 else
1247 res = 0;
1248 break;
1249 case SYS_PWM_AUTO_POINT1_PWM:
1250 /* Only valid for pwm[1-3] */
1251 res = data->pwm_min[ix];
1252 break;
1253 case SYS_PWM_AUTO_POINT2_PWM:
1254 /* Only valid for pwm[1-3] */
1255 res = 255; /* hard-wired */
1256 break;
1257 default:
1258 res = 0;
1259 dev_dbg(dev, "Unknown function %d.\n", fn);
1260 }
1261
1262 return sprintf(buf, "%d\n", res);
1263 }
1264
1265 static struct attribute *dme1737_pwm_chmod_attr[];
1266 static void dme1737_chmod_file(struct device*, struct attribute*, umode_t);
1267
1268 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1269 const char *buf, size_t count)
1270 {
1271 struct dme1737_data *data = dev_get_drvdata(dev);
1272 struct sensor_device_attribute_2
1273 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1274 int ix = sensor_attr_2->index;
1275 int fn = sensor_attr_2->nr;
1276 long val;
1277 int err;
1278
1279 err = kstrtol(buf, 10, &val);
1280 if (err)
1281 return err;
1282
1283 mutex_lock(&data->update_lock);
1284 switch (fn) {
1285 case SYS_PWM:
1286 data->pwm[ix] = clamp_val(val, 0, 255);
1287 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
1288 break;
1289 case SYS_PWM_FREQ:
1290 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
1291 DME1737_REG_PWM_FREQ(ix)));
1292 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
1293 data->pwm_freq[ix]);
1294 break;
1295 case SYS_PWM_ENABLE:
1296 /* Only valid for pwm[1-3] */
1297 if (val < 0 || val > 2) {
1298 count = -EINVAL;
1299 dev_warn(dev,
1300 "PWM enable %ld not supported. Choose one of 0, 1, or 2.\n",
1301 val);
1302 goto exit;
1303 }
1304 /* Refresh the cache */
1305 data->pwm_config[ix] = dme1737_read(data,
1306 DME1737_REG_PWM_CONFIG(ix));
1307 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
1308 /* Bail out if no change */
1309 goto exit;
1310 }
1311 /* Do some housekeeping if we are currently in auto mode */
1312 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1313 /* Save the current zone channel assignment */
1314 data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
1315 data->pwm_config[ix]);
1316 /* Save the current ramp rate state and disable it */
1317 data->pwm_rr[ix > 0] = dme1737_read(data,
1318 DME1737_REG_PWM_RR(ix > 0));
1319 data->pwm_rr_en &= ~(1 << ix);
1320 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
1321 data->pwm_rr_en |= (1 << ix);
1322 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
1323 data->pwm_rr[ix > 0]);
1324 dme1737_write(data,
1325 DME1737_REG_PWM_RR(ix > 0),
1326 data->pwm_rr[ix > 0]);
1327 }
1328 }
1329 /* Set the new PWM mode */
1330 switch (val) {
1331 case 0:
1332 /* Change permissions of pwm[ix] to read-only */
1333 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1334 S_IRUGO);
1335 /* Turn fan fully on */
1336 data->pwm_config[ix] = PWM_EN_TO_REG(0,
1337 data->pwm_config[ix]);
1338 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1339 data->pwm_config[ix]);
1340 break;
1341 case 1:
1342 /* Turn on manual mode */
1343 data->pwm_config[ix] = PWM_EN_TO_REG(1,
1344 data->pwm_config[ix]);
1345 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1346 data->pwm_config[ix]);
1347 /* Change permissions of pwm[ix] to read-writeable */
1348 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1349 S_IRUGO | S_IWUSR);
1350 break;
1351 case 2:
1352 /* Change permissions of pwm[ix] to read-only */
1353 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1354 S_IRUGO);
1355 /*
1356 * Turn on auto mode using the saved zone channel
1357 * assignment
1358 */
1359 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1360 data->pwm_acz[ix],
1361 data->pwm_config[ix]);
1362 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1363 data->pwm_config[ix]);
1364 /* Enable PWM ramp rate if previously enabled */
1365 if (data->pwm_rr_en & (1 << ix)) {
1366 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
1367 dme1737_read(data,
1368 DME1737_REG_PWM_RR(ix > 0)));
1369 dme1737_write(data,
1370 DME1737_REG_PWM_RR(ix > 0),
1371 data->pwm_rr[ix > 0]);
1372 }
1373 break;
1374 }
1375 break;
1376 case SYS_PWM_RAMP_RATE:
1377 /* Only valid for pwm[1-3] */
1378 /* Refresh the cache */
1379 data->pwm_config[ix] = dme1737_read(data,
1380 DME1737_REG_PWM_CONFIG(ix));
1381 data->pwm_rr[ix > 0] = dme1737_read(data,
1382 DME1737_REG_PWM_RR(ix > 0));
1383 /* Set the ramp rate value */
1384 if (val > 0) {
1385 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1386 data->pwm_rr[ix > 0]);
1387 }
1388 /*
1389 * Enable/disable the feature only if the associated PWM
1390 * output is in automatic mode.
1391 */
1392 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1393 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1394 data->pwm_rr[ix > 0]);
1395 }
1396 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
1397 data->pwm_rr[ix > 0]);
1398 break;
1399 case SYS_PWM_AUTO_CHANNELS_ZONE:
1400 /* Only valid for pwm[1-3] */
1401 if (!(val == 1 || val == 2 || val == 4 ||
1402 val == 6 || val == 7)) {
1403 count = -EINVAL;
1404 dev_warn(dev,
1405 "PWM auto channels zone %ld not supported. Choose one of 1, 2, 4, 6, "
1406 "or 7.\n", val);
1407 goto exit;
1408 }
1409 /* Refresh the cache */
1410 data->pwm_config[ix] = dme1737_read(data,
1411 DME1737_REG_PWM_CONFIG(ix));
1412 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1413 /*
1414 * PWM is already in auto mode so update the temp
1415 * channel assignment
1416 */
1417 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1418 data->pwm_config[ix]);
1419 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1420 data->pwm_config[ix]);
1421 } else {
1422 /*
1423 * PWM is not in auto mode so we save the temp
1424 * channel assignment for later use
1425 */
1426 data->pwm_acz[ix] = val;
1427 }
1428 break;
1429 case SYS_PWM_AUTO_PWM_MIN:
1430 /* Only valid for pwm[1-3] */
1431 /* Refresh the cache */
1432 data->pwm_min[ix] = dme1737_read(data,
1433 DME1737_REG_PWM_MIN(ix));
1434 /*
1435 * There are only 2 values supported for the auto_pwm_min
1436 * value: 0 or auto_point1_pwm. So if the temperature drops
1437 * below the auto_point1_temp_hyst value, the fan either turns
1438 * off or runs at auto_point1_pwm duty-cycle.
1439 */
1440 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1441 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
1442 dme1737_read(data,
1443 DME1737_REG_PWM_RR(0)));
1444 } else {
1445 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
1446 dme1737_read(data,
1447 DME1737_REG_PWM_RR(0)));
1448 }
1449 dme1737_write(data, DME1737_REG_PWM_RR(0),
1450 data->pwm_rr[0]);
1451 break;
1452 case SYS_PWM_AUTO_POINT1_PWM:
1453 /* Only valid for pwm[1-3] */
1454 data->pwm_min[ix] = clamp_val(val, 0, 255);
1455 dme1737_write(data, DME1737_REG_PWM_MIN(ix),
1456 data->pwm_min[ix]);
1457 break;
1458 default:
1459 dev_dbg(dev, "Unknown function %d.\n", fn);
1460 }
1461 exit:
1462 mutex_unlock(&data->update_lock);
1463
1464 return count;
1465 }
1466
1467 /* ---------------------------------------------------------------------
1468 * Miscellaneous sysfs attributes
1469 * --------------------------------------------------------------------- */
1470
1471 static ssize_t show_vrm(struct device *dev, struct device_attribute *attr,
1472 char *buf)
1473 {
1474 struct i2c_client *client = to_i2c_client(dev);
1475 struct dme1737_data *data = i2c_get_clientdata(client);
1476
1477 return sprintf(buf, "%d\n", data->vrm);
1478 }
1479
1480 static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1481 const char *buf, size_t count)
1482 {
1483 struct dme1737_data *data = dev_get_drvdata(dev);
1484 long val;
1485 int err;
1486
1487 err = kstrtol(buf, 10, &val);
1488 if (err)
1489 return err;
1490
1491 data->vrm = val;
1492 return count;
1493 }
1494
1495 static ssize_t show_vid(struct device *dev, struct device_attribute *attr,
1496 char *buf)
1497 {
1498 struct dme1737_data *data = dme1737_update_device(dev);
1499
1500 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1501 }
1502
1503 static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1504 char *buf)
1505 {
1506 struct dme1737_data *data = dev_get_drvdata(dev);
1507
1508 return sprintf(buf, "%s\n", data->name);
1509 }
1510
1511 /* ---------------------------------------------------------------------
1512 * Sysfs device attribute defines and structs
1513 * --------------------------------------------------------------------- */
1514
1515 /* Voltages 0-7 */
1516
1517 #define SENSOR_DEVICE_ATTR_IN(ix) \
1518 static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
1519 show_in, NULL, SYS_IN_INPUT, ix); \
1520 static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
1521 show_in, set_in, SYS_IN_MIN, ix); \
1522 static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
1523 show_in, set_in, SYS_IN_MAX, ix); \
1524 static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
1525 show_in, NULL, SYS_IN_ALARM, ix)
1526
1527 SENSOR_DEVICE_ATTR_IN(0);
1528 SENSOR_DEVICE_ATTR_IN(1);
1529 SENSOR_DEVICE_ATTR_IN(2);
1530 SENSOR_DEVICE_ATTR_IN(3);
1531 SENSOR_DEVICE_ATTR_IN(4);
1532 SENSOR_DEVICE_ATTR_IN(5);
1533 SENSOR_DEVICE_ATTR_IN(6);
1534 SENSOR_DEVICE_ATTR_IN(7);
1535
1536 /* Temperatures 1-3 */
1537
1538 #define SENSOR_DEVICE_ATTR_TEMP(ix) \
1539 static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
1540 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
1541 static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
1542 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
1543 static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
1544 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
1545 static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
1546 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
1547 static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
1548 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
1549 static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
1550 show_temp, NULL, SYS_TEMP_FAULT, ix-1)
1551
1552 SENSOR_DEVICE_ATTR_TEMP(1);
1553 SENSOR_DEVICE_ATTR_TEMP(2);
1554 SENSOR_DEVICE_ATTR_TEMP(3);
1555
1556 /* Zones 1-3 */
1557
1558 #define SENSOR_DEVICE_ATTR_ZONE(ix) \
1559 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
1560 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
1561 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
1562 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
1563 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
1564 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
1565 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
1566 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
1567 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
1568 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
1569
1570 SENSOR_DEVICE_ATTR_ZONE(1);
1571 SENSOR_DEVICE_ATTR_ZONE(2);
1572 SENSOR_DEVICE_ATTR_ZONE(3);
1573
1574 /* Fans 1-4 */
1575
1576 #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
1577 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1578 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1579 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1580 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1581 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1582 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1583 static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
1584 show_fan, set_fan, SYS_FAN_TYPE, ix-1)
1585
1586 SENSOR_DEVICE_ATTR_FAN_1TO4(1);
1587 SENSOR_DEVICE_ATTR_FAN_1TO4(2);
1588 SENSOR_DEVICE_ATTR_FAN_1TO4(3);
1589 SENSOR_DEVICE_ATTR_FAN_1TO4(4);
1590
1591 /* Fans 5-6 */
1592
1593 #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
1594 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1595 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1596 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1597 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1598 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1599 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1600 static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
1601 show_fan, set_fan, SYS_FAN_MAX, ix-1)
1602
1603 SENSOR_DEVICE_ATTR_FAN_5TO6(5);
1604 SENSOR_DEVICE_ATTR_FAN_5TO6(6);
1605
1606 /* PWMs 1-3 */
1607
1608 #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
1609 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1610 show_pwm, set_pwm, SYS_PWM, ix-1); \
1611 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1612 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1613 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1614 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
1615 static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
1616 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
1617 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
1618 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
1619 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
1620 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
1621 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
1622 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
1623 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
1624 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
1625
1626 SENSOR_DEVICE_ATTR_PWM_1TO3(1);
1627 SENSOR_DEVICE_ATTR_PWM_1TO3(2);
1628 SENSOR_DEVICE_ATTR_PWM_1TO3(3);
1629
1630 /* PWMs 5-6 */
1631
1632 #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
1633 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1634 show_pwm, set_pwm, SYS_PWM, ix-1); \
1635 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1636 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1637 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1638 show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
1639
1640 SENSOR_DEVICE_ATTR_PWM_5TO6(5);
1641 SENSOR_DEVICE_ATTR_PWM_5TO6(6);
1642
1643 /* Misc */
1644
1645 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1646 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1647 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
1648
1649 /*
1650 * This struct holds all the attributes that are always present and need to be
1651 * created unconditionally. The attributes that need modification of their
1652 * permissions are created read-only and write permissions are added or removed
1653 * on the fly when required
1654 */
1655 static struct attribute *dme1737_attr[] = {
1656 /* Voltages */
1657 &sensor_dev_attr_in0_input.dev_attr.attr,
1658 &sensor_dev_attr_in0_min.dev_attr.attr,
1659 &sensor_dev_attr_in0_max.dev_attr.attr,
1660 &sensor_dev_attr_in0_alarm.dev_attr.attr,
1661 &sensor_dev_attr_in1_input.dev_attr.attr,
1662 &sensor_dev_attr_in1_min.dev_attr.attr,
1663 &sensor_dev_attr_in1_max.dev_attr.attr,
1664 &sensor_dev_attr_in1_alarm.dev_attr.attr,
1665 &sensor_dev_attr_in2_input.dev_attr.attr,
1666 &sensor_dev_attr_in2_min.dev_attr.attr,
1667 &sensor_dev_attr_in2_max.dev_attr.attr,
1668 &sensor_dev_attr_in2_alarm.dev_attr.attr,
1669 &sensor_dev_attr_in3_input.dev_attr.attr,
1670 &sensor_dev_attr_in3_min.dev_attr.attr,
1671 &sensor_dev_attr_in3_max.dev_attr.attr,
1672 &sensor_dev_attr_in3_alarm.dev_attr.attr,
1673 &sensor_dev_attr_in4_input.dev_attr.attr,
1674 &sensor_dev_attr_in4_min.dev_attr.attr,
1675 &sensor_dev_attr_in4_max.dev_attr.attr,
1676 &sensor_dev_attr_in4_alarm.dev_attr.attr,
1677 &sensor_dev_attr_in5_input.dev_attr.attr,
1678 &sensor_dev_attr_in5_min.dev_attr.attr,
1679 &sensor_dev_attr_in5_max.dev_attr.attr,
1680 &sensor_dev_attr_in5_alarm.dev_attr.attr,
1681 &sensor_dev_attr_in6_input.dev_attr.attr,
1682 &sensor_dev_attr_in6_min.dev_attr.attr,
1683 &sensor_dev_attr_in6_max.dev_attr.attr,
1684 &sensor_dev_attr_in6_alarm.dev_attr.attr,
1685 /* Temperatures */
1686 &sensor_dev_attr_temp1_input.dev_attr.attr,
1687 &sensor_dev_attr_temp1_min.dev_attr.attr,
1688 &sensor_dev_attr_temp1_max.dev_attr.attr,
1689 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
1690 &sensor_dev_attr_temp1_fault.dev_attr.attr,
1691 &sensor_dev_attr_temp2_input.dev_attr.attr,
1692 &sensor_dev_attr_temp2_min.dev_attr.attr,
1693 &sensor_dev_attr_temp2_max.dev_attr.attr,
1694 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
1695 &sensor_dev_attr_temp2_fault.dev_attr.attr,
1696 &sensor_dev_attr_temp3_input.dev_attr.attr,
1697 &sensor_dev_attr_temp3_min.dev_attr.attr,
1698 &sensor_dev_attr_temp3_max.dev_attr.attr,
1699 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1700 &sensor_dev_attr_temp3_fault.dev_attr.attr,
1701 /* Zones */
1702 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1703 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1704 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1705 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
1706 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1707 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1708 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1709 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
1710 NULL
1711 };
1712
1713 static const struct attribute_group dme1737_group = {
1714 .attrs = dme1737_attr,
1715 };
1716
1717 /*
1718 * The following struct holds temp offset attributes, which are not available
1719 * in all chips. The following chips support them:
1720 * DME1737, SCH311x
1721 */
1722 static struct attribute *dme1737_temp_offset_attr[] = {
1723 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1724 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1725 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1726 NULL
1727 };
1728
1729 static const struct attribute_group dme1737_temp_offset_group = {
1730 .attrs = dme1737_temp_offset_attr,
1731 };
1732
1733 /*
1734 * The following struct holds VID related attributes, which are not available
1735 * in all chips. The following chips support them:
1736 * DME1737
1737 */
1738 static struct attribute *dme1737_vid_attr[] = {
1739 &dev_attr_vrm.attr,
1740 &dev_attr_cpu0_vid.attr,
1741 NULL
1742 };
1743
1744 static const struct attribute_group dme1737_vid_group = {
1745 .attrs = dme1737_vid_attr,
1746 };
1747
1748 /*
1749 * The following struct holds temp zone 3 related attributes, which are not
1750 * available in all chips. The following chips support them:
1751 * DME1737, SCH311x, SCH5027
1752 */
1753 static struct attribute *dme1737_zone3_attr[] = {
1754 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1755 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1756 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1757 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
1758 NULL
1759 };
1760
1761 static const struct attribute_group dme1737_zone3_group = {
1762 .attrs = dme1737_zone3_attr,
1763 };
1764
1765
1766 /*
1767 * The following struct holds temp zone hysteresis related attributes, which
1768 * are not available in all chips. The following chips support them:
1769 * DME1737, SCH311x
1770 */
1771 static struct attribute *dme1737_zone_hyst_attr[] = {
1772 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1773 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1774 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
1775 NULL
1776 };
1777
1778 static const struct attribute_group dme1737_zone_hyst_group = {
1779 .attrs = dme1737_zone_hyst_attr,
1780 };
1781
1782 /*
1783 * The following struct holds voltage in7 related attributes, which
1784 * are not available in all chips. The following chips support them:
1785 * SCH5127
1786 */
1787 static struct attribute *dme1737_in7_attr[] = {
1788 &sensor_dev_attr_in7_input.dev_attr.attr,
1789 &sensor_dev_attr_in7_min.dev_attr.attr,
1790 &sensor_dev_attr_in7_max.dev_attr.attr,
1791 &sensor_dev_attr_in7_alarm.dev_attr.attr,
1792 NULL
1793 };
1794
1795 static const struct attribute_group dme1737_in7_group = {
1796 .attrs = dme1737_in7_attr,
1797 };
1798
1799 /*
1800 * The following structs hold the PWM attributes, some of which are optional.
1801 * Their creation depends on the chip configuration which is determined during
1802 * module load.
1803 */
1804 static struct attribute *dme1737_pwm1_attr[] = {
1805 &sensor_dev_attr_pwm1.dev_attr.attr,
1806 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1807 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1808 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1809 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1810 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1811 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1812 NULL
1813 };
1814 static struct attribute *dme1737_pwm2_attr[] = {
1815 &sensor_dev_attr_pwm2.dev_attr.attr,
1816 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1817 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1818 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1819 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1820 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1821 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1822 NULL
1823 };
1824 static struct attribute *dme1737_pwm3_attr[] = {
1825 &sensor_dev_attr_pwm3.dev_attr.attr,
1826 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1827 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1828 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1829 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1830 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1831 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1832 NULL
1833 };
1834 static struct attribute *dme1737_pwm5_attr[] = {
1835 &sensor_dev_attr_pwm5.dev_attr.attr,
1836 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1837 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
1838 NULL
1839 };
1840 static struct attribute *dme1737_pwm6_attr[] = {
1841 &sensor_dev_attr_pwm6.dev_attr.attr,
1842 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1843 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
1844 NULL
1845 };
1846
1847 static const struct attribute_group dme1737_pwm_group[] = {
1848 { .attrs = dme1737_pwm1_attr },
1849 { .attrs = dme1737_pwm2_attr },
1850 { .attrs = dme1737_pwm3_attr },
1851 { .attrs = NULL },
1852 { .attrs = dme1737_pwm5_attr },
1853 { .attrs = dme1737_pwm6_attr },
1854 };
1855
1856 /*
1857 * The following struct holds auto PWM min attributes, which are not available
1858 * in all chips. Their creation depends on the chip type which is determined
1859 * during module load.
1860 */
1861 static struct attribute *dme1737_auto_pwm_min_attr[] = {
1862 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1863 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1864 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1865 };
1866
1867 /*
1868 * The following structs hold the fan attributes, some of which are optional.
1869 * Their creation depends on the chip configuration which is determined during
1870 * module load.
1871 */
1872 static struct attribute *dme1737_fan1_attr[] = {
1873 &sensor_dev_attr_fan1_input.dev_attr.attr,
1874 &sensor_dev_attr_fan1_min.dev_attr.attr,
1875 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1876 &sensor_dev_attr_fan1_type.dev_attr.attr,
1877 NULL
1878 };
1879 static struct attribute *dme1737_fan2_attr[] = {
1880 &sensor_dev_attr_fan2_input.dev_attr.attr,
1881 &sensor_dev_attr_fan2_min.dev_attr.attr,
1882 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1883 &sensor_dev_attr_fan2_type.dev_attr.attr,
1884 NULL
1885 };
1886 static struct attribute *dme1737_fan3_attr[] = {
1887 &sensor_dev_attr_fan3_input.dev_attr.attr,
1888 &sensor_dev_attr_fan3_min.dev_attr.attr,
1889 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1890 &sensor_dev_attr_fan3_type.dev_attr.attr,
1891 NULL
1892 };
1893 static struct attribute *dme1737_fan4_attr[] = {
1894 &sensor_dev_attr_fan4_input.dev_attr.attr,
1895 &sensor_dev_attr_fan4_min.dev_attr.attr,
1896 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1897 &sensor_dev_attr_fan4_type.dev_attr.attr,
1898 NULL
1899 };
1900 static struct attribute *dme1737_fan5_attr[] = {
1901 &sensor_dev_attr_fan5_input.dev_attr.attr,
1902 &sensor_dev_attr_fan5_min.dev_attr.attr,
1903 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1904 &sensor_dev_attr_fan5_max.dev_attr.attr,
1905 NULL
1906 };
1907 static struct attribute *dme1737_fan6_attr[] = {
1908 &sensor_dev_attr_fan6_input.dev_attr.attr,
1909 &sensor_dev_attr_fan6_min.dev_attr.attr,
1910 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
1911 &sensor_dev_attr_fan6_max.dev_attr.attr,
1912 NULL
1913 };
1914
1915 static const struct attribute_group dme1737_fan_group[] = {
1916 { .attrs = dme1737_fan1_attr },
1917 { .attrs = dme1737_fan2_attr },
1918 { .attrs = dme1737_fan3_attr },
1919 { .attrs = dme1737_fan4_attr },
1920 { .attrs = dme1737_fan5_attr },
1921 { .attrs = dme1737_fan6_attr },
1922 };
1923
1924 /*
1925 * The permissions of the following zone attributes are changed to read-
1926 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1927 */
1928 static struct attribute *dme1737_zone_chmod_attr[] = {
1929 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1930 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1931 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1932 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1933 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1934 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1935 NULL
1936 };
1937
1938 static const struct attribute_group dme1737_zone_chmod_group = {
1939 .attrs = dme1737_zone_chmod_attr,
1940 };
1941
1942
1943 /*
1944 * The permissions of the following zone 3 attributes are changed to read-
1945 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1946 */
1947 static struct attribute *dme1737_zone3_chmod_attr[] = {
1948 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1949 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1950 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1951 NULL
1952 };
1953
1954 static const struct attribute_group dme1737_zone3_chmod_group = {
1955 .attrs = dme1737_zone3_chmod_attr,
1956 };
1957
1958 /*
1959 * The permissions of the following PWM attributes are changed to read-
1960 * writeable if the chip is *not* locked and the respective PWM is available.
1961 * Otherwise they stay read-only.
1962 */
1963 static struct attribute *dme1737_pwm1_chmod_attr[] = {
1964 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1965 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1966 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1967 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1968 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1969 NULL
1970 };
1971 static struct attribute *dme1737_pwm2_chmod_attr[] = {
1972 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1973 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1974 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1975 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1976 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1977 NULL
1978 };
1979 static struct attribute *dme1737_pwm3_chmod_attr[] = {
1980 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1981 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1982 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1983 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1984 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1985 NULL
1986 };
1987 static struct attribute *dme1737_pwm5_chmod_attr[] = {
1988 &sensor_dev_attr_pwm5.dev_attr.attr,
1989 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1990 NULL
1991 };
1992 static struct attribute *dme1737_pwm6_chmod_attr[] = {
1993 &sensor_dev_attr_pwm6.dev_attr.attr,
1994 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1995 NULL
1996 };
1997
1998 static const struct attribute_group dme1737_pwm_chmod_group[] = {
1999 { .attrs = dme1737_pwm1_chmod_attr },
2000 { .attrs = dme1737_pwm2_chmod_attr },
2001 { .attrs = dme1737_pwm3_chmod_attr },
2002 { .attrs = NULL },
2003 { .attrs = dme1737_pwm5_chmod_attr },
2004 { .attrs = dme1737_pwm6_chmod_attr },
2005 };
2006
2007 /*
2008 * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
2009 * chip is not locked. Otherwise they are read-only.
2010 */
2011 static struct attribute *dme1737_pwm_chmod_attr[] = {
2012 &sensor_dev_attr_pwm1.dev_attr.attr,
2013 &sensor_dev_attr_pwm2.dev_attr.attr,
2014 &sensor_dev_attr_pwm3.dev_attr.attr,
2015 };
2016
2017 /* ---------------------------------------------------------------------
2018 * Super-IO functions
2019 * --------------------------------------------------------------------- */
2020
2021 static inline void dme1737_sio_enter(int sio_cip)
2022 {
2023 outb(0x55, sio_cip);
2024 }
2025
2026 static inline void dme1737_sio_exit(int sio_cip)
2027 {
2028 outb(0xaa, sio_cip);
2029 }
2030
2031 static inline int dme1737_sio_inb(int sio_cip, int reg)
2032 {
2033 outb(reg, sio_cip);
2034 return inb(sio_cip + 1);
2035 }
2036
2037 static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
2038 {
2039 outb(reg, sio_cip);
2040 outb(val, sio_cip + 1);
2041 }
2042
2043 /* ---------------------------------------------------------------------
2044 * Device initialization
2045 * --------------------------------------------------------------------- */
2046
2047 static int dme1737_i2c_get_features(int, struct dme1737_data*);
2048
2049 static void dme1737_chmod_file(struct device *dev,
2050 struct attribute *attr, umode_t mode)
2051 {
2052 if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
2053 dev_warn(dev, "Failed to change permissions of %s.\n",
2054 attr->name);
2055 }
2056 }
2057
2058 static void dme1737_chmod_group(struct device *dev,
2059 const struct attribute_group *group,
2060 umode_t mode)
2061 {
2062 struct attribute **attr;
2063
2064 for (attr = group->attrs; *attr; attr++)
2065 dme1737_chmod_file(dev, *attr, mode);
2066 }
2067
2068 static void dme1737_remove_files(struct device *dev)
2069 {
2070 struct dme1737_data *data = dev_get_drvdata(dev);
2071 int ix;
2072
2073 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
2074 if (data->has_features & HAS_FAN(ix)) {
2075 sysfs_remove_group(&dev->kobj,
2076 &dme1737_fan_group[ix]);
2077 }
2078 }
2079
2080 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
2081 if (data->has_features & HAS_PWM(ix)) {
2082 sysfs_remove_group(&dev->kobj,
2083 &dme1737_pwm_group[ix]);
2084 if ((data->has_features & HAS_PWM_MIN) && ix < 3) {
2085 sysfs_remove_file(&dev->kobj,
2086 dme1737_auto_pwm_min_attr[ix]);
2087 }
2088 }
2089 }
2090
2091 if (data->has_features & HAS_TEMP_OFFSET)
2092 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
2093 if (data->has_features & HAS_VID)
2094 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
2095 if (data->has_features & HAS_ZONE3)
2096 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
2097 if (data->has_features & HAS_ZONE_HYST)
2098 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
2099 if (data->has_features & HAS_IN7)
2100 sysfs_remove_group(&dev->kobj, &dme1737_in7_group);
2101 sysfs_remove_group(&dev->kobj, &dme1737_group);
2102
2103 if (!data->client)
2104 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
2105 }
2106
2107 static int dme1737_create_files(struct device *dev)
2108 {
2109 struct dme1737_data *data = dev_get_drvdata(dev);
2110 int err, ix;
2111
2112 /* Create a name attribute for ISA devices */
2113 if (!data->client) {
2114 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr);
2115 if (err)
2116 goto exit;
2117 }
2118
2119 /* Create standard sysfs attributes */
2120 err = sysfs_create_group(&dev->kobj, &dme1737_group);
2121 if (err)
2122 goto exit_remove;
2123
2124 /* Create chip-dependent sysfs attributes */
2125 if (data->has_features & HAS_TEMP_OFFSET) {
2126 err = sysfs_create_group(&dev->kobj,
2127 &dme1737_temp_offset_group);
2128 if (err)
2129 goto exit_remove;
2130 }
2131 if (data->has_features & HAS_VID) {
2132 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group);
2133 if (err)
2134 goto exit_remove;
2135 }
2136 if (data->has_features & HAS_ZONE3) {
2137 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group);
2138 if (err)
2139 goto exit_remove;
2140 }
2141 if (data->has_features & HAS_ZONE_HYST) {
2142 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group);
2143 if (err)
2144 goto exit_remove;
2145 }
2146 if (data->has_features & HAS_IN7) {
2147 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group);
2148 if (err)
2149 goto exit_remove;
2150 }
2151
2152 /* Create fan sysfs attributes */
2153 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
2154 if (data->has_features & HAS_FAN(ix)) {
2155 err = sysfs_create_group(&dev->kobj,
2156 &dme1737_fan_group[ix]);
2157 if (err)
2158 goto exit_remove;
2159 }
2160 }
2161
2162 /* Create PWM sysfs attributes */
2163 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
2164 if (data->has_features & HAS_PWM(ix)) {
2165 err = sysfs_create_group(&dev->kobj,
2166 &dme1737_pwm_group[ix]);
2167 if (err)
2168 goto exit_remove;
2169 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) {
2170 err = sysfs_create_file(&dev->kobj,
2171 dme1737_auto_pwm_min_attr[ix]);
2172 if (err)
2173 goto exit_remove;
2174 }
2175 }
2176 }
2177
2178 /*
2179 * Inform if the device is locked. Otherwise change the permissions of
2180 * selected attributes from read-only to read-writeable.
2181 */
2182 if (data->config & 0x02) {
2183 dev_info(dev,
2184 "Device is locked. Some attributes will be read-only.\n");
2185 } else {
2186 /* Change permissions of zone sysfs attributes */
2187 dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
2188 S_IRUGO | S_IWUSR);
2189
2190 /* Change permissions of chip-dependent sysfs attributes */
2191 if (data->has_features & HAS_TEMP_OFFSET) {
2192 dme1737_chmod_group(dev, &dme1737_temp_offset_group,
2193 S_IRUGO | S_IWUSR);
2194 }
2195 if (data->has_features & HAS_ZONE3) {
2196 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group,
2197 S_IRUGO | S_IWUSR);
2198 }
2199 if (data->has_features & HAS_ZONE_HYST) {
2200 dme1737_chmod_group(dev, &dme1737_zone_hyst_group,
2201 S_IRUGO | S_IWUSR);
2202 }
2203
2204 /* Change permissions of PWM sysfs attributes */
2205 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
2206 if (data->has_features & HAS_PWM(ix)) {
2207 dme1737_chmod_group(dev,
2208 &dme1737_pwm_chmod_group[ix],
2209 S_IRUGO | S_IWUSR);
2210 if ((data->has_features & HAS_PWM_MIN) &&
2211 ix < 3) {
2212 dme1737_chmod_file(dev,
2213 dme1737_auto_pwm_min_attr[ix],
2214 S_IRUGO | S_IWUSR);
2215 }
2216 }
2217 }
2218
2219 /* Change permissions of pwm[1-3] if in manual mode */
2220 for (ix = 0; ix < 3; ix++) {
2221 if ((data->has_features & HAS_PWM(ix)) &&
2222 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
2223 dme1737_chmod_file(dev,
2224 dme1737_pwm_chmod_attr[ix],
2225 S_IRUGO | S_IWUSR);
2226 }
2227 }
2228 }
2229
2230 return 0;
2231
2232 exit_remove:
2233 dme1737_remove_files(dev);
2234 exit:
2235 return err;
2236 }
2237
2238 static int dme1737_init_device(struct device *dev)
2239 {
2240 struct dme1737_data *data = dev_get_drvdata(dev);
2241 struct i2c_client *client = data->client;
2242 int ix;
2243 u8 reg;
2244
2245 /* Point to the right nominal voltages array */
2246 data->in_nominal = IN_NOMINAL(data->type);
2247
2248 data->config = dme1737_read(data, DME1737_REG_CONFIG);
2249 /* Inform if part is not monitoring/started */
2250 if (!(data->config & 0x01)) {
2251 if (!force_start) {
2252 dev_err(dev,
2253 "Device is not monitoring. Use the force_start load parameter to override.\n");
2254 return -EFAULT;
2255 }
2256
2257 /* Force monitoring */
2258 data->config |= 0x01;
2259 dme1737_write(data, DME1737_REG_CONFIG, data->config);
2260 }
2261 /* Inform if part is not ready */
2262 if (!(data->config & 0x04)) {
2263 dev_err(dev, "Device is not ready.\n");
2264 return -EFAULT;
2265 }
2266
2267 /*
2268 * Determine which optional fan and pwm features are enabled (only
2269 * valid for I2C devices)
2270 */
2271 if (client) { /* I2C chip */
2272 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
2273 /* Check if optional fan3 input is enabled */
2274 if (data->config2 & 0x04)
2275 data->has_features |= HAS_FAN(2);
2276
2277 /*
2278 * Fan4 and pwm3 are only available if the client's I2C address
2279 * is the default 0x2e. Otherwise the I/Os associated with
2280 * these functions are used for addr enable/select.
2281 */
2282 if (client->addr == 0x2e)
2283 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
2284
2285 /*
2286 * Determine which of the optional fan[5-6] and pwm[5-6]
2287 * features are enabled. For this, we need to query the runtime
2288 * registers through the Super-IO LPC interface. Try both
2289 * config ports 0x2e and 0x4e.
2290 */
2291 if (dme1737_i2c_get_features(0x2e, data) &&
2292 dme1737_i2c_get_features(0x4e, data)) {
2293 dev_warn(dev,
2294 "Failed to query Super-IO for optional features.\n");
2295 }
2296 }
2297
2298 /* Fan[1-2] and pwm[1-2] are present in all chips */
2299 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1);
2300
2301 /* Chip-dependent features */
2302 switch (data->type) {
2303 case dme1737:
2304 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 |
2305 HAS_ZONE_HYST | HAS_PWM_MIN;
2306 break;
2307 case sch311x:
2308 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 |
2309 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2);
2310 break;
2311 case sch5027:
2312 data->has_features |= HAS_ZONE3;
2313 break;
2314 case sch5127:
2315 data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7;
2316 break;
2317 default:
2318 break;
2319 }
2320
2321 dev_info(dev,
2322 "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
2323 (data->has_features & HAS_PWM(2)) ? "yes" : "no",
2324 (data->has_features & HAS_PWM(4)) ? "yes" : "no",
2325 (data->has_features & HAS_PWM(5)) ? "yes" : "no",
2326 (data->has_features & HAS_FAN(2)) ? "yes" : "no",
2327 (data->has_features & HAS_FAN(3)) ? "yes" : "no",
2328 (data->has_features & HAS_FAN(4)) ? "yes" : "no",
2329 (data->has_features & HAS_FAN(5)) ? "yes" : "no");
2330
2331 reg = dme1737_read(data, DME1737_REG_TACH_PWM);
2332 /* Inform if fan-to-pwm mapping differs from the default */
2333 if (client && reg != 0xa4) { /* I2C chip */
2334 dev_warn(dev,
2335 "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, fan4->pwm%d. %s\n",
2336 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2337 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1,
2338 DO_REPORT);
2339 } else if (!client && reg != 0x24) { /* ISA chip */
2340 dev_warn(dev,
2341 "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. %s\n",
2342 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2343 ((reg >> 4) & 0x03) + 1, DO_REPORT);
2344 }
2345
2346 /*
2347 * Switch pwm[1-3] to manual mode if they are currently disabled and
2348 * set the duty-cycles to 0% (which is identical to the PWMs being
2349 * disabled).
2350 */
2351 if (!(data->config & 0x02)) {
2352 for (ix = 0; ix < 3; ix++) {
2353 data->pwm_config[ix] = dme1737_read(data,
2354 DME1737_REG_PWM_CONFIG(ix));
2355 if ((data->has_features & HAS_PWM(ix)) &&
2356 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
2357 dev_info(dev,
2358 "Switching pwm%d to manual mode.\n",
2359 ix + 1);
2360 data->pwm_config[ix] = PWM_EN_TO_REG(1,
2361 data->pwm_config[ix]);
2362 dme1737_write(data, DME1737_REG_PWM(ix), 0);
2363 dme1737_write(data,
2364 DME1737_REG_PWM_CONFIG(ix),
2365 data->pwm_config[ix]);
2366 }
2367 }
2368 }
2369
2370 /* Initialize the default PWM auto channels zone (acz) assignments */
2371 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
2372 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
2373 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2374
2375 /* Set VRM */
2376 if (data->has_features & HAS_VID)
2377 data->vrm = vid_which_vrm();
2378
2379 return 0;
2380 }
2381
2382 /* ---------------------------------------------------------------------
2383 * I2C device detection and registration
2384 * --------------------------------------------------------------------- */
2385
2386 static struct i2c_driver dme1737_i2c_driver;
2387
2388 static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2389 {
2390 int err = 0, reg;
2391 u16 addr;
2392
2393 dme1737_sio_enter(sio_cip);
2394
2395 /*
2396 * Check device ID
2397 * We currently know about two kinds of DME1737 and SCH5027.
2398 */
2399 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2400 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2401 reg == SCH5027_ID)) {
2402 err = -ENODEV;
2403 goto exit;
2404 }
2405
2406 /* Select logical device A (runtime registers) */
2407 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2408
2409 /* Get the base address of the runtime registers */
2410 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2411 dme1737_sio_inb(sio_cip, 0x61);
2412 if (!addr) {
2413 err = -ENODEV;
2414 goto exit;
2415 }
2416
2417 /*
2418 * Read the runtime registers to determine which optional features
2419 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
2420 * to '10' if the respective feature is enabled.
2421 */
2422 if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */
2423 data->has_features |= HAS_FAN(5);
2424 if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */
2425 data->has_features |= HAS_PWM(5);
2426 if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */
2427 data->has_features |= HAS_FAN(4);
2428 if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */
2429 data->has_features |= HAS_PWM(4);
2430
2431 exit:
2432 dme1737_sio_exit(sio_cip);
2433
2434 return err;
2435 }
2436
2437 /* Return 0 if detection is successful, -ENODEV otherwise */
2438 static int dme1737_i2c_detect(struct i2c_client *client,
2439 struct i2c_board_info *info)
2440 {
2441 struct i2c_adapter *adapter = client->adapter;
2442 struct device *dev = &adapter->dev;
2443 u8 company, verstep = 0;
2444 const char *name;
2445
2446 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2447 return -ENODEV;
2448
2449 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2450 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
2451
2452 if (company == DME1737_COMPANY_SMSC &&
2453 verstep == SCH5027_VERSTEP) {
2454 name = "sch5027";
2455 } else if (company == DME1737_COMPANY_SMSC &&
2456 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
2457 name = "dme1737";
2458 } else {
2459 return -ENODEV;
2460 }
2461
2462 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
2463 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737",
2464 client->addr, verstep);
2465 strlcpy(info->type, name, I2C_NAME_SIZE);
2466
2467 return 0;
2468 }
2469
2470 static int dme1737_i2c_probe(struct i2c_client *client,
2471 const struct i2c_device_id *id)
2472 {
2473 struct dme1737_data *data;
2474 struct device *dev = &client->dev;
2475 int err;
2476
2477 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2478 if (!data)
2479 return -ENOMEM;
2480
2481 i2c_set_clientdata(client, data);
2482 data->type = id->driver_data;
2483 data->client = client;
2484 data->name = client->name;
2485 mutex_init(&data->update_lock);
2486
2487 /* Initialize the DME1737 chip */
2488 err = dme1737_init_device(dev);
2489 if (err) {
2490 dev_err(dev, "Failed to initialize device.\n");
2491 return err;
2492 }
2493
2494 /* Create sysfs files */
2495 err = dme1737_create_files(dev);
2496 if (err) {
2497 dev_err(dev, "Failed to create sysfs files.\n");
2498 return err;
2499 }
2500
2501 /* Register device */
2502 data->hwmon_dev = hwmon_device_register(dev);
2503 if (IS_ERR(data->hwmon_dev)) {
2504 dev_err(dev, "Failed to register device.\n");
2505 err = PTR_ERR(data->hwmon_dev);
2506 goto exit_remove;
2507 }
2508
2509 return 0;
2510
2511 exit_remove:
2512 dme1737_remove_files(dev);
2513 return err;
2514 }
2515
2516 static int dme1737_i2c_remove(struct i2c_client *client)
2517 {
2518 struct dme1737_data *data = i2c_get_clientdata(client);
2519
2520 hwmon_device_unregister(data->hwmon_dev);
2521 dme1737_remove_files(&client->dev);
2522
2523 return 0;
2524 }
2525
2526 static const struct i2c_device_id dme1737_id[] = {
2527 { "dme1737", dme1737 },
2528 { "sch5027", sch5027 },
2529 { }
2530 };
2531 MODULE_DEVICE_TABLE(i2c, dme1737_id);
2532
2533 static struct i2c_driver dme1737_i2c_driver = {
2534 .class = I2C_CLASS_HWMON,
2535 .driver = {
2536 .name = "dme1737",
2537 },
2538 .probe = dme1737_i2c_probe,
2539 .remove = dme1737_i2c_remove,
2540 .id_table = dme1737_id,
2541 .detect = dme1737_i2c_detect,
2542 .address_list = normal_i2c,
2543 };
2544
2545 /* ---------------------------------------------------------------------
2546 * ISA device detection and registration
2547 * --------------------------------------------------------------------- */
2548
2549 static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2550 {
2551 int err = 0, reg;
2552 unsigned short base_addr;
2553
2554 dme1737_sio_enter(sio_cip);
2555
2556 /*
2557 * Check device ID
2558 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127
2559 */
2560 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2561 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2562 reg == SCH5127_ID)) {
2563 err = -ENODEV;
2564 goto exit;
2565 }
2566
2567 /* Select logical device A (runtime registers) */
2568 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2569
2570 /* Get the base address of the runtime registers */
2571 base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2572 dme1737_sio_inb(sio_cip, 0x61);
2573 if (!base_addr) {
2574 pr_err("Base address not set\n");
2575 err = -ENODEV;
2576 goto exit;
2577 }
2578
2579 /*
2580 * Access to the hwmon registers is through an index/data register
2581 * pair located at offset 0x70/0x71.
2582 */
2583 *addr = base_addr + 0x70;
2584
2585 exit:
2586 dme1737_sio_exit(sio_cip);
2587 return err;
2588 }
2589
2590 static int __init dme1737_isa_device_add(unsigned short addr)
2591 {
2592 struct resource res = {
2593 .start = addr,
2594 .end = addr + DME1737_EXTENT - 1,
2595 .name = "dme1737",
2596 .flags = IORESOURCE_IO,
2597 };
2598 int err;
2599
2600 err = acpi_check_resource_conflict(&res);
2601 if (err)
2602 goto exit;
2603
2604 pdev = platform_device_alloc("dme1737", addr);
2605 if (!pdev) {
2606 pr_err("Failed to allocate device\n");
2607 err = -ENOMEM;
2608 goto exit;
2609 }
2610
2611 err = platform_device_add_resources(pdev, &res, 1);
2612 if (err) {
2613 pr_err("Failed to add device resource (err = %d)\n", err);
2614 goto exit_device_put;
2615 }
2616
2617 err = platform_device_add(pdev);
2618 if (err) {
2619 pr_err("Failed to add device (err = %d)\n", err);
2620 goto exit_device_put;
2621 }
2622
2623 return 0;
2624
2625 exit_device_put:
2626 platform_device_put(pdev);
2627 pdev = NULL;
2628 exit:
2629 return err;
2630 }
2631
2632 static int dme1737_isa_probe(struct platform_device *pdev)
2633 {
2634 u8 company, device;
2635 struct resource *res;
2636 struct dme1737_data *data;
2637 struct device *dev = &pdev->dev;
2638 int err;
2639
2640 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2641 if (!devm_request_region(dev, res->start, DME1737_EXTENT, "dme1737")) {
2642 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
2643 (unsigned short)res->start,
2644 (unsigned short)res->start + DME1737_EXTENT - 1);
2645 return -EBUSY;
2646 }
2647
2648 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2649 if (!data)
2650 return -ENOMEM;
2651
2652 data->addr = res->start;
2653 platform_set_drvdata(pdev, data);
2654
2655 /* Skip chip detection if module is loaded with force_id parameter */
2656 switch (force_id) {
2657 case SCH3112_ID:
2658 case SCH3114_ID:
2659 case SCH3116_ID:
2660 data->type = sch311x;
2661 break;
2662 case SCH5127_ID:
2663 data->type = sch5127;
2664 break;
2665 default:
2666 company = dme1737_read(data, DME1737_REG_COMPANY);
2667 device = dme1737_read(data, DME1737_REG_DEVICE);
2668
2669 if ((company == DME1737_COMPANY_SMSC) &&
2670 (device == SCH311X_DEVICE)) {
2671 data->type = sch311x;
2672 } else if ((company == DME1737_COMPANY_SMSC) &&
2673 (device == SCH5127_DEVICE)) {
2674 data->type = sch5127;
2675 } else {
2676 return -ENODEV;
2677 }
2678 }
2679
2680 if (data->type == sch5127)
2681 data->name = "sch5127";
2682 else
2683 data->name = "sch311x";
2684
2685 /* Initialize the mutex */
2686 mutex_init(&data->update_lock);
2687
2688 dev_info(dev, "Found a %s chip at 0x%04x\n",
2689 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr);
2690
2691 /* Initialize the chip */
2692 err = dme1737_init_device(dev);
2693 if (err) {
2694 dev_err(dev, "Failed to initialize device.\n");
2695 return err;
2696 }
2697
2698 /* Create sysfs files */
2699 err = dme1737_create_files(dev);
2700 if (err) {
2701 dev_err(dev, "Failed to create sysfs files.\n");
2702 return err;
2703 }
2704
2705 /* Register device */
2706 data->hwmon_dev = hwmon_device_register(dev);
2707 if (IS_ERR(data->hwmon_dev)) {
2708 dev_err(dev, "Failed to register device.\n");
2709 err = PTR_ERR(data->hwmon_dev);
2710 goto exit_remove_files;
2711 }
2712
2713 return 0;
2714
2715 exit_remove_files:
2716 dme1737_remove_files(dev);
2717 return err;
2718 }
2719
2720 static int dme1737_isa_remove(struct platform_device *pdev)
2721 {
2722 struct dme1737_data *data = platform_get_drvdata(pdev);
2723
2724 hwmon_device_unregister(data->hwmon_dev);
2725 dme1737_remove_files(&pdev->dev);
2726
2727 return 0;
2728 }
2729
2730 static struct platform_driver dme1737_isa_driver = {
2731 .driver = {
2732 .owner = THIS_MODULE,
2733 .name = "dme1737",
2734 },
2735 .probe = dme1737_isa_probe,
2736 .remove = dme1737_isa_remove,
2737 };
2738
2739 /* ---------------------------------------------------------------------
2740 * Module initialization and cleanup
2741 * --------------------------------------------------------------------- */
2742
2743 static int __init dme1737_init(void)
2744 {
2745 int err;
2746 unsigned short addr;
2747
2748 err = i2c_add_driver(&dme1737_i2c_driver);
2749 if (err)
2750 goto exit;
2751
2752 if (dme1737_isa_detect(0x2e, &addr) &&
2753 dme1737_isa_detect(0x4e, &addr) &&
2754 (!probe_all_addr ||
2755 (dme1737_isa_detect(0x162e, &addr) &&
2756 dme1737_isa_detect(0x164e, &addr)))) {
2757 /* Return 0 if we didn't find an ISA device */
2758 return 0;
2759 }
2760
2761 err = platform_driver_register(&dme1737_isa_driver);
2762 if (err)
2763 goto exit_del_i2c_driver;
2764
2765 /* Sets global pdev as a side effect */
2766 err = dme1737_isa_device_add(addr);
2767 if (err)
2768 goto exit_del_isa_driver;
2769
2770 return 0;
2771
2772 exit_del_isa_driver:
2773 platform_driver_unregister(&dme1737_isa_driver);
2774 exit_del_i2c_driver:
2775 i2c_del_driver(&dme1737_i2c_driver);
2776 exit:
2777 return err;
2778 }
2779
2780 static void __exit dme1737_exit(void)
2781 {
2782 if (pdev) {
2783 platform_device_unregister(pdev);
2784 platform_driver_unregister(&dme1737_isa_driver);
2785 }
2786
2787 i2c_del_driver(&dme1737_i2c_driver);
2788 }
2789
2790 MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
2791 MODULE_DESCRIPTION("DME1737 sensors");
2792 MODULE_LICENSE("GPL");
2793
2794 module_init(dme1737_init);
2795 module_exit(dme1737_exit);
Linux kernel - Deliverables
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