projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'drm-panel/drm/panel/for-next'
[deliverable/linux.git] / drivers / i2c / busses / i2c-designware-core.c
1 /*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
22 *
23 */
24 #include <linux/export.h>
25 #include <linux/errno.h>
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include "i2c-designware-core.h"
34
35 /*
36 * Registers offset
37 */
38 #define DW_IC_CON 0x0
39 #define DW_IC_TAR 0x4
40 #define DW_IC_DATA_CMD 0x10
41 #define DW_IC_SS_SCL_HCNT 0x14
42 #define DW_IC_SS_SCL_LCNT 0x18
43 #define DW_IC_FS_SCL_HCNT 0x1c
44 #define DW_IC_FS_SCL_LCNT 0x20
45 #define DW_IC_HS_SCL_HCNT 0x24
46 #define DW_IC_HS_SCL_LCNT 0x28
47 #define DW_IC_INTR_STAT 0x2c
48 #define DW_IC_INTR_MASK 0x30
49 #define DW_IC_RAW_INTR_STAT 0x34
50 #define DW_IC_RX_TL 0x38
51 #define DW_IC_TX_TL 0x3c
52 #define DW_IC_CLR_INTR 0x40
53 #define DW_IC_CLR_RX_UNDER 0x44
54 #define DW_IC_CLR_RX_OVER 0x48
55 #define DW_IC_CLR_TX_OVER 0x4c
56 #define DW_IC_CLR_RD_REQ 0x50
57 #define DW_IC_CLR_TX_ABRT 0x54
58 #define DW_IC_CLR_RX_DONE 0x58
59 #define DW_IC_CLR_ACTIVITY 0x5c
60 #define DW_IC_CLR_STOP_DET 0x60
61 #define DW_IC_CLR_START_DET 0x64
62 #define DW_IC_CLR_GEN_CALL 0x68
63 #define DW_IC_ENABLE 0x6c
64 #define DW_IC_STATUS 0x70
65 #define DW_IC_TXFLR 0x74
66 #define DW_IC_RXFLR 0x78
67 #define DW_IC_SDA_HOLD 0x7c
68 #define DW_IC_TX_ABRT_SOURCE 0x80
69 #define DW_IC_ENABLE_STATUS 0x9c
70 #define DW_IC_COMP_PARAM_1 0xf4
71 #define DW_IC_COMP_VERSION 0xf8
72 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
73 #define DW_IC_COMP_TYPE 0xfc
74 #define DW_IC_COMP_TYPE_VALUE 0x44570140
75
76 #define DW_IC_INTR_RX_UNDER 0x001
77 #define DW_IC_INTR_RX_OVER 0x002
78 #define DW_IC_INTR_RX_FULL 0x004
79 #define DW_IC_INTR_TX_OVER 0x008
80 #define DW_IC_INTR_TX_EMPTY 0x010
81 #define DW_IC_INTR_RD_REQ 0x020
82 #define DW_IC_INTR_TX_ABRT 0x040
83 #define DW_IC_INTR_RX_DONE 0x080
84 #define DW_IC_INTR_ACTIVITY 0x100
85 #define DW_IC_INTR_STOP_DET 0x200
86 #define DW_IC_INTR_START_DET 0x400
87 #define DW_IC_INTR_GEN_CALL 0x800
88
89 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
90 DW_IC_INTR_TX_EMPTY | \
91 DW_IC_INTR_TX_ABRT | \
92 DW_IC_INTR_STOP_DET)
93
94 #define DW_IC_STATUS_ACTIVITY 0x1
95 #define DW_IC_STATUS_TFE BIT(2)
96 #define DW_IC_STATUS_MST_ACTIVITY BIT(5)
97
98 #define DW_IC_ERR_TX_ABRT 0x1
99
100 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
101
102 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
103 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
104
105 /*
106 * status codes
107 */
108 #define STATUS_IDLE 0x0
109 #define STATUS_WRITE_IN_PROGRESS 0x1
110 #define STATUS_READ_IN_PROGRESS 0x2
111
112 #define TIMEOUT 20 /* ms */
113
114 /*
115 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
116 *
117 * only expected abort codes are listed here
118 * refer to the datasheet for the full list
119 */
120 #define ABRT_7B_ADDR_NOACK 0
121 #define ABRT_10ADDR1_NOACK 1
122 #define ABRT_10ADDR2_NOACK 2
123 #define ABRT_TXDATA_NOACK 3
124 #define ABRT_GCALL_NOACK 4
125 #define ABRT_GCALL_READ 5
126 #define ABRT_SBYTE_ACKDET 7
127 #define ABRT_SBYTE_NORSTRT 9
128 #define ABRT_10B_RD_NORSTRT 10
129 #define ABRT_MASTER_DIS 11
130 #define ARB_LOST 12
131
132 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
133 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
134 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
135 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
136 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
137 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
138 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
139 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
140 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
141 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
142 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
143
144 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
145 DW_IC_TX_ABRT_10ADDR1_NOACK | \
146 DW_IC_TX_ABRT_10ADDR2_NOACK | \
147 DW_IC_TX_ABRT_TXDATA_NOACK | \
148 DW_IC_TX_ABRT_GCALL_NOACK)
149
150 static char *abort_sources[] = {
151 [ABRT_7B_ADDR_NOACK] =
152 "slave address not acknowledged (7bit mode)",
153 [ABRT_10ADDR1_NOACK] =
154 "first address byte not acknowledged (10bit mode)",
155 [ABRT_10ADDR2_NOACK] =
156 "second address byte not acknowledged (10bit mode)",
157 [ABRT_TXDATA_NOACK] =
158 "data not acknowledged",
159 [ABRT_GCALL_NOACK] =
160 "no acknowledgement for a general call",
161 [ABRT_GCALL_READ] =
162 "read after general call",
163 [ABRT_SBYTE_ACKDET] =
164 "start byte acknowledged",
165 [ABRT_SBYTE_NORSTRT] =
166 "trying to send start byte when restart is disabled",
167 [ABRT_10B_RD_NORSTRT] =
168 "trying to read when restart is disabled (10bit mode)",
169 [ABRT_MASTER_DIS] =
170 "trying to use disabled adapter",
171 [ARB_LOST] =
172 "lost arbitration",
173 };
174
175 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
176 {
177 u32 value;
178
179 if (dev->accessor_flags & ACCESS_16BIT)
180 value = readw_relaxed(dev->base + offset) |
181 (readw_relaxed(dev->base + offset + 2) << 16);
182 else
183 value = readl_relaxed(dev->base + offset);
184
185 if (dev->accessor_flags & ACCESS_SWAP)
186 return swab32(value);
187 else
188 return value;
189 }
190
191 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
192 {
193 if (dev->accessor_flags & ACCESS_SWAP)
194 b = swab32(b);
195
196 if (dev->accessor_flags & ACCESS_16BIT) {
197 writew_relaxed((u16)b, dev->base + offset);
198 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
199 } else {
200 writel_relaxed(b, dev->base + offset);
201 }
202 }
203
204 static u32
205 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
206 {
207 /*
208 * DesignWare I2C core doesn't seem to have solid strategy to meet
209 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
210 * will result in violation of the tHD;STA spec.
211 */
212 if (cond)
213 /*
214 * Conditional expression:
215 *
216 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
217 *
218 * This is based on the DW manuals, and represents an ideal
219 * configuration. The resulting I2C bus speed will be
220 * faster than any of the others.
221 *
222 * If your hardware is free from tHD;STA issue, try this one.
223 */
224 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
225 else
226 /*
227 * Conditional expression:
228 *
229 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
230 *
231 * This is just experimental rule; the tHD;STA period turned
232 * out to be proportinal to (_HCNT + 3). With this setting,
233 * we could meet both tHIGH and tHD;STA timing specs.
234 *
235 * If unsure, you'd better to take this alternative.
236 *
237 * The reason why we need to take into account "tf" here,
238 * is the same as described in i2c_dw_scl_lcnt().
239 */
240 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
241 - 3 + offset;
242 }
243
244 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
245 {
246 /*
247 * Conditional expression:
248 *
249 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
250 *
251 * DW I2C core starts counting the SCL CNTs for the LOW period
252 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
253 * In order to meet the tLOW timing spec, we need to take into
254 * account the fall time of SCL signal (tf). Default tf value
255 * should be 0.3 us, for safety.
256 */
257 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
258 }
259
260 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
261 {
262 dw_writel(dev, enable, DW_IC_ENABLE);
263 }
264
265 static void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable)
266 {
267 int timeout = 100;
268
269 do {
270 __i2c_dw_enable(dev, enable);
271 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
272 return;
273
274 /*
275 * Wait 10 times the signaling period of the highest I2C
276 * transfer supported by the driver (for 400KHz this is
277 * 25us) as described in the DesignWare I2C databook.
278 */
279 usleep_range(25, 250);
280 } while (timeout--);
281
282 dev_warn(dev->dev, "timeout in %sabling adapter\n",
283 enable ? "en" : "dis");
284 }
285
286 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
287 {
288 /*
289 * Clock is not necessary if we got LCNT/HCNT values directly from
290 * the platform code.
291 */
292 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
293 return 0;
294 return dev->get_clk_rate_khz(dev);
295 }
296
297 static int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
298 {
299 int ret;
300
301 if (!dev->acquire_lock)
302 return 0;
303
304 ret = dev->acquire_lock(dev);
305 if (!ret)
306 return 0;
307
308 dev_err(dev->dev, "couldn't acquire bus ownership\n");
309
310 return ret;
311 }
312
313 static void i2c_dw_release_lock(struct dw_i2c_dev *dev)
314 {
315 if (dev->release_lock)
316 dev->release_lock(dev);
317 }
318
319 /**
320 * i2c_dw_init() - initialize the designware i2c master hardware
321 * @dev: device private data
322 *
323 * This functions configures and enables the I2C master.
324 * This function is called during I2C init function, and in case of timeout at
325 * run time.
326 */
327 int i2c_dw_init(struct dw_i2c_dev *dev)
328 {
329 u32 hcnt, lcnt;
330 u32 reg, comp_param1;
331 u32 sda_falling_time, scl_falling_time;
332 int ret;
333
334 ret = i2c_dw_acquire_lock(dev);
335 if (ret)
336 return ret;
337
338 reg = dw_readl(dev, DW_IC_COMP_TYPE);
339 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
340 /* Configure register endianess access */
341 dev->accessor_flags |= ACCESS_SWAP;
342 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
343 /* Configure register access mode 16bit */
344 dev->accessor_flags |= ACCESS_16BIT;
345 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
346 dev_err(dev->dev, "Unknown Synopsys component type: "
347 "0x%08x\n", reg);
348 i2c_dw_release_lock(dev);
349 return -ENODEV;
350 }
351
352 comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
353
354 /* Disable the adapter */
355 __i2c_dw_enable_and_wait(dev, false);
356
357 /* set standard and fast speed deviders for high/low periods */
358
359 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
360 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
361
362 /* Set SCL timing parameters for standard-mode */
363 if (dev->ss_hcnt && dev->ss_lcnt) {
364 hcnt = dev->ss_hcnt;
365 lcnt = dev->ss_lcnt;
366 } else {
367 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
368 4000, /* tHD;STA = tHIGH = 4.0 us */
369 sda_falling_time,
370 0, /* 0: DW default, 1: Ideal */
371 0); /* No offset */
372 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
373 4700, /* tLOW = 4.7 us */
374 scl_falling_time,
375 0); /* No offset */
376 }
377 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
378 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
379 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
380
381 /* Set SCL timing parameters for fast-mode or fast-mode plus */
382 if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
383 hcnt = dev->fp_hcnt;
384 lcnt = dev->fp_lcnt;
385 } else if (dev->fs_hcnt && dev->fs_lcnt) {
386 hcnt = dev->fs_hcnt;
387 lcnt = dev->fs_lcnt;
388 } else {
389 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
390 600, /* tHD;STA = tHIGH = 0.6 us */
391 sda_falling_time,
392 0, /* 0: DW default, 1: Ideal */
393 0); /* No offset */
394 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
395 1300, /* tLOW = 1.3 us */
396 scl_falling_time,
397 0); /* No offset */
398 }
399 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
400 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
401 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
402
403 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
404 DW_IC_CON_SPEED_HIGH) {
405 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
406 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
407 dev_err(dev->dev, "High Speed not supported!\n");
408 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
409 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
410 } else if (dev->hs_hcnt && dev->hs_lcnt) {
411 hcnt = dev->hs_hcnt;
412 lcnt = dev->hs_lcnt;
413 dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
414 dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
415 dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
416 hcnt, lcnt);
417 }
418 }
419
420 /* Configure SDA Hold Time if required */
421 reg = dw_readl(dev, DW_IC_COMP_VERSION);
422 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
423 if (dev->sda_hold_time) {
424 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
425 } else {
426 /* Keep previous hold time setting if no one set it */
427 dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
428 }
429 } else {
430 dev_warn(dev->dev,
431 "Hardware too old to adjust SDA hold time.\n");
432 }
433
434 /* Configure Tx/Rx FIFO threshold levels */
435 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
436 dw_writel(dev, 0, DW_IC_RX_TL);
437
438 /* configure the i2c master */
439 dw_writel(dev, dev->master_cfg , DW_IC_CON);
440
441 i2c_dw_release_lock(dev);
442
443 return 0;
444 }
445 EXPORT_SYMBOL_GPL(i2c_dw_init);
446
447 /*
448 * Waiting for bus not busy
449 */
450 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
451 {
452 int timeout = TIMEOUT;
453
454 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
455 if (timeout <= 0) {
456 dev_warn(dev->dev, "timeout waiting for bus ready\n");
457 return -ETIMEDOUT;
458 }
459 timeout--;
460 usleep_range(1000, 1100);
461 }
462
463 return 0;
464 }
465
466 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
467 {
468 struct i2c_msg *msgs = dev->msgs;
469 u32 ic_tar = 0;
470 bool enabled;
471
472 enabled = dw_readl(dev, DW_IC_ENABLE_STATUS) & 1;
473
474 if (enabled) {
475 u32 ic_status;
476
477 /*
478 * Only disable adapter if ic_tar and ic_con can't be
479 * dynamically updated
480 */
481 ic_status = dw_readl(dev, DW_IC_STATUS);
482 if (!dev->dynamic_tar_update_enabled ||
483 (ic_status & DW_IC_STATUS_MST_ACTIVITY) ||
484 !(ic_status & DW_IC_STATUS_TFE)) {
485 __i2c_dw_enable_and_wait(dev, false);
486 enabled = false;
487 }
488 }
489
490 /* if the slave address is ten bit address, enable 10BITADDR */
491 if (dev->dynamic_tar_update_enabled) {
492 /*
493 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
494 * mode has to be enabled via bit 12 of IC_TAR register,
495 * otherwise bit 4 of IC_CON is used.
496 */
497 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
498 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
499 } else {
500 u32 ic_con = dw_readl(dev, DW_IC_CON);
501
502 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
503 ic_con |= DW_IC_CON_10BITADDR_MASTER;
504 else
505 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
506 dw_writel(dev, ic_con, DW_IC_CON);
507 }
508
509 /*
510 * Set the slave (target) address and enable 10-bit addressing mode
511 * if applicable.
512 */
513 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
514
515 /* enforce disabled interrupts (due to HW issues) */
516 i2c_dw_disable_int(dev);
517
518 if (!enabled)
519 __i2c_dw_enable(dev, true);
520
521 /* Clear and enable interrupts */
522 dw_readl(dev, DW_IC_CLR_INTR);
523 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
524 }
525
526 /*
527 * Initiate (and continue) low level master read/write transaction.
528 * This function is only called from i2c_dw_isr, and pumping i2c_msg
529 * messages into the tx buffer. Even if the size of i2c_msg data is
530 * longer than the size of the tx buffer, it handles everything.
531 */
532 static void
533 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
534 {
535 struct i2c_msg *msgs = dev->msgs;
536 u32 intr_mask;
537 int tx_limit, rx_limit;
538 u32 addr = msgs[dev->msg_write_idx].addr;
539 u32 buf_len = dev->tx_buf_len;
540 u8 *buf = dev->tx_buf;
541 bool need_restart = false;
542
543 intr_mask = DW_IC_INTR_DEFAULT_MASK;
544
545 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
546 /*
547 * if target address has changed, we need to
548 * reprogram the target address in the i2c
549 * adapter when we are done with this transfer
550 */
551 if (msgs[dev->msg_write_idx].addr != addr) {
552 dev_err(dev->dev,
553 "%s: invalid target address\n", __func__);
554 dev->msg_err = -EINVAL;
555 break;
556 }
557
558 if (msgs[dev->msg_write_idx].len == 0) {
559 dev_err(dev->dev,
560 "%s: invalid message length\n", __func__);
561 dev->msg_err = -EINVAL;
562 break;
563 }
564
565 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
566 /* new i2c_msg */
567 buf = msgs[dev->msg_write_idx].buf;
568 buf_len = msgs[dev->msg_write_idx].len;
569
570 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
571 * IC_RESTART_EN are set, we must manually
572 * set restart bit between messages.
573 */
574 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
575 (dev->msg_write_idx > 0))
576 need_restart = true;
577 }
578
579 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
580 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
581
582 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
583 u32 cmd = 0;
584
585 /*
586 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
587 * manually set the stop bit. However, it cannot be
588 * detected from the registers so we set it always
589 * when writing/reading the last byte.
590 */
591 if (dev->msg_write_idx == dev->msgs_num - 1 &&
592 buf_len == 1)
593 cmd |= BIT(9);
594
595 if (need_restart) {
596 cmd |= BIT(10);
597 need_restart = false;
598 }
599
600 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
601
602 /* avoid rx buffer overrun */
603 if (rx_limit - dev->rx_outstanding <= 0)
604 break;
605
606 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
607 rx_limit--;
608 dev->rx_outstanding++;
609 } else
610 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
611 tx_limit--; buf_len--;
612 }
613
614 dev->tx_buf = buf;
615 dev->tx_buf_len = buf_len;
616
617 if (buf_len > 0) {
618 /* more bytes to be written */
619 dev->status |= STATUS_WRITE_IN_PROGRESS;
620 break;
621 } else
622 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
623 }
624
625 /*
626 * If i2c_msg index search is completed, we don't need TX_EMPTY
627 * interrupt any more.
628 */
629 if (dev->msg_write_idx == dev->msgs_num)
630 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
631
632 if (dev->msg_err)
633 intr_mask = 0;
634
635 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
636 }
637
638 static void
639 i2c_dw_read(struct dw_i2c_dev *dev)
640 {
641 struct i2c_msg *msgs = dev->msgs;
642 int rx_valid;
643
644 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
645 u32 len;
646 u8 *buf;
647
648 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
649 continue;
650
651 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
652 len = msgs[dev->msg_read_idx].len;
653 buf = msgs[dev->msg_read_idx].buf;
654 } else {
655 len = dev->rx_buf_len;
656 buf = dev->rx_buf;
657 }
658
659 rx_valid = dw_readl(dev, DW_IC_RXFLR);
660
661 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
662 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
663 dev->rx_outstanding--;
664 }
665
666 if (len > 0) {
667 dev->status |= STATUS_READ_IN_PROGRESS;
668 dev->rx_buf_len = len;
669 dev->rx_buf = buf;
670 return;
671 } else
672 dev->status &= ~STATUS_READ_IN_PROGRESS;
673 }
674 }
675
676 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
677 {
678 unsigned long abort_source = dev->abort_source;
679 int i;
680
681 if (abort_source & DW_IC_TX_ABRT_NOACK) {
682 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
683 dev_dbg(dev->dev,
684 "%s: %s\n", __func__, abort_sources[i]);
685 return -EREMOTEIO;
686 }
687
688 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
689 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
690
691 if (abort_source & DW_IC_TX_ARB_LOST)
692 return -EAGAIN;
693 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
694 return -EINVAL; /* wrong msgs[] data */
695 else
696 return -EIO;
697 }
698
699 /*
700 * Prepare controller for a transaction and start transfer by calling
701 * i2c_dw_xfer_init()
702 */
703 static int
704 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
705 {
706 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
707 int ret;
708
709 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
710
711 pm_runtime_get_sync(dev->dev);
712
713 reinit_completion(&dev->cmd_complete);
714 dev->msgs = msgs;
715 dev->msgs_num = num;
716 dev->cmd_err = 0;
717 dev->msg_write_idx = 0;
718 dev->msg_read_idx = 0;
719 dev->msg_err = 0;
720 dev->status = STATUS_IDLE;
721 dev->abort_source = 0;
722 dev->rx_outstanding = 0;
723
724 ret = i2c_dw_acquire_lock(dev);
725 if (ret)
726 goto done_nolock;
727
728 ret = i2c_dw_wait_bus_not_busy(dev);
729 if (ret < 0)
730 goto done;
731
732 /* start the transfers */
733 i2c_dw_xfer_init(dev);
734
735 /* wait for tx to complete */
736 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
737 dev_err(dev->dev, "controller timed out\n");
738 /* i2c_dw_init implicitly disables the adapter */
739 i2c_dw_init(dev);
740 ret = -ETIMEDOUT;
741 goto done;
742 }
743
744 if (dev->msg_err) {
745 ret = dev->msg_err;
746 goto done;
747 }
748
749 /* no error */
750 if (likely(!dev->cmd_err)) {
751 ret = num;
752 goto done;
753 }
754
755 /* We have an error */
756 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
757 ret = i2c_dw_handle_tx_abort(dev);
758 goto done;
759 }
760 ret = -EIO;
761
762 done:
763 i2c_dw_release_lock(dev);
764
765 done_nolock:
766 pm_runtime_mark_last_busy(dev->dev);
767 pm_runtime_put_autosuspend(dev->dev);
768
769 return ret;
770 }
771
772 static u32 i2c_dw_func(struct i2c_adapter *adap)
773 {
774 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
775 return dev->functionality;
776 }
777
778 static struct i2c_algorithm i2c_dw_algo = {
779 .master_xfer = i2c_dw_xfer,
780 .functionality = i2c_dw_func,
781 };
782
783 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
784 {
785 u32 stat;
786
787 /*
788 * The IC_INTR_STAT register just indicates "enabled" interrupts.
789 * Ths unmasked raw version of interrupt status bits are available
790 * in the IC_RAW_INTR_STAT register.
791 *
792 * That is,
793 * stat = dw_readl(IC_INTR_STAT);
794 * equals to,
795 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
796 *
797 * The raw version might be useful for debugging purposes.
798 */
799 stat = dw_readl(dev, DW_IC_INTR_STAT);
800
801 /*
802 * Do not use the IC_CLR_INTR register to clear interrupts, or
803 * you'll miss some interrupts, triggered during the period from
804 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
805 *
806 * Instead, use the separately-prepared IC_CLR_* registers.
807 */
808 if (stat & DW_IC_INTR_RX_UNDER)
809 dw_readl(dev, DW_IC_CLR_RX_UNDER);
810 if (stat & DW_IC_INTR_RX_OVER)
811 dw_readl(dev, DW_IC_CLR_RX_OVER);
812 if (stat & DW_IC_INTR_TX_OVER)
813 dw_readl(dev, DW_IC_CLR_TX_OVER);
814 if (stat & DW_IC_INTR_RD_REQ)
815 dw_readl(dev, DW_IC_CLR_RD_REQ);
816 if (stat & DW_IC_INTR_TX_ABRT) {
817 /*
818 * The IC_TX_ABRT_SOURCE register is cleared whenever
819 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
820 */
821 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
822 dw_readl(dev, DW_IC_CLR_TX_ABRT);
823 }
824 if (stat & DW_IC_INTR_RX_DONE)
825 dw_readl(dev, DW_IC_CLR_RX_DONE);
826 if (stat & DW_IC_INTR_ACTIVITY)
827 dw_readl(dev, DW_IC_CLR_ACTIVITY);
828 if (stat & DW_IC_INTR_STOP_DET)
829 dw_readl(dev, DW_IC_CLR_STOP_DET);
830 if (stat & DW_IC_INTR_START_DET)
831 dw_readl(dev, DW_IC_CLR_START_DET);
832 if (stat & DW_IC_INTR_GEN_CALL)
833 dw_readl(dev, DW_IC_CLR_GEN_CALL);
834
835 return stat;
836 }
837
838 /*
839 * Interrupt service routine. This gets called whenever an I2C interrupt
840 * occurs.
841 */
842 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
843 {
844 struct dw_i2c_dev *dev = dev_id;
845 u32 stat, enabled;
846
847 enabled = dw_readl(dev, DW_IC_ENABLE);
848 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
849 dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
850 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
851 return IRQ_NONE;
852
853 stat = i2c_dw_read_clear_intrbits(dev);
854
855 if (stat & DW_IC_INTR_TX_ABRT) {
856 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
857 dev->status = STATUS_IDLE;
858
859 /*
860 * Anytime TX_ABRT is set, the contents of the tx/rx
861 * buffers are flushed. Make sure to skip them.
862 */
863 dw_writel(dev, 0, DW_IC_INTR_MASK);
864 goto tx_aborted;
865 }
866
867 if (stat & DW_IC_INTR_RX_FULL)
868 i2c_dw_read(dev);
869
870 if (stat & DW_IC_INTR_TX_EMPTY)
871 i2c_dw_xfer_msg(dev);
872
873 /*
874 * No need to modify or disable the interrupt mask here.
875 * i2c_dw_xfer_msg() will take care of it according to
876 * the current transmit status.
877 */
878
879 tx_aborted:
880 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET))
881 || dev->msg_err) {
882 /*
883 * We must disable interruts before returning and signaling
884 * the end of the current transfer. Otherwise the hardware
885 * might continue generating interrupts for non-existent
886 * transfers.
887 */
888 i2c_dw_disable_int(dev);
889 dw_readl(dev, DW_IC_CLR_INTR);
890
891 complete(&dev->cmd_complete);
892 } else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
893 /* workaround to trigger pending interrupt */
894 stat = dw_readl(dev, DW_IC_INTR_MASK);
895 i2c_dw_disable_int(dev);
896 dw_writel(dev, stat, DW_IC_INTR_MASK);
897 }
898
899 return IRQ_HANDLED;
900 }
901
902 void i2c_dw_disable(struct dw_i2c_dev *dev)
903 {
904 /* Disable controller */
905 __i2c_dw_enable_and_wait(dev, false);
906
907 /* Disable all interupts */
908 dw_writel(dev, 0, DW_IC_INTR_MASK);
909 dw_readl(dev, DW_IC_CLR_INTR);
910 }
911 EXPORT_SYMBOL_GPL(i2c_dw_disable);
912
913 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
914 {
915 dw_writel(dev, 0, DW_IC_INTR_MASK);
916 }
917 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
918
919 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
920 {
921 return dw_readl(dev, DW_IC_COMP_PARAM_1);
922 }
923 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
924
925 int i2c_dw_probe(struct dw_i2c_dev *dev)
926 {
927 struct i2c_adapter *adap = &dev->adapter;
928 int r;
929 u32 reg;
930
931 init_completion(&dev->cmd_complete);
932
933 r = i2c_dw_init(dev);
934 if (r)
935 return r;
936
937 r = i2c_dw_acquire_lock(dev);
938 if (r)
939 return r;
940
941 /*
942 * Test if dynamic TAR update is enabled in this controller by writing
943 * to IC_10BITADDR_MASTER field in IC_CON: when it is enabled this
944 * field is read-only so it should not succeed
945 */
946 reg = dw_readl(dev, DW_IC_CON);
947 dw_writel(dev, reg ^ DW_IC_CON_10BITADDR_MASTER, DW_IC_CON);
948
949 if ((dw_readl(dev, DW_IC_CON) & DW_IC_CON_10BITADDR_MASTER) ==
950 (reg & DW_IC_CON_10BITADDR_MASTER)) {
951 dev->dynamic_tar_update_enabled = true;
952 dev_dbg(dev->dev, "Dynamic TAR update enabled");
953 }
954
955 i2c_dw_release_lock(dev);
956
957 snprintf(adap->name, sizeof(adap->name),
958 "Synopsys DesignWare I2C adapter");
959 adap->retries = 3;
960 adap->algo = &i2c_dw_algo;
961 adap->dev.parent = dev->dev;
962 i2c_set_adapdata(adap, dev);
963
964 i2c_dw_disable_int(dev);
965 r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
966 IRQF_SHARED | IRQF_COND_SUSPEND,
967 dev_name(dev->dev), dev);
968 if (r) {
969 dev_err(dev->dev, "failure requesting irq %i: %d\n",
970 dev->irq, r);
971 return r;
972 }
973
974 /*
975 * Increment PM usage count during adapter registration in order to
976 * avoid possible spurious runtime suspend when adapter device is
977 * registered to the device core and immediate resume in case bus has
978 * registered I2C slaves that do I2C transfers in their probe.
979 */
980 pm_runtime_get_noresume(dev->dev);
981 r = i2c_add_numbered_adapter(adap);
982 if (r)
983 dev_err(dev->dev, "failure adding adapter: %d\n", r);
984 pm_runtime_put_noidle(dev->dev);
985
986 return r;
987 }
988 EXPORT_SYMBOL_GPL(i2c_dw_probe);
989
990 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
991 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.069554 seconds and 6 git commands to generate.