2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
27 #include <linux/delay.h>
29 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
30 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
31 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
33 #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
34 #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
35 #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
36 #define MV64XXX_I2C_REG_CONTROL_START 0x00000020
37 #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
38 #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
40 /* Ctlr status values */
41 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
42 #define MV64XXX_I2C_STATUS_MAST_START 0x08
43 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
46 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
47 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
48 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
57 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
59 /* Register defines (I2C bridge) */
60 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
61 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
62 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
63 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
64 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
65 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
66 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
67 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
68 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
70 /* Bridge Control values */
71 #define MV64XXX_I2C_BRIDGE_CONTROL_WR 0x00000001
72 #define MV64XXX_I2C_BRIDGE_CONTROL_RD 0x00000002
73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT 0x00001000
75 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
76 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
77 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE 0x00080000
79 /* Bridge Status values */
80 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR 0x00000001
81 #define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001
82 #define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000
87 MV64XXX_I2C_STATE_INVALID
,
88 MV64XXX_I2C_STATE_IDLE
,
89 MV64XXX_I2C_STATE_WAITING_FOR_START_COND
,
90 MV64XXX_I2C_STATE_WAITING_FOR_RESTART
,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK
,
92 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK
,
93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK
,
94 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA
,
99 MV64XXX_I2C_ACTION_INVALID
,
100 MV64XXX_I2C_ACTION_CONTINUE
,
101 MV64XXX_I2C_ACTION_SEND_RESTART
,
102 MV64XXX_I2C_ACTION_OFFLOAD_RESTART
,
103 MV64XXX_I2C_ACTION_SEND_ADDR_1
,
104 MV64XXX_I2C_ACTION_SEND_ADDR_2
,
105 MV64XXX_I2C_ACTION_SEND_DATA
,
106 MV64XXX_I2C_ACTION_RCV_DATA
,
107 MV64XXX_I2C_ACTION_RCV_DATA_STOP
,
108 MV64XXX_I2C_ACTION_SEND_STOP
,
109 MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP
,
112 struct mv64xxx_i2c_regs
{
122 struct mv64xxx_i2c_data
{
123 struct i2c_msg
*msgs
;
130 void __iomem
*reg_base
;
131 struct mv64xxx_i2c_regs reg_offsets
;
141 #if defined(CONFIG_HAVE_CLK)
144 wait_queue_head_t waitq
;
147 struct i2c_adapter adapter
;
148 bool offload_enabled
;
149 /* 5us delay in order to avoid repeated start timing violation */
151 struct reset_control
*rstc
;
152 bool irq_clear_inverted
;
155 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx
= {
165 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i
= {
176 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data
*drv_data
,
181 drv_data
->cntl_bits
= MV64XXX_I2C_REG_CONTROL_ACK
|
182 MV64XXX_I2C_REG_CONTROL_INTEN
| MV64XXX_I2C_REG_CONTROL_TWSIEN
;
184 if (msg
->flags
& I2C_M_RD
)
187 if (msg
->flags
& I2C_M_TEN
) {
188 drv_data
->addr1
= 0xf0 | (((u32
)msg
->addr
& 0x300) >> 7) | dir
;
189 drv_data
->addr2
= (u32
)msg
->addr
& 0xff;
191 drv_data
->addr1
= MV64XXX_I2C_ADDR_ADDR((u32
)msg
->addr
) | dir
;
196 static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data
*drv_data
)
198 unsigned long data_reg_hi
= 0;
199 unsigned long data_reg_lo
= 0;
200 unsigned long ctrl_reg
;
201 struct i2c_msg
*msg
= drv_data
->msgs
;
203 if (!drv_data
->offload_enabled
)
206 /* Only regular transactions can be offloaded */
207 if ((msg
->flags
& ~(I2C_M_TEN
| I2C_M_RD
)) != 0)
210 /* Only 1-8 byte transfers can be offloaded */
211 if (msg
->len
< 1 || msg
->len
> 8)
214 /* Build transaction */
215 ctrl_reg
= MV64XXX_I2C_BRIDGE_CONTROL_ENABLE
|
216 (msg
->addr
<< MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT
);
218 if ((msg
->flags
& I2C_M_TEN
) != 0)
219 ctrl_reg
|= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT
;
221 if ((msg
->flags
& I2C_M_RD
) == 0) {
222 u8 local_buf
[8] = { 0 };
224 memcpy(local_buf
, msg
->buf
, msg
->len
);
225 data_reg_lo
= cpu_to_le32(*((u32
*)local_buf
));
226 data_reg_hi
= cpu_to_le32(*((u32
*)(local_buf
+4)));
228 ctrl_reg
|= MV64XXX_I2C_BRIDGE_CONTROL_WR
|
229 (msg
->len
- 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT
;
232 drv_data
->reg_base
+ MV64XXX_I2C_REG_TX_DATA_LO
);
234 drv_data
->reg_base
+ MV64XXX_I2C_REG_TX_DATA_HI
);
237 ctrl_reg
|= MV64XXX_I2C_BRIDGE_CONTROL_RD
|
238 (msg
->len
- 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT
;
241 /* Execute transaction */
242 writel(ctrl_reg
, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_CONTROL
);
248 mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data
*drv_data
)
250 struct i2c_msg
*msg
= drv_data
->msg
;
252 if (msg
->flags
& I2C_M_RD
) {
253 u32 data_reg_lo
= readl(drv_data
->reg_base
+
254 MV64XXX_I2C_REG_RX_DATA_LO
);
255 u32 data_reg_hi
= readl(drv_data
->reg_base
+
256 MV64XXX_I2C_REG_RX_DATA_HI
);
257 u8 local_buf
[8] = { 0 };
259 *((u32
*)local_buf
) = le32_to_cpu(data_reg_lo
);
260 *((u32
*)(local_buf
+4)) = le32_to_cpu(data_reg_hi
);
261 memcpy(msg
->buf
, local_buf
, msg
->len
);
266 *****************************************************************************
268 * Finite State Machine & Interrupt Routines
270 *****************************************************************************
273 /* Reset hardware and initialize FSM */
275 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data
*drv_data
)
277 if (drv_data
->offload_enabled
) {
278 writel(0, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_CONTROL
);
279 writel(0, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_TIMING
);
280 writel(0, drv_data
->reg_base
+
281 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE
);
282 writel(0, drv_data
->reg_base
+
283 MV64XXX_I2C_REG_BRIDGE_INTR_MASK
);
286 writel(0, drv_data
->reg_base
+ drv_data
->reg_offsets
.soft_reset
);
287 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data
->freq_m
) | MV64XXX_I2C_BAUD_DIV_N(drv_data
->freq_n
),
288 drv_data
->reg_base
+ drv_data
->reg_offsets
.clock
);
289 writel(0, drv_data
->reg_base
+ drv_data
->reg_offsets
.addr
);
290 writel(0, drv_data
->reg_base
+ drv_data
->reg_offsets
.ext_addr
);
291 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN
| MV64XXX_I2C_REG_CONTROL_STOP
,
292 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
293 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
297 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data
*drv_data
, u32 status
)
300 * If state is idle, then this is likely the remnants of an old
301 * operation that driver has given up on or the user has killed.
302 * If so, issue the stop condition and go to idle.
304 if (drv_data
->state
== MV64XXX_I2C_STATE_IDLE
) {
305 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
309 /* The status from the ctlr [mostly] tells us what to do next */
311 /* Start condition interrupt */
312 case MV64XXX_I2C_STATUS_MAST_START
: /* 0x08 */
313 case MV64XXX_I2C_STATUS_MAST_REPEAT_START
: /* 0x10 */
314 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_ADDR_1
;
315 drv_data
->state
= MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK
;
318 /* Performing a write */
319 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK
: /* 0x18 */
320 if (drv_data
->msg
->flags
& I2C_M_TEN
) {
321 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_ADDR_2
;
323 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK
;
327 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK
: /* 0xd0 */
328 case MV64XXX_I2C_STATUS_MAST_WR_ACK
: /* 0x28 */
329 if ((drv_data
->bytes_left
== 0)
330 || (drv_data
->aborting
331 && (drv_data
->byte_posn
!= 0))) {
332 if (drv_data
->send_stop
|| drv_data
->aborting
) {
333 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
334 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
337 MV64XXX_I2C_ACTION_SEND_RESTART
;
339 MV64XXX_I2C_STATE_WAITING_FOR_RESTART
;
342 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_DATA
;
344 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK
;
345 drv_data
->bytes_left
--;
349 /* Performing a read */
350 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK
: /* 40 */
351 if (drv_data
->msg
->flags
& I2C_M_TEN
) {
352 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_ADDR_2
;
354 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK
;
358 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK
: /* 0xe0 */
359 if (drv_data
->bytes_left
== 0) {
360 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
361 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
365 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK
: /* 0x50 */
366 if (status
!= MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK
)
367 drv_data
->action
= MV64XXX_I2C_ACTION_CONTINUE
;
369 drv_data
->action
= MV64XXX_I2C_ACTION_RCV_DATA
;
370 drv_data
->bytes_left
--;
372 drv_data
->state
= MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA
;
374 if ((drv_data
->bytes_left
== 1) || drv_data
->aborting
)
375 drv_data
->cntl_bits
&= ~MV64XXX_I2C_REG_CONTROL_ACK
;
378 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK
: /* 0x58 */
379 drv_data
->action
= MV64XXX_I2C_ACTION_RCV_DATA_STOP
;
380 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
383 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK
: /* 0x20 */
384 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK
: /* 30 */
385 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK
: /* 48 */
386 /* Doesn't seem to be a device at other end */
387 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
388 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
389 drv_data
->rc
= -ENXIO
;
392 case MV64XXX_I2C_STATUS_OFFLOAD_OK
:
393 if (drv_data
->send_stop
|| drv_data
->aborting
) {
394 drv_data
->action
= MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP
;
395 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
397 drv_data
->action
= MV64XXX_I2C_ACTION_OFFLOAD_RESTART
;
398 drv_data
->state
= MV64XXX_I2C_STATE_WAITING_FOR_RESTART
;
403 dev_err(&drv_data
->adapter
.dev
,
404 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
405 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
406 drv_data
->state
, status
, drv_data
->msg
->addr
,
407 drv_data
->msg
->flags
);
408 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
409 mv64xxx_i2c_hw_init(drv_data
);
414 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data
*drv_data
)
416 drv_data
->msg
= drv_data
->msgs
;
417 drv_data
->byte_posn
= 0;
418 drv_data
->bytes_left
= drv_data
->msg
->len
;
419 drv_data
->aborting
= 0;
422 /* Can we offload this msg ? */
423 if (mv64xxx_i2c_offload_msg(drv_data
) < 0) {
424 /* No, switch to standard path */
425 mv64xxx_i2c_prepare_for_io(drv_data
, drv_data
->msgs
);
426 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_START
,
427 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
432 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data
*drv_data
)
434 switch(drv_data
->action
) {
435 case MV64XXX_I2C_ACTION_OFFLOAD_RESTART
:
436 mv64xxx_i2c_update_offload_data(drv_data
);
437 writel(0, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_CONTROL
);
438 writel(0, drv_data
->reg_base
+
439 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE
);
441 case MV64XXX_I2C_ACTION_SEND_RESTART
:
442 /* We should only get here if we have further messages */
443 BUG_ON(drv_data
->num_msgs
== 0);
446 drv_data
->num_msgs
--;
447 mv64xxx_i2c_send_start(drv_data
);
449 if (drv_data
->errata_delay
)
453 * We're never at the start of the message here, and by this
454 * time it's already too late to do any protocol mangling.
455 * Thankfully, do not advertise support for that feature.
457 drv_data
->send_stop
= drv_data
->num_msgs
== 1;
460 case MV64XXX_I2C_ACTION_CONTINUE
:
461 writel(drv_data
->cntl_bits
,
462 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
465 case MV64XXX_I2C_ACTION_SEND_ADDR_1
:
466 writel(drv_data
->addr1
,
467 drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
468 writel(drv_data
->cntl_bits
,
469 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
472 case MV64XXX_I2C_ACTION_SEND_ADDR_2
:
473 writel(drv_data
->addr2
,
474 drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
475 writel(drv_data
->cntl_bits
,
476 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
479 case MV64XXX_I2C_ACTION_SEND_DATA
:
480 writel(drv_data
->msg
->buf
[drv_data
->byte_posn
++],
481 drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
482 writel(drv_data
->cntl_bits
,
483 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
486 case MV64XXX_I2C_ACTION_RCV_DATA
:
487 drv_data
->msg
->buf
[drv_data
->byte_posn
++] =
488 readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
489 writel(drv_data
->cntl_bits
,
490 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
493 case MV64XXX_I2C_ACTION_RCV_DATA_STOP
:
494 drv_data
->msg
->buf
[drv_data
->byte_posn
++] =
495 readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
496 drv_data
->cntl_bits
&= ~MV64XXX_I2C_REG_CONTROL_INTEN
;
497 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_STOP
,
498 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
500 if (drv_data
->errata_delay
)
503 wake_up(&drv_data
->waitq
);
506 case MV64XXX_I2C_ACTION_INVALID
:
508 dev_err(&drv_data
->adapter
.dev
,
509 "mv64xxx_i2c_do_action: Invalid action: %d\n",
514 case MV64XXX_I2C_ACTION_SEND_STOP
:
515 drv_data
->cntl_bits
&= ~MV64XXX_I2C_REG_CONTROL_INTEN
;
516 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_STOP
,
517 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
519 wake_up(&drv_data
->waitq
);
522 case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP
:
523 mv64xxx_i2c_update_offload_data(drv_data
);
524 writel(0, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_CONTROL
);
525 writel(0, drv_data
->reg_base
+
526 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE
);
528 wake_up(&drv_data
->waitq
);
534 mv64xxx_i2c_intr(int irq
, void *dev_id
)
536 struct mv64xxx_i2c_data
*drv_data
= dev_id
;
539 irqreturn_t rc
= IRQ_NONE
;
541 spin_lock_irqsave(&drv_data
->lock
, flags
);
543 if (drv_data
->offload_enabled
) {
544 while (readl(drv_data
->reg_base
+
545 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE
)) {
546 int reg_status
= readl(drv_data
->reg_base
+
547 MV64XXX_I2C_REG_BRIDGE_STATUS
);
548 if (reg_status
& MV64XXX_I2C_BRIDGE_STATUS_ERROR
)
549 status
= MV64XXX_I2C_STATUS_OFFLOAD_ERROR
;
551 status
= MV64XXX_I2C_STATUS_OFFLOAD_OK
;
552 mv64xxx_i2c_fsm(drv_data
, status
);
553 mv64xxx_i2c_do_action(drv_data
);
557 while (readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.control
) &
558 MV64XXX_I2C_REG_CONTROL_IFLG
) {
559 status
= readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.status
);
560 mv64xxx_i2c_fsm(drv_data
, status
);
561 mv64xxx_i2c_do_action(drv_data
);
563 if (drv_data
->irq_clear_inverted
)
564 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_IFLG
,
565 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
569 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
575 *****************************************************************************
577 * I2C Msg Execution Routines
579 *****************************************************************************
582 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data
*drv_data
)
588 time_left
= wait_event_timeout(drv_data
->waitq
,
589 !drv_data
->block
, drv_data
->adapter
.timeout
);
591 spin_lock_irqsave(&drv_data
->lock
, flags
);
592 if (!time_left
) { /* Timed out */
593 drv_data
->rc
= -ETIMEDOUT
;
595 } else if (time_left
< 0) { /* Interrupted/Error */
596 drv_data
->rc
= time_left
; /* errno value */
600 if (abort
&& drv_data
->block
) {
601 drv_data
->aborting
= 1;
602 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
604 time_left
= wait_event_timeout(drv_data
->waitq
,
605 !drv_data
->block
, drv_data
->adapter
.timeout
);
607 if ((time_left
<= 0) && drv_data
->block
) {
608 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
609 dev_err(&drv_data
->adapter
.dev
,
610 "mv64xxx: I2C bus locked, block: %d, "
611 "time_left: %d\n", drv_data
->block
,
613 mv64xxx_i2c_hw_init(drv_data
);
616 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
620 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data
*drv_data
, struct i2c_msg
*msg
,
625 spin_lock_irqsave(&drv_data
->lock
, flags
);
627 drv_data
->state
= MV64XXX_I2C_STATE_WAITING_FOR_START_COND
;
629 drv_data
->send_stop
= is_last
;
631 mv64xxx_i2c_send_start(drv_data
);
632 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
634 mv64xxx_i2c_wait_for_completion(drv_data
);
639 *****************************************************************************
641 * I2C Core Support Routines (Interface to higher level I2C code)
643 *****************************************************************************
646 mv64xxx_i2c_functionality(struct i2c_adapter
*adap
)
648 return I2C_FUNC_I2C
| I2C_FUNC_10BIT_ADDR
| I2C_FUNC_SMBUS_EMUL
;
652 mv64xxx_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
654 struct mv64xxx_i2c_data
*drv_data
= i2c_get_adapdata(adap
);
657 BUG_ON(drv_data
->msgs
!= NULL
);
658 drv_data
->msgs
= msgs
;
659 drv_data
->num_msgs
= num
;
661 rc
= mv64xxx_i2c_execute_msg(drv_data
, &msgs
[0], num
== 1);
665 drv_data
->num_msgs
= 0;
666 drv_data
->msgs
= NULL
;
671 static const struct i2c_algorithm mv64xxx_i2c_algo
= {
672 .master_xfer
= mv64xxx_i2c_xfer
,
673 .functionality
= mv64xxx_i2c_functionality
,
677 *****************************************************************************
679 * Driver Interface & Early Init Routines
681 *****************************************************************************
683 static const struct of_device_id mv64xxx_i2c_of_match_table
[] = {
684 { .compatible
= "allwinner,sun4i-a10-i2c", .data
= &mv64xxx_i2c_regs_sun4i
},
685 { .compatible
= "allwinner,sun6i-a31-i2c", .data
= &mv64xxx_i2c_regs_sun4i
},
686 { .compatible
= "marvell,mv64xxx-i2c", .data
= &mv64xxx_i2c_regs_mv64xxx
},
687 { .compatible
= "marvell,mv78230-i2c", .data
= &mv64xxx_i2c_regs_mv64xxx
},
688 { .compatible
= "marvell,mv78230-a0-i2c", .data
= &mv64xxx_i2c_regs_mv64xxx
},
691 MODULE_DEVICE_TABLE(of
, mv64xxx_i2c_of_match_table
);
694 #ifdef CONFIG_HAVE_CLK
696 mv64xxx_calc_freq(const int tclk
, const int n
, const int m
)
698 return tclk
/ (10 * (m
+ 1) * (2 << n
));
702 mv64xxx_find_baud_factors(const u32 req_freq
, const u32 tclk
, u32
*best_n
,
705 int freq
, delta
, best_delta
= INT_MAX
;
708 for (n
= 0; n
<= 7; n
++)
709 for (m
= 0; m
<= 15; m
++) {
710 freq
= mv64xxx_calc_freq(tclk
, n
, m
);
711 delta
= req_freq
- freq
;
712 if (delta
>= 0 && delta
< best_delta
) {
720 if (best_delta
== INT_MAX
)
724 #endif /* CONFIG_HAVE_CLK */
727 mv64xxx_of_config(struct mv64xxx_i2c_data
*drv_data
,
730 /* CLK is mandatory when using DT to describe the i2c bus. We
731 * need to know tclk in order to calculate bus clock
734 #if !defined(CONFIG_HAVE_CLK)
735 /* Have OF but no CLK */
738 const struct of_device_id
*device
;
739 struct device_node
*np
= dev
->of_node
;
743 if (IS_ERR(drv_data
->clk
)) {
747 tclk
= clk_get_rate(drv_data
->clk
);
749 rc
= of_property_read_u32(np
, "clock-frequency", &bus_freq
);
751 bus_freq
= 100000; /* 100kHz by default */
753 if (!mv64xxx_find_baud_factors(bus_freq
, tclk
,
754 &drv_data
->freq_n
, &drv_data
->freq_m
)) {
758 drv_data
->irq
= irq_of_parse_and_map(np
, 0);
760 drv_data
->rstc
= devm_reset_control_get_optional(dev
, NULL
);
761 if (IS_ERR(drv_data
->rstc
)) {
762 if (PTR_ERR(drv_data
->rstc
) == -EPROBE_DEFER
) {
767 reset_control_deassert(drv_data
->rstc
);
770 /* Its not yet defined how timeouts will be specified in device tree.
771 * So hard code the value to 1 second.
773 drv_data
->adapter
.timeout
= HZ
;
775 device
= of_match_device(mv64xxx_i2c_of_match_table
, dev
);
779 memcpy(&drv_data
->reg_offsets
, device
->data
, sizeof(drv_data
->reg_offsets
));
782 * For controllers embedded in new SoCs activate the
783 * Transaction Generator support and the errata fix.
785 if (of_device_is_compatible(np
, "marvell,mv78230-i2c")) {
786 drv_data
->offload_enabled
= true;
787 drv_data
->errata_delay
= true;
790 if (of_device_is_compatible(np
, "marvell,mv78230-a0-i2c")) {
791 drv_data
->offload_enabled
= false;
792 drv_data
->errata_delay
= true;
795 if (of_device_is_compatible(np
, "allwinner,sun6i-a31-i2c"))
796 drv_data
->irq_clear_inverted
= true;
802 #else /* CONFIG_OF */
804 mv64xxx_of_config(struct mv64xxx_i2c_data
*drv_data
,
809 #endif /* CONFIG_OF */
812 mv64xxx_i2c_probe(struct platform_device
*pd
)
814 struct mv64xxx_i2c_data
*drv_data
;
815 struct mv64xxx_i2c_pdata
*pdata
= dev_get_platdata(&pd
->dev
);
819 if ((!pdata
&& !pd
->dev
.of_node
))
822 drv_data
= devm_kzalloc(&pd
->dev
, sizeof(struct mv64xxx_i2c_data
),
827 r
= platform_get_resource(pd
, IORESOURCE_MEM
, 0);
828 drv_data
->reg_base
= devm_ioremap_resource(&pd
->dev
, r
);
829 if (IS_ERR(drv_data
->reg_base
))
830 return PTR_ERR(drv_data
->reg_base
);
832 strlcpy(drv_data
->adapter
.name
, MV64XXX_I2C_CTLR_NAME
" adapter",
833 sizeof(drv_data
->adapter
.name
));
835 init_waitqueue_head(&drv_data
->waitq
);
836 spin_lock_init(&drv_data
->lock
);
838 #if defined(CONFIG_HAVE_CLK)
839 /* Not all platforms have a clk */
840 drv_data
->clk
= devm_clk_get(&pd
->dev
, NULL
);
841 if (!IS_ERR(drv_data
->clk
)) {
842 clk_prepare(drv_data
->clk
);
843 clk_enable(drv_data
->clk
);
847 drv_data
->freq_m
= pdata
->freq_m
;
848 drv_data
->freq_n
= pdata
->freq_n
;
849 drv_data
->irq
= platform_get_irq(pd
, 0);
850 drv_data
->adapter
.timeout
= msecs_to_jiffies(pdata
->timeout
);
851 drv_data
->offload_enabled
= false;
852 memcpy(&drv_data
->reg_offsets
, &mv64xxx_i2c_regs_mv64xxx
, sizeof(drv_data
->reg_offsets
));
853 } else if (pd
->dev
.of_node
) {
854 rc
= mv64xxx_of_config(drv_data
, &pd
->dev
);
858 if (drv_data
->irq
< 0) {
863 drv_data
->adapter
.dev
.parent
= &pd
->dev
;
864 drv_data
->adapter
.algo
= &mv64xxx_i2c_algo
;
865 drv_data
->adapter
.owner
= THIS_MODULE
;
866 drv_data
->adapter
.class = I2C_CLASS_DEPRECATED
;
867 drv_data
->adapter
.nr
= pd
->id
;
868 drv_data
->adapter
.dev
.of_node
= pd
->dev
.of_node
;
869 platform_set_drvdata(pd
, drv_data
);
870 i2c_set_adapdata(&drv_data
->adapter
, drv_data
);
872 mv64xxx_i2c_hw_init(drv_data
);
874 rc
= request_irq(drv_data
->irq
, mv64xxx_i2c_intr
, 0,
875 MV64XXX_I2C_CTLR_NAME
, drv_data
);
877 dev_err(&drv_data
->adapter
.dev
,
878 "mv64xxx: Can't register intr handler irq%d: %d\n",
881 } else if ((rc
= i2c_add_numbered_adapter(&drv_data
->adapter
)) != 0) {
882 dev_err(&drv_data
->adapter
.dev
,
883 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc
);
890 free_irq(drv_data
->irq
, drv_data
);
892 if (!IS_ERR_OR_NULL(drv_data
->rstc
))
893 reset_control_assert(drv_data
->rstc
);
895 #if defined(CONFIG_HAVE_CLK)
896 /* Not all platforms have a clk */
897 if (!IS_ERR(drv_data
->clk
)) {
898 clk_disable(drv_data
->clk
);
899 clk_unprepare(drv_data
->clk
);
906 mv64xxx_i2c_remove(struct platform_device
*dev
)
908 struct mv64xxx_i2c_data
*drv_data
= platform_get_drvdata(dev
);
910 i2c_del_adapter(&drv_data
->adapter
);
911 free_irq(drv_data
->irq
, drv_data
);
912 if (!IS_ERR_OR_NULL(drv_data
->rstc
))
913 reset_control_assert(drv_data
->rstc
);
914 #if defined(CONFIG_HAVE_CLK)
915 /* Not all platforms have a clk */
916 if (!IS_ERR(drv_data
->clk
)) {
917 clk_disable(drv_data
->clk
);
918 clk_unprepare(drv_data
->clk
);
925 static struct platform_driver mv64xxx_i2c_driver
= {
926 .probe
= mv64xxx_i2c_probe
,
927 .remove
= mv64xxx_i2c_remove
,
929 .owner
= THIS_MODULE
,
930 .name
= MV64XXX_I2C_CTLR_NAME
,
931 .of_match_table
= mv64xxx_i2c_of_match_table
,
935 module_platform_driver(mv64xxx_i2c_driver
);
937 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
938 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
939 MODULE_LICENSE("GPL");