2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/atomic.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <linux/i2c.h>
26 #include <asm/octeon/octeon.h>
28 #define DRV_NAME "i2c-octeon"
30 /* Register offsets */
33 #define SW_TWSI_EXT 0x18
35 /* Controller command patterns */
36 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */
37 #define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
38 #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
39 #define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
40 #define SW_TWSI_SIZE_SHIFT 52
41 #define SW_TWSI_ADDR_SHIFT 40
42 #define SW_TWSI_IA_SHIFT 32 /* Internal address */
44 /* Controller opcode word (bits 60:57) */
45 #define SW_TWSI_OP_SHIFT 57
46 #define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
47 #define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
48 #define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
49 #define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
50 #define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
51 #define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
53 /* Controller extended opcode word (bits 34:32) */
54 #define SW_TWSI_EOP_SHIFT 32
55 #define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
56 #define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
57 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
58 #define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
59 #define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
61 /* Controller command and status bits */
62 #define TWSI_CTL_CE 0x80 /* High level controller enable */
63 #define TWSI_CTL_ENAB 0x40 /* Bus enable */
64 #define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
65 #define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
66 #define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
67 #define TWSI_CTL_AAK 0x04 /* Assert ACK */
70 #define STAT_ERROR 0x00
71 #define STAT_START 0x08
72 #define STAT_REP_START 0x10
73 #define STAT_TXADDR_ACK 0x18
74 #define STAT_TXADDR_NAK 0x20
75 #define STAT_TXDATA_ACK 0x28
76 #define STAT_TXDATA_NAK 0x30
77 #define STAT_LOST_ARB_38 0x38
78 #define STAT_RXADDR_ACK 0x40
79 #define STAT_RXADDR_NAK 0x48
80 #define STAT_RXDATA_ACK 0x50
81 #define STAT_RXDATA_NAK 0x58
82 #define STAT_SLAVE_60 0x60
83 #define STAT_LOST_ARB_68 0x68
84 #define STAT_SLAVE_70 0x70
85 #define STAT_LOST_ARB_78 0x78
86 #define STAT_SLAVE_80 0x80
87 #define STAT_SLAVE_88 0x88
88 #define STAT_GENDATA_ACK 0x90
89 #define STAT_GENDATA_NAK 0x98
90 #define STAT_SLAVE_A0 0xA0
91 #define STAT_SLAVE_A8 0xA8
92 #define STAT_LOST_ARB_B0 0xB0
93 #define STAT_SLAVE_LOST 0xB8
94 #define STAT_SLAVE_NAK 0xC0
95 #define STAT_SLAVE_ACK 0xC8
96 #define STAT_AD2W_ACK 0xD0
97 #define STAT_AD2W_NAK 0xD8
98 #define STAT_IDLE 0xF8
100 /* TWSI_INT values */
101 #define TWSI_INT_ST_INT BIT_ULL(0)
102 #define TWSI_INT_TS_INT BIT_ULL(1)
103 #define TWSI_INT_CORE_INT BIT_ULL(2)
104 #define TWSI_INT_ST_EN BIT_ULL(4)
105 #define TWSI_INT_TS_EN BIT_ULL(5)
106 #define TWSI_INT_CORE_EN BIT_ULL(6)
107 #define TWSI_INT_SDA_OVR BIT_ULL(8)
108 #define TWSI_INT_SCL_OVR BIT_ULL(9)
109 #define TWSI_INT_SDA BIT_ULL(10)
110 #define TWSI_INT_SCL BIT_ULL(11)
112 #define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
115 wait_queue_head_t queue
;
116 struct i2c_adapter adap
;
118 int hlc_irq
; /* For cn7890 only */
121 void __iomem
*twsi_base
;
124 bool broken_irq_mode
;
125 bool broken_irq_check
;
126 void (*int_enable
)(struct octeon_i2c
*);
127 void (*int_disable
)(struct octeon_i2c
*);
128 void (*hlc_int_enable
)(struct octeon_i2c
*);
129 void (*hlc_int_disable
)(struct octeon_i2c
*);
130 atomic_t int_enable_cnt
;
131 atomic_t hlc_int_enable_cnt
;
134 static void octeon_i2c_writeq_flush(u64 val
, void __iomem
*addr
)
136 __raw_writeq(val
, addr
);
137 __raw_readq(addr
); /* wait for write to land */
141 * octeon_i2c_reg_write - write an I2C core register
142 * @i2c: The struct octeon_i2c
143 * @eop_reg: Register selector
144 * @data: Value to be written
146 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
148 static void octeon_i2c_reg_write(struct octeon_i2c
*i2c
, u64 eop_reg
, u8 data
)
152 __raw_writeq(SW_TWSI_V
| eop_reg
| data
, i2c
->twsi_base
+ SW_TWSI
);
154 tmp
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
155 } while ((tmp
& SW_TWSI_V
) != 0);
158 #define octeon_i2c_ctl_write(i2c, val) \
159 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
160 #define octeon_i2c_data_write(i2c, val) \
161 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
164 * octeon_i2c_reg_read - read lower bits of an I2C core register
165 * @i2c: The struct octeon_i2c
166 * @eop_reg: Register selector
170 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
172 static u8
octeon_i2c_reg_read(struct octeon_i2c
*i2c
, u64 eop_reg
)
176 __raw_writeq(SW_TWSI_V
| eop_reg
| SW_TWSI_R
, i2c
->twsi_base
+ SW_TWSI
);
178 tmp
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
179 } while ((tmp
& SW_TWSI_V
) != 0);
184 #define octeon_i2c_ctl_read(i2c) \
185 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
186 #define octeon_i2c_data_read(i2c) \
187 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
188 #define octeon_i2c_stat_read(i2c) \
189 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
192 * octeon_i2c_read_int - read the TWSI_INT register
193 * @i2c: The struct octeon_i2c
195 * Returns the value of the register.
197 static u64
octeon_i2c_read_int(struct octeon_i2c
*i2c
)
199 return __raw_readq(i2c
->twsi_base
+ TWSI_INT
);
203 * octeon_i2c_write_int - write the TWSI_INT register
204 * @i2c: The struct octeon_i2c
205 * @data: Value to be written
207 static void octeon_i2c_write_int(struct octeon_i2c
*i2c
, u64 data
)
209 octeon_i2c_writeq_flush(data
, i2c
->twsi_base
+ TWSI_INT
);
213 * octeon_i2c_int_enable - enable the CORE interrupt
214 * @i2c: The struct octeon_i2c
216 * The interrupt will be asserted when there is non-STAT_IDLE state in
217 * the SW_TWSI_EOP_TWSI_STAT register.
219 static void octeon_i2c_int_enable(struct octeon_i2c
*i2c
)
221 octeon_i2c_write_int(i2c
, TWSI_INT_CORE_EN
);
224 /* disable the CORE interrupt */
225 static void octeon_i2c_int_disable(struct octeon_i2c
*i2c
)
227 /* clear TS/ST/IFLG events */
228 octeon_i2c_write_int(i2c
, 0);
232 * octeon_i2c_int_enable78 - enable the CORE interrupt
233 * @i2c: The struct octeon_i2c
235 * The interrupt will be asserted when there is non-STAT_IDLE state in the
236 * SW_TWSI_EOP_TWSI_STAT register.
238 static void octeon_i2c_int_enable78(struct octeon_i2c
*i2c
)
240 atomic_inc_return(&i2c
->int_enable_cnt
);
241 enable_irq(i2c
->irq
);
244 static void __octeon_i2c_irq_disable(atomic_t
*cnt
, int irq
)
249 * The interrupt can be disabled in two places, but we only
250 * want to make the disable_irq_nosync() call once, so keep
251 * track with the atomic variable.
253 count
= atomic_dec_if_positive(cnt
);
255 disable_irq_nosync(irq
);
258 /* disable the CORE interrupt */
259 static void octeon_i2c_int_disable78(struct octeon_i2c
*i2c
)
261 __octeon_i2c_irq_disable(&i2c
->int_enable_cnt
, i2c
->irq
);
265 * octeon_i2c_hlc_int_enable78 - enable the ST interrupt
266 * @i2c: The struct octeon_i2c
268 * The interrupt will be asserted when there is non-STAT_IDLE state in
269 * the SW_TWSI_EOP_TWSI_STAT register.
271 static void octeon_i2c_hlc_int_enable78(struct octeon_i2c
*i2c
)
273 atomic_inc_return(&i2c
->hlc_int_enable_cnt
);
274 enable_irq(i2c
->hlc_irq
);
277 /* disable the ST interrupt */
278 static void octeon_i2c_hlc_int_disable78(struct octeon_i2c
*i2c
)
280 __octeon_i2c_irq_disable(&i2c
->hlc_int_enable_cnt
, i2c
->hlc_irq
);
284 * Cleanup low-level state & enable high-level controller.
286 static void octeon_i2c_hlc_enable(struct octeon_i2c
*i2c
)
291 if (i2c
->hlc_enabled
)
293 i2c
->hlc_enabled
= true;
296 val
= octeon_i2c_ctl_read(i2c
);
297 if (!(val
& (TWSI_CTL_STA
| TWSI_CTL_STP
)))
300 /* clear IFLG event */
301 if (val
& TWSI_CTL_IFLG
)
302 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
);
305 pr_err("%s: giving up\n", __func__
);
309 /* spin until any start/stop has finished */
312 octeon_i2c_ctl_write(i2c
, TWSI_CTL_CE
| TWSI_CTL_AAK
| TWSI_CTL_ENAB
);
315 static void octeon_i2c_hlc_disable(struct octeon_i2c
*i2c
)
317 if (!i2c
->hlc_enabled
)
320 i2c
->hlc_enabled
= false;
321 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
);
324 /* interrupt service routine */
325 static irqreturn_t
octeon_i2c_isr(int irq
, void *dev_id
)
327 struct octeon_i2c
*i2c
= dev_id
;
329 i2c
->int_disable(i2c
);
330 wake_up(&i2c
->queue
);
335 /* HLC interrupt service routine */
336 static irqreturn_t
octeon_i2c_hlc_isr78(int irq
, void *dev_id
)
338 struct octeon_i2c
*i2c
= dev_id
;
340 i2c
->hlc_int_disable(i2c
);
341 wake_up(&i2c
->queue
);
346 static bool octeon_i2c_test_iflg(struct octeon_i2c
*i2c
)
348 return (octeon_i2c_ctl_read(i2c
) & TWSI_CTL_IFLG
);
351 static bool octeon_i2c_test_ready(struct octeon_i2c
*i2c
, bool *first
)
353 if (octeon_i2c_test_iflg(i2c
))
362 * IRQ has signaled an event but IFLG hasn't changed.
363 * Sleep and retry once.
365 usleep_range(I2C_OCTEON_EVENT_WAIT
, 2 * I2C_OCTEON_EVENT_WAIT
);
366 return octeon_i2c_test_iflg(i2c
);
370 * octeon_i2c_wait - wait for the IFLG to be set
371 * @i2c: The struct octeon_i2c
373 * Returns 0 on success, otherwise a negative errno.
375 static int octeon_i2c_wait(struct octeon_i2c
*i2c
)
381 * Some chip revisions don't assert the irq in the interrupt
382 * controller. So we must poll for the IFLG change.
384 if (i2c
->broken_irq_mode
) {
385 u64 end
= get_jiffies_64() + i2c
->adap
.timeout
;
387 while (!octeon_i2c_test_iflg(i2c
) &&
388 time_before64(get_jiffies_64(), end
))
389 usleep_range(I2C_OCTEON_EVENT_WAIT
/ 2, I2C_OCTEON_EVENT_WAIT
);
391 return octeon_i2c_test_iflg(i2c
) ? 0 : -ETIMEDOUT
;
394 i2c
->int_enable(i2c
);
395 time_left
= wait_event_timeout(i2c
->queue
, octeon_i2c_test_ready(i2c
, &first
),
397 i2c
->int_disable(i2c
);
399 if (i2c
->broken_irq_check
&& !time_left
&&
400 octeon_i2c_test_iflg(i2c
)) {
401 dev_err(i2c
->dev
, "broken irq connection detected, switching to polling mode.\n");
402 i2c
->broken_irq_mode
= true;
412 static int octeon_i2c_check_status(struct octeon_i2c
*i2c
, int final_read
)
414 u8 stat
= octeon_i2c_stat_read(i2c
);
417 /* Everything is fine */
420 case STAT_RXADDR_ACK
:
421 case STAT_TXADDR_ACK
:
422 case STAT_TXDATA_ACK
:
425 /* ACK allowed on pre-terminal bytes only */
426 case STAT_RXDATA_ACK
:
431 /* NAK allowed on terminal byte only */
432 case STAT_RXDATA_NAK
:
437 /* Arbitration lost */
438 case STAT_LOST_ARB_38
:
439 case STAT_LOST_ARB_68
:
440 case STAT_LOST_ARB_78
:
441 case STAT_LOST_ARB_B0
:
444 /* Being addressed as slave, should back off & listen */
447 case STAT_GENDATA_ACK
:
448 case STAT_GENDATA_NAK
:
451 /* Core busy as slave */
456 case STAT_SLAVE_LOST
:
461 case STAT_TXDATA_NAK
:
463 case STAT_TXADDR_NAK
:
464 case STAT_RXADDR_NAK
:
468 dev_err(i2c
->dev
, "unhandled state: %d\n", stat
);
473 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c
*i2c
)
475 return (__raw_readq(i2c
->twsi_base
+ SW_TWSI
) & SW_TWSI_V
) == 0;
478 static bool octeon_i2c_hlc_test_ready(struct octeon_i2c
*i2c
, bool *first
)
480 /* check if valid bit is cleared */
481 if (octeon_i2c_hlc_test_valid(i2c
))
490 * IRQ has signaled an event but valid bit isn't cleared.
491 * Sleep and retry once.
493 usleep_range(I2C_OCTEON_EVENT_WAIT
, 2 * I2C_OCTEON_EVENT_WAIT
);
494 return octeon_i2c_hlc_test_valid(i2c
);
497 static void octeon_i2c_hlc_int_enable(struct octeon_i2c
*i2c
)
499 octeon_i2c_write_int(i2c
, TWSI_INT_ST_EN
);
502 static void octeon_i2c_hlc_int_clear(struct octeon_i2c
*i2c
)
504 /* clear ST/TS events, listen for neither */
505 octeon_i2c_write_int(i2c
, TWSI_INT_ST_INT
| TWSI_INT_TS_INT
);
509 * octeon_i2c_hlc_wait - wait for an HLC operation to complete
510 * @i2c: The struct octeon_i2c
512 * Returns 0 on success, otherwise -ETIMEDOUT.
514 static int octeon_i2c_hlc_wait(struct octeon_i2c
*i2c
)
520 * Some cn38xx boards don't assert the irq in the interrupt
521 * controller. So we must poll for the valid bit change.
523 if (i2c
->broken_irq_mode
) {
524 u64 end
= get_jiffies_64() + i2c
->adap
.timeout
;
526 while (!octeon_i2c_hlc_test_valid(i2c
) &&
527 time_before64(get_jiffies_64(), end
))
528 usleep_range(I2C_OCTEON_EVENT_WAIT
/ 2, I2C_OCTEON_EVENT_WAIT
);
530 return octeon_i2c_hlc_test_valid(i2c
) ? 0 : -ETIMEDOUT
;
533 i2c
->hlc_int_enable(i2c
);
534 time_left
= wait_event_timeout(i2c
->queue
,
535 octeon_i2c_hlc_test_ready(i2c
, &first
),
537 i2c
->hlc_int_disable(i2c
);
539 octeon_i2c_hlc_int_clear(i2c
);
541 if (i2c
->broken_irq_check
&& !time_left
&&
542 octeon_i2c_hlc_test_valid(i2c
)) {
543 dev_err(i2c
->dev
, "broken irq connection detected, switching to polling mode.\n");
544 i2c
->broken_irq_mode
= true;
553 /* high-level-controller pure read of up to 8 bytes */
554 static int octeon_i2c_hlc_read(struct octeon_i2c
*i2c
, struct i2c_msg
*msgs
)
559 octeon_i2c_hlc_enable(i2c
);
560 octeon_i2c_hlc_int_clear(i2c
);
562 cmd
= SW_TWSI_V
| SW_TWSI_R
| SW_TWSI_SOVR
;
564 cmd
|= (u64
)(msgs
[0].len
- 1) << SW_TWSI_SIZE_SHIFT
;
566 cmd
|= (u64
)(msgs
[0].addr
& 0x7full
) << SW_TWSI_ADDR_SHIFT
;
568 if (msgs
[0].flags
& I2C_M_TEN
)
569 cmd
|= SW_TWSI_OP_10
;
573 octeon_i2c_writeq_flush(cmd
, i2c
->twsi_base
+ SW_TWSI
);
574 ret
= octeon_i2c_hlc_wait(i2c
);
578 cmd
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
579 if ((cmd
& SW_TWSI_R
) == 0)
582 for (i
= 0, j
= msgs
[0].len
- 1; i
< msgs
[0].len
&& i
< 4; i
++, j
--)
583 msgs
[0].buf
[j
] = (cmd
>> (8 * i
)) & 0xff;
585 if (msgs
[0].len
> 4) {
586 cmd
= __raw_readq(i2c
->twsi_base
+ SW_TWSI_EXT
);
587 for (i
= 0; i
< msgs
[0].len
- 4 && i
< 4; i
++, j
--)
588 msgs
[0].buf
[j
] = (cmd
>> (8 * i
)) & 0xff;
595 /* high-level-controller pure write of up to 8 bytes */
596 static int octeon_i2c_hlc_write(struct octeon_i2c
*i2c
, struct i2c_msg
*msgs
)
601 octeon_i2c_hlc_enable(i2c
);
602 octeon_i2c_hlc_int_clear(i2c
);
604 cmd
= SW_TWSI_V
| SW_TWSI_SOVR
;
606 cmd
|= (u64
)(msgs
[0].len
- 1) << SW_TWSI_SIZE_SHIFT
;
608 cmd
|= (u64
)(msgs
[0].addr
& 0x7full
) << SW_TWSI_ADDR_SHIFT
;
610 if (msgs
[0].flags
& I2C_M_TEN
)
611 cmd
|= SW_TWSI_OP_10
;
615 for (i
= 0, j
= msgs
[0].len
- 1; i
< msgs
[0].len
&& i
< 4; i
++, j
--)
616 cmd
|= (u64
)msgs
[0].buf
[j
] << (8 * i
);
618 if (msgs
[0].len
> 4) {
621 for (i
= 0; i
< msgs
[0].len
- 4 && i
< 4; i
++, j
--)
622 ext
|= (u64
)msgs
[0].buf
[j
] << (8 * i
);
623 octeon_i2c_writeq_flush(ext
, i2c
->twsi_base
+ SW_TWSI_EXT
);
626 octeon_i2c_writeq_flush(cmd
, i2c
->twsi_base
+ SW_TWSI
);
627 ret
= octeon_i2c_hlc_wait(i2c
);
631 cmd
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
632 if ((cmd
& SW_TWSI_R
) == 0)
635 ret
= octeon_i2c_check_status(i2c
, false);
641 /* high-level-controller composite write+read, msg0=addr, msg1=data */
642 static int octeon_i2c_hlc_comp_read(struct octeon_i2c
*i2c
, struct i2c_msg
*msgs
)
647 octeon_i2c_hlc_enable(i2c
);
649 cmd
= SW_TWSI_V
| SW_TWSI_R
| SW_TWSI_SOVR
;
651 cmd
|= (u64
)(msgs
[1].len
- 1) << SW_TWSI_SIZE_SHIFT
;
653 cmd
|= (u64
)(msgs
[0].addr
& 0x7full
) << SW_TWSI_ADDR_SHIFT
;
655 if (msgs
[0].flags
& I2C_M_TEN
)
656 cmd
|= SW_TWSI_OP_10_IA
;
658 cmd
|= SW_TWSI_OP_7_IA
;
660 if (msgs
[0].len
== 2) {
664 ext
= (u64
)msgs
[0].buf
[0] << SW_TWSI_IA_SHIFT
;
665 cmd
|= (u64
)msgs
[0].buf
[1] << SW_TWSI_IA_SHIFT
;
666 octeon_i2c_writeq_flush(ext
, i2c
->twsi_base
+ SW_TWSI_EXT
);
668 cmd
|= (u64
)msgs
[0].buf
[0] << SW_TWSI_IA_SHIFT
;
671 octeon_i2c_hlc_int_clear(i2c
);
672 octeon_i2c_writeq_flush(cmd
, i2c
->twsi_base
+ SW_TWSI
);
674 ret
= octeon_i2c_hlc_wait(i2c
);
678 cmd
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
679 if ((cmd
& SW_TWSI_R
) == 0)
682 for (i
= 0, j
= msgs
[1].len
- 1; i
< msgs
[1].len
&& i
< 4; i
++, j
--)
683 msgs
[1].buf
[j
] = (cmd
>> (8 * i
)) & 0xff;
685 if (msgs
[1].len
> 4) {
686 cmd
= __raw_readq(i2c
->twsi_base
+ SW_TWSI_EXT
);
687 for (i
= 0; i
< msgs
[1].len
- 4 && i
< 4; i
++, j
--)
688 msgs
[1].buf
[j
] = (cmd
>> (8 * i
)) & 0xff;
695 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
696 static int octeon_i2c_hlc_comp_write(struct octeon_i2c
*i2c
, struct i2c_msg
*msgs
)
698 bool set_ext
= false;
702 octeon_i2c_hlc_enable(i2c
);
704 cmd
= SW_TWSI_V
| SW_TWSI_SOVR
;
706 cmd
|= (u64
)(msgs
[1].len
- 1) << SW_TWSI_SIZE_SHIFT
;
708 cmd
|= (u64
)(msgs
[0].addr
& 0x7full
) << SW_TWSI_ADDR_SHIFT
;
710 if (msgs
[0].flags
& I2C_M_TEN
)
711 cmd
|= SW_TWSI_OP_10_IA
;
713 cmd
|= SW_TWSI_OP_7_IA
;
715 if (msgs
[0].len
== 2) {
717 ext
|= (u64
)msgs
[0].buf
[0] << SW_TWSI_IA_SHIFT
;
719 cmd
|= (u64
)msgs
[0].buf
[1] << SW_TWSI_IA_SHIFT
;
721 cmd
|= (u64
)msgs
[0].buf
[0] << SW_TWSI_IA_SHIFT
;
724 for (i
= 0, j
= msgs
[1].len
- 1; i
< msgs
[1].len
&& i
< 4; i
++, j
--)
725 cmd
|= (u64
)msgs
[1].buf
[j
] << (8 * i
);
727 if (msgs
[1].len
> 4) {
728 for (i
= 0; i
< msgs
[1].len
- 4 && i
< 4; i
++, j
--)
729 ext
|= (u64
)msgs
[1].buf
[j
] << (8 * i
);
733 octeon_i2c_writeq_flush(ext
, i2c
->twsi_base
+ SW_TWSI_EXT
);
735 octeon_i2c_hlc_int_clear(i2c
);
736 octeon_i2c_writeq_flush(cmd
, i2c
->twsi_base
+ SW_TWSI
);
738 ret
= octeon_i2c_hlc_wait(i2c
);
742 cmd
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
743 if ((cmd
& SW_TWSI_R
) == 0)
746 ret
= octeon_i2c_check_status(i2c
, false);
752 /* calculate and set clock divisors */
753 static void octeon_i2c_set_clock(struct octeon_i2c
*i2c
)
755 int tclk
, thp_base
, inc
, thp_idx
, mdiv_idx
, ndiv_idx
, foscl
, diff
;
756 int thp
= 0x18, mdiv
= 2, ndiv
= 0, delta_hz
= 1000000;
758 for (ndiv_idx
= 0; ndiv_idx
< 8 && delta_hz
!= 0; ndiv_idx
++) {
760 * An mdiv value of less than 2 seems to not work well
761 * with ds1337 RTCs, so we constrain it to larger values.
763 for (mdiv_idx
= 15; mdiv_idx
>= 2 && delta_hz
!= 0; mdiv_idx
--) {
765 * For given ndiv and mdiv values check the
766 * two closest thp values.
768 tclk
= i2c
->twsi_freq
* (mdiv_idx
+ 1) * 10;
769 tclk
*= (1 << ndiv_idx
);
770 thp_base
= (i2c
->sys_freq
/ (tclk
* 2)) - 1;
772 for (inc
= 0; inc
<= 1; inc
++) {
773 thp_idx
= thp_base
+ inc
;
774 if (thp_idx
< 5 || thp_idx
> 0xff)
777 foscl
= i2c
->sys_freq
/ (2 * (thp_idx
+ 1));
778 foscl
= foscl
/ (1 << ndiv_idx
);
779 foscl
= foscl
/ (mdiv_idx
+ 1) / 10;
780 diff
= abs(foscl
- i2c
->twsi_freq
);
781 if (diff
< delta_hz
) {
790 octeon_i2c_reg_write(i2c
, SW_TWSI_OP_TWSI_CLK
, thp
);
791 octeon_i2c_reg_write(i2c
, SW_TWSI_EOP_TWSI_CLKCTL
, (mdiv
<< 3) | ndiv
);
794 static int octeon_i2c_init_lowlevel(struct octeon_i2c
*i2c
)
799 /* reset controller */
800 octeon_i2c_reg_write(i2c
, SW_TWSI_EOP_TWSI_RST
, 0);
802 for (tries
= 10; tries
&& status
!= STAT_IDLE
; tries
--) {
804 status
= octeon_i2c_stat_read(i2c
);
805 if (status
== STAT_IDLE
)
809 if (status
!= STAT_IDLE
) {
810 dev_err(i2c
->dev
, "%s: TWSI_RST failed! (0x%x)\n",
815 /* toggle twice to force both teardowns */
816 octeon_i2c_hlc_enable(i2c
);
817 octeon_i2c_hlc_disable(i2c
);
821 static int octeon_i2c_recovery(struct octeon_i2c
*i2c
)
825 ret
= i2c_recover_bus(&i2c
->adap
);
827 /* recover failed, try hardware re-init */
828 ret
= octeon_i2c_init_lowlevel(i2c
);
833 * octeon_i2c_start - send START to the bus
834 * @i2c: The struct octeon_i2c
836 * Returns 0 on success, otherwise a negative errno.
838 static int octeon_i2c_start(struct octeon_i2c
*i2c
)
843 octeon_i2c_hlc_disable(i2c
);
845 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
| TWSI_CTL_STA
);
846 ret
= octeon_i2c_wait(i2c
);
850 stat
= octeon_i2c_stat_read(i2c
);
851 if (stat
== STAT_START
|| stat
== STAT_REP_START
)
852 /* START successful, bail out */
856 /* START failed, try to recover */
857 ret
= octeon_i2c_recovery(i2c
);
858 return (ret
) ? ret
: -EAGAIN
;
861 /* send STOP to the bus */
862 static void octeon_i2c_stop(struct octeon_i2c
*i2c
)
864 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
| TWSI_CTL_STP
);
868 * octeon_i2c_write - send data to the bus via low-level controller
869 * @i2c: The struct octeon_i2c
870 * @target: Target address
871 * @data: Pointer to the data to be sent
872 * @length: Length of the data
874 * The address is sent over the bus, then the data.
876 * Returns 0 on success, otherwise a negative errno.
878 static int octeon_i2c_write(struct octeon_i2c
*i2c
, int target
,
879 const u8
*data
, int length
)
883 octeon_i2c_data_write(i2c
, target
<< 1);
884 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
);
886 result
= octeon_i2c_wait(i2c
);
890 for (i
= 0; i
< length
; i
++) {
891 result
= octeon_i2c_check_status(i2c
, false);
895 octeon_i2c_data_write(i2c
, data
[i
]);
896 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
);
898 result
= octeon_i2c_wait(i2c
);
907 * octeon_i2c_read - receive data from the bus via low-level controller
908 * @i2c: The struct octeon_i2c
909 * @target: Target address
910 * @data: Pointer to the location to store the data
911 * @rlength: Length of the data
912 * @recv_len: flag for length byte
914 * The address is sent over the bus, then the data is read.
916 * Returns 0 on success, otherwise a negative errno.
918 static int octeon_i2c_read(struct octeon_i2c
*i2c
, int target
,
919 u8
*data
, u16
*rlength
, bool recv_len
)
921 int i
, result
, length
= *rlength
;
922 bool final_read
= false;
924 octeon_i2c_data_write(i2c
, (target
<< 1) | 1);
925 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
);
927 result
= octeon_i2c_wait(i2c
);
932 result
= octeon_i2c_check_status(i2c
, false);
936 for (i
= 0; i
< length
; i
++) {
938 * For the last byte to receive TWSI_CTL_AAK must not be set.
940 * A special case is I2C_M_RECV_LEN where we don't know the
941 * additional length yet. If recv_len is set we assume we're
942 * not reading the final byte and therefore need to set
945 if ((i
+ 1 == length
) && !(recv_len
&& i
== 0))
948 /* clear iflg to allow next event */
950 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
);
952 octeon_i2c_ctl_write(i2c
, TWSI_CTL_ENAB
| TWSI_CTL_AAK
);
954 result
= octeon_i2c_wait(i2c
);
958 data
[i
] = octeon_i2c_data_read(i2c
);
959 if (recv_len
&& i
== 0) {
960 if (data
[i
] > I2C_SMBUS_BLOCK_MAX
+ 1)
965 result
= octeon_i2c_check_status(i2c
, final_read
);
974 * octeon_i2c_xfer - The driver's master_xfer function
975 * @adap: Pointer to the i2c_adapter structure
976 * @msgs: Pointer to the messages to be processed
977 * @num: Length of the MSGS array
979 * Returns the number of messages processed, or a negative errno on failure.
981 static int octeon_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
,
984 struct octeon_i2c
*i2c
= i2c_get_adapdata(adap
);
988 if (msgs
[0].len
> 0 && msgs
[0].len
<= 8) {
989 if (msgs
[0].flags
& I2C_M_RD
)
990 ret
= octeon_i2c_hlc_read(i2c
, msgs
);
992 ret
= octeon_i2c_hlc_write(i2c
, msgs
);
995 } else if (num
== 2) {
996 if ((msgs
[0].flags
& I2C_M_RD
) == 0 &&
997 (msgs
[1].flags
& I2C_M_RECV_LEN
) == 0 &&
998 msgs
[0].len
> 0 && msgs
[0].len
<= 2 &&
999 msgs
[1].len
> 0 && msgs
[1].len
<= 8 &&
1000 msgs
[0].addr
== msgs
[1].addr
) {
1001 if (msgs
[1].flags
& I2C_M_RD
)
1002 ret
= octeon_i2c_hlc_comp_read(i2c
, msgs
);
1004 ret
= octeon_i2c_hlc_comp_write(i2c
, msgs
);
1009 for (i
= 0; ret
== 0 && i
< num
; i
++) {
1010 struct i2c_msg
*pmsg
= &msgs
[i
];
1012 /* zero-length messages are not supported */
1018 ret
= octeon_i2c_start(i2c
);
1022 if (pmsg
->flags
& I2C_M_RD
)
1023 ret
= octeon_i2c_read(i2c
, pmsg
->addr
, pmsg
->buf
,
1024 &pmsg
->len
, pmsg
->flags
& I2C_M_RECV_LEN
);
1026 ret
= octeon_i2c_write(i2c
, pmsg
->addr
, pmsg
->buf
,
1029 octeon_i2c_stop(i2c
);
1031 return (ret
!= 0) ? ret
: num
;
1034 static int octeon_i2c_get_scl(struct i2c_adapter
*adap
)
1036 struct octeon_i2c
*i2c
= i2c_get_adapdata(adap
);
1039 state
= octeon_i2c_read_int(i2c
);
1040 return state
& TWSI_INT_SCL
;
1043 static void octeon_i2c_set_scl(struct i2c_adapter
*adap
, int val
)
1045 struct octeon_i2c
*i2c
= i2c_get_adapdata(adap
);
1047 octeon_i2c_write_int(i2c
, TWSI_INT_SCL_OVR
);
1050 static int octeon_i2c_get_sda(struct i2c_adapter
*adap
)
1052 struct octeon_i2c
*i2c
= i2c_get_adapdata(adap
);
1055 state
= octeon_i2c_read_int(i2c
);
1056 return state
& TWSI_INT_SDA
;
1059 static void octeon_i2c_prepare_recovery(struct i2c_adapter
*adap
)
1061 struct octeon_i2c
*i2c
= i2c_get_adapdata(adap
);
1064 * The stop resets the state machine, does not _transmit_ STOP unless
1065 * engine was active.
1067 octeon_i2c_stop(i2c
);
1069 octeon_i2c_hlc_disable(i2c
);
1070 octeon_i2c_write_int(i2c
, 0);
1073 static void octeon_i2c_unprepare_recovery(struct i2c_adapter
*adap
)
1075 struct octeon_i2c
*i2c
= i2c_get_adapdata(adap
);
1077 octeon_i2c_write_int(i2c
, 0);
1080 static struct i2c_bus_recovery_info octeon_i2c_recovery_info
= {
1081 .recover_bus
= i2c_generic_scl_recovery
,
1082 .get_scl
= octeon_i2c_get_scl
,
1083 .set_scl
= octeon_i2c_set_scl
,
1084 .get_sda
= octeon_i2c_get_sda
,
1085 .prepare_recovery
= octeon_i2c_prepare_recovery
,
1086 .unprepare_recovery
= octeon_i2c_unprepare_recovery
,
1089 static u32
octeon_i2c_functionality(struct i2c_adapter
*adap
)
1091 return I2C_FUNC_I2C
| (I2C_FUNC_SMBUS_EMUL
& ~I2C_FUNC_SMBUS_QUICK
) |
1092 I2C_FUNC_SMBUS_READ_BLOCK_DATA
| I2C_SMBUS_BLOCK_PROC_CALL
;
1095 static const struct i2c_algorithm octeon_i2c_algo
= {
1096 .master_xfer
= octeon_i2c_xfer
,
1097 .functionality
= octeon_i2c_functionality
,
1100 static struct i2c_adapter octeon_i2c_ops
= {
1101 .owner
= THIS_MODULE
,
1102 .name
= "OCTEON adapter",
1103 .algo
= &octeon_i2c_algo
,
1106 static int octeon_i2c_probe(struct platform_device
*pdev
)
1108 struct device_node
*node
= pdev
->dev
.of_node
;
1109 int irq
, result
= 0, hlc_irq
= 0;
1110 struct resource
*res_mem
;
1111 struct octeon_i2c
*i2c
;
1114 cn78xx_style
= of_device_is_compatible(node
, "cavium,octeon-7890-twsi");
1116 hlc_irq
= platform_get_irq(pdev
, 0);
1120 irq
= platform_get_irq(pdev
, 2);
1124 /* All adaptors have an irq. */
1125 irq
= platform_get_irq(pdev
, 0);
1130 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(*i2c
), GFP_KERNEL
);
1135 i2c
->dev
= &pdev
->dev
;
1137 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1138 i2c
->twsi_base
= devm_ioremap_resource(&pdev
->dev
, res_mem
);
1139 if (IS_ERR(i2c
->twsi_base
)) {
1140 result
= PTR_ERR(i2c
->twsi_base
);
1145 * "clock-rate" is a legacy binding, the official binding is
1146 * "clock-frequency". Try the official one first and then
1147 * fall back if it doesn't exist.
1149 if (of_property_read_u32(node
, "clock-frequency", &i2c
->twsi_freq
) &&
1150 of_property_read_u32(node
, "clock-rate", &i2c
->twsi_freq
)) {
1152 "no I2C 'clock-rate' or 'clock-frequency' property\n");
1157 i2c
->sys_freq
= octeon_get_io_clock_rate();
1159 init_waitqueue_head(&i2c
->queue
);
1164 i2c
->hlc_irq
= hlc_irq
;
1166 i2c
->int_enable
= octeon_i2c_int_enable78
;
1167 i2c
->int_disable
= octeon_i2c_int_disable78
;
1168 i2c
->hlc_int_enable
= octeon_i2c_hlc_int_enable78
;
1169 i2c
->hlc_int_disable
= octeon_i2c_hlc_int_disable78
;
1171 irq_set_status_flags(i2c
->irq
, IRQ_NOAUTOEN
);
1172 irq_set_status_flags(i2c
->hlc_irq
, IRQ_NOAUTOEN
);
1174 result
= devm_request_irq(&pdev
->dev
, i2c
->hlc_irq
,
1175 octeon_i2c_hlc_isr78
, 0,
1178 dev_err(i2c
->dev
, "failed to attach interrupt\n");
1182 i2c
->int_enable
= octeon_i2c_int_enable
;
1183 i2c
->int_disable
= octeon_i2c_int_disable
;
1184 i2c
->hlc_int_enable
= octeon_i2c_hlc_int_enable
;
1185 i2c
->hlc_int_disable
= octeon_i2c_int_disable
;
1188 result
= devm_request_irq(&pdev
->dev
, i2c
->irq
,
1189 octeon_i2c_isr
, 0, DRV_NAME
, i2c
);
1191 dev_err(i2c
->dev
, "failed to attach interrupt\n");
1195 if (OCTEON_IS_MODEL(OCTEON_CN38XX
))
1196 i2c
->broken_irq_check
= true;
1198 result
= octeon_i2c_init_lowlevel(i2c
);
1200 dev_err(i2c
->dev
, "init low level failed\n");
1204 octeon_i2c_set_clock(i2c
);
1206 i2c
->adap
= octeon_i2c_ops
;
1207 i2c
->adap
.timeout
= msecs_to_jiffies(2);
1208 i2c
->adap
.retries
= 5;
1209 i2c
->adap
.bus_recovery_info
= &octeon_i2c_recovery_info
;
1210 i2c
->adap
.dev
.parent
= &pdev
->dev
;
1211 i2c
->adap
.dev
.of_node
= node
;
1212 i2c_set_adapdata(&i2c
->adap
, i2c
);
1213 platform_set_drvdata(pdev
, i2c
);
1215 result
= i2c_add_adapter(&i2c
->adap
);
1217 dev_err(i2c
->dev
, "failed to add adapter\n");
1220 dev_info(i2c
->dev
, "probed\n");
1227 static int octeon_i2c_remove(struct platform_device
*pdev
)
1229 struct octeon_i2c
*i2c
= platform_get_drvdata(pdev
);
1231 i2c_del_adapter(&i2c
->adap
);
1235 static const struct of_device_id octeon_i2c_match
[] = {
1236 { .compatible
= "cavium,octeon-3860-twsi", },
1237 { .compatible
= "cavium,octeon-7890-twsi", },
1240 MODULE_DEVICE_TABLE(of
, octeon_i2c_match
);
1242 static struct platform_driver octeon_i2c_driver
= {
1243 .probe
= octeon_i2c_probe
,
1244 .remove
= octeon_i2c_remove
,
1247 .of_match_table
= octeon_i2c_match
,
1251 module_platform_driver(octeon_i2c_driver
);
1253 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
1254 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
1255 MODULE_LICENSE("GPL");