drivers/i2c/busses/i2c-octeon.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
   4  *
   5  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
   6  *
   7  * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/i2c.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24
  25 #include <asm/octeon/octeon.h>
  26
  27 #define DRV_NAME "i2c-octeon"
  28
  29 /* Register offsets */
  30 #define SW_TWSI                 0x00
  31 #define TWSI_INT                0x10
  32
  33 /* Controller command patterns */
  34 #define SW_TWSI_V               BIT_ULL(63)     /* Valid bit */
  35 #define SW_TWSI_R               BIT_ULL(56)     /* Result or read bit */
  36
  37 /* Controller opcode word (bits 60:57) */
  38 #define SW_TWSI_OP_SHIFT        57
  39 #define SW_TWSI_OP_TWSI_CLK     (4ULL << SW_TWSI_OP_SHIFT)
  40 #define SW_TWSI_OP_EOP          (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
  41
  42 /* Controller extended opcode word (bits 34:32) */
  43 #define SW_TWSI_EOP_SHIFT       32
  44 #define SW_TWSI_EOP_TWSI_DATA   (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
  45 #define SW_TWSI_EOP_TWSI_CTL    (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
  46 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
  47 #define SW_TWSI_EOP_TWSI_STAT   (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
  48 #define SW_TWSI_EOP_TWSI_RST    (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
  49
  50 /* Controller command and status bits */
  51 #define TWSI_CTL_CE             0x80
  52 #define TWSI_CTL_ENAB           0x40    /* Bus enable */
  53 #define TWSI_CTL_STA            0x20    /* Master-mode start, HW clears when done */
  54 #define TWSI_CTL_STP            0x10    /* Master-mode stop, HW clears when done */
  55 #define TWSI_CTL_IFLG           0x08    /* HW event, SW writes 0 to ACK */
  56 #define TWSI_CTL_AAK            0x04    /* Assert ACK */
  57
  58 /* Some status values */
  59 #define STAT_START              0x08
  60 #define STAT_RSTART             0x10
  61 #define STAT_TXADDR_ACK         0x18
  62 #define STAT_TXDATA_ACK         0x28
  63 #define STAT_RXADDR_ACK         0x40
  64 #define STAT_RXDATA_ACK         0x50
  65 #define STAT_IDLE               0xF8
  66
  67 /* TWSI_INT values */
  68 #define TWSI_INT_CORE_EN        BIT_ULL(6)
  69 #define TWSI_INT_SDA_OVR        BIT_ULL(8)
  70 #define TWSI_INT_SCL_OVR        BIT_ULL(9)
  71
  72 struct octeon_i2c {
  73         wait_queue_head_t queue;
  74         struct i2c_adapter adap;
  75         int irq;
  76         u32 twsi_freq;
  77         int sys_freq;
  78         resource_size_t twsi_phys;
  79         void __iomem *twsi_base;
  80         resource_size_t regsize;
  81         struct device *dev;
  82 };
  83
  84 /**
  85  * octeon_i2c_write_sw - write an I2C core register
  86  * @i2c: The struct octeon_i2c
  87  * @eop_reg: Register selector
  88  * @data: Value to be written
  89  *
  90  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
  91  */
  92 static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
  93 {
  94         u64 tmp;
  95
  96         __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
  97         do {
  98                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
  99         } while ((tmp & SW_TWSI_V) != 0);
 100 }
 101
 102 /**
 103  * octeon_i2c_read_sw - read lower bits of an I2C core register
 104  * @i2c: The struct octeon_i2c
 105  * @eop_reg: Register selector
 106  *
 107  * Returns the data.
 108  *
 109  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 110  */
 111 static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
 112 {
 113         u64 tmp;
 114
 115         __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
 116         do {
 117                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
 118         } while ((tmp & SW_TWSI_V) != 0);
 119
 120         return tmp & 0xFF;
 121 }
 122
 123 /**
 124  * octeon_i2c_write_int - write the TWSI_INT register
 125  * @i2c: The struct octeon_i2c
 126  * @data: Value to be written
 127  */
 128 static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
 129 {
 130         __raw_writeq(data, i2c->twsi_base + TWSI_INT);
 131         __raw_readq(i2c->twsi_base + TWSI_INT);
 132 }
 133
 134 /**
 135  * octeon_i2c_int_enable - enable the CORE interrupt
 136  * @i2c: The struct octeon_i2c
 137  *
 138  * The interrupt will be asserted when there is non-STAT_IDLE state in
 139  * the SW_TWSI_EOP_TWSI_STAT register.
 140  */
 141 static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
 142 {
 143         octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
 144 }
 145
 146 /* disable the CORE interrupt */
 147 static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
 148 {
 149         /* clear TS/ST/IFLG events */
 150         octeon_i2c_write_int(i2c, 0);
 151 }
 152
 153 /**
 154  * octeon_i2c_unblock - unblock the bus
 155  * @i2c: The struct octeon_i2c
 156  *
 157  * If there was a reset while a device was driving 0 to bus, bus is blocked.
 158  * We toggle it free manually by some clock cycles and send a stop.
 159  */
 160 static void octeon_i2c_unblock(struct octeon_i2c *i2c)
 161 {
 162         int i;
 163
 164         dev_dbg(i2c->dev, "%s\n", __func__);
 165
 166         for (i = 0; i < 9; i++) {
 167                 octeon_i2c_write_int(i2c, 0);
 168                 udelay(5);
 169                 octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
 170                 udelay(5);
 171         }
 172         /* hand-crank a STOP */
 173         octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
 174         udelay(5);
 175         octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
 176         udelay(5);
 177         octeon_i2c_write_int(i2c, 0);
 178 }
 179
 180 /* interrupt service routine */
 181 static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
 182 {
 183         struct octeon_i2c *i2c = dev_id;
 184
 185         octeon_i2c_int_disable(i2c);
 186         wake_up(&i2c->queue);
 187
 188         return IRQ_HANDLED;
 189 }
 190
 191
 192 static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
 193 {
 194         return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
 195 }
 196
 197 /**
 198  * octeon_i2c_wait - wait for the IFLG to be set
 199  * @i2c: The struct octeon_i2c
 200  *
 201  * Returns 0 on success, otherwise a negative errno.
 202  */
 203 static int octeon_i2c_wait(struct octeon_i2c *i2c)
 204 {
 205         long time_left;
 206
 207         octeon_i2c_int_enable(i2c);
 208         time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
 209                                        i2c->adap.timeout);
 210         octeon_i2c_int_disable(i2c);
 211         if (!time_left) {
 212                 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
 213                 return -ETIMEDOUT;
 214         }
 215
 216         return 0;
 217 }
 218
 219 /**
 220  * octeon_i2c_start - send START to the bus
 221  * @i2c: The struct octeon_i2c
 222  *
 223  * Returns 0 on success, otherwise a negative errno.
 224  */
 225 static int octeon_i2c_start(struct octeon_i2c *i2c)
 226 {
 227         int result;
 228         u8 data;
 229
 230         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 231                             TWSI_CTL_ENAB | TWSI_CTL_STA);
 232
 233         result = octeon_i2c_wait(i2c);
 234         if (result) {
 235                 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
 236                         /*
 237                          * Controller refused to send start flag May
 238                          * be a client is holding SDA low - let's try
 239                          * to free it.
 240                          */
 241                         octeon_i2c_unblock(i2c);
 242                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 243                                             TWSI_CTL_ENAB | TWSI_CTL_STA);
 244                         result = octeon_i2c_wait(i2c);
 245                 }
 246                 if (result)
 247                         return result;
 248         }
 249
 250         data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 251         if ((data != STAT_START) && (data != STAT_RSTART)) {
 252                 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
 253                 return -EIO;
 254         }
 255
 256         return 0;
 257 }
 258
 259 /* send STOP to the bus */
 260 static void octeon_i2c_stop(struct octeon_i2c *i2c)
 261 {
 262         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 263                             TWSI_CTL_ENAB | TWSI_CTL_STP);
 264 }
 265
 266 /**
 267  * octeon_i2c_write - send data to the bus via low-level controller
 268  * @i2c: The struct octeon_i2c
 269  * @target: Target address
 270  * @data: Pointer to the data to be sent
 271  * @length: Length of the data
 272  *
 273  * The address is sent over the bus, then the data.
 274  *
 275  * Returns 0 on success, otherwise a negative errno.
 276  */
 277 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
 278                             const u8 *data, int length)
 279 {
 280         int i, result;
 281         u8 tmp;
 282
 283         result = octeon_i2c_start(i2c);
 284         if (result)
 285                 return result;
 286
 287         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
 288         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 289
 290         result = octeon_i2c_wait(i2c);
 291         if (result)
 292                 return result;
 293
 294         for (i = 0; i < length; i++) {
 295                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 296
 297                 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
 298                         dev_err(i2c->dev,
 299                                 "%s: bad status before write (0x%x)\n",
 300                                 __func__, tmp);
 301                         return -EIO;
 302                 }
 303
 304                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
 305                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 306
 307                 result = octeon_i2c_wait(i2c);
 308                 if (result)
 309                         return result;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /**
 316  * octeon_i2c_read - receive data from the bus via low-level controller
 317  * @i2c: The struct octeon_i2c
 318  * @target: Target address
 319  * @data: Pointer to the location to store the data
 320  * @length: Length of the data
 321  *
 322  * The address is sent over the bus, then the data is read.
 323  *
 324  * Returns 0 on success, otherwise a negative errno.
 325  */
 326 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
 327                            u8 *data, int length)
 328 {
 329         int i, result;
 330         u8 tmp;
 331
 332         if (length < 1)
 333                 return -EINVAL;
 334
 335         result = octeon_i2c_start(i2c);
 336         if (result)
 337                 return result;
 338
 339         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
 340         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 341
 342         result = octeon_i2c_wait(i2c);
 343         if (result)
 344                 return result;
 345
 346         for (i = 0; i < length; i++) {
 347                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 348
 349                 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
 350                         dev_err(i2c->dev,
 351                                 "%s: bad status before read (0x%x)\n",
 352                                 __func__, tmp);
 353                         return -EIO;
 354                 }
 355
 356                 if (i + 1 < length)
 357                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 358                                             TWSI_CTL_ENAB | TWSI_CTL_AAK);
 359                 else
 360                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 361                                             TWSI_CTL_ENAB);
 362
 363                 result = octeon_i2c_wait(i2c);
 364                 if (result)
 365                         return result;
 366
 367                 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
 368         }
 369         return 0;
 370 }
 371
 372 /**
 373  * octeon_i2c_xfer - The driver's master_xfer function
 374  * @adap: Pointer to the i2c_adapter structure
 375  * @msgs: Pointer to the messages to be processed
 376  * @num: Length of the MSGS array
 377  *
 378  * Returns the number of messages processed, or a negative errno on failure.
 379  */
 380 static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 381                            int num)
 382 {
 383         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 384         int i, ret = 0;
 385
 386         for (i = 0; ret == 0 && i < num; i++) {
 387                 struct i2c_msg *pmsg = &msgs[i];
 388
 389                 dev_dbg(i2c->dev,
 390                         "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
 391                          pmsg->flags & I2C_M_RD ? "read" : "write",
 392                          pmsg->len, pmsg->addr, i + 1, num);
 393                 if (pmsg->flags & I2C_M_RD)
 394                         ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
 395                                               pmsg->len);
 396                 else
 397                         ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
 398                                                pmsg->len);
 399         }
 400         octeon_i2c_stop(i2c);
 401
 402         return (ret != 0) ? ret : num;
 403 }
 404
 405 static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
 406 {
 407         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 408 }
 409
 410 static const struct i2c_algorithm octeon_i2c_algo = {
 411         .master_xfer = octeon_i2c_xfer,
 412         .functionality = octeon_i2c_functionality,
 413 };
 414
 415 static struct i2c_adapter octeon_i2c_ops = {
 416         .owner = THIS_MODULE,
 417         .name = "OCTEON adapter",
 418         .algo = &octeon_i2c_algo,
 419         .timeout = HZ / 50,
 420 };
 421
 422 /* calculate and set clock divisors */
 423 static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
 424 {
 425         int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
 426         int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
 427
 428         for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
 429                 /*
 430                  * An mdiv value of less than 2 seems to not work well
 431                  * with ds1337 RTCs, so we constrain it to larger values.
 432                  */
 433                 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
 434                         /*
 435                          * For given ndiv and mdiv values check the
 436                          * two closest thp values.
 437                          */
 438                         tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
 439                         tclk *= (1 << ndiv_idx);
 440                         thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
 441
 442                         for (inc = 0; inc <= 1; inc++) {
 443                                 thp_idx = thp_base + inc;
 444                                 if (thp_idx < 5 || thp_idx > 0xff)
 445                                         continue;
 446
 447                                 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
 448                                 foscl = foscl / (1 << ndiv_idx);
 449                                 foscl = foscl / (mdiv_idx + 1) / 10;
 450                                 diff = abs(foscl - i2c->twsi_freq);
 451                                 if (diff < delta_hz) {
 452                                         delta_hz = diff;
 453                                         thp = thp_idx;
 454                                         mdiv = mdiv_idx;
 455                                         ndiv = ndiv_idx;
 456                                 }
 457                         }
 458                 }
 459         }
 460         octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
 461         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
 462 }
 463
 464 static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
 465 {
 466         u8 status;
 467         int tries;
 468
 469         /* disable high level controller, enable bus access */
 470         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 471
 472         /* reset controller */
 473         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
 474
 475         for (tries = 10; tries; tries--) {
 476                 udelay(1);
 477                 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 478                 if (status == STAT_IDLE)
 479                         return 0;
 480         }
 481         dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
 482         return -EIO;
 483 }
 484
 485 static int octeon_i2c_probe(struct platform_device *pdev)
 486 {
 487         struct device_node *node = pdev->dev.of_node;
 488         struct resource *res_mem;
 489         struct octeon_i2c *i2c;
 490         int irq, result = 0;
 491
 492         /* All adaptors have an irq.  */
 493         irq = platform_get_irq(pdev, 0);
 494         if (irq < 0)
 495                 return irq;
 496
 497         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 498         if (!i2c) {
 499                 result = -ENOMEM;
 500                 goto out;
 501         }
 502         i2c->dev = &pdev->dev;
 503
 504         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 505
 506         if (res_mem == NULL) {
 507                 dev_err(i2c->dev, "found no memory resource\n");
 508                 result = -ENXIO;
 509                 goto out;
 510         }
 511         i2c->twsi_phys = res_mem->start;
 512         i2c->regsize = resource_size(res_mem);
 513
 514         /*
 515          * "clock-rate" is a legacy binding, the official binding is
 516          * "clock-frequency".  Try the official one first and then
 517          * fall back if it doesn't exist.
 518          */
 519         if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
 520             of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
 521                 dev_err(i2c->dev,
 522                         "no I2C 'clock-rate' or 'clock-frequency' property\n");
 523                 result = -ENXIO;
 524                 goto out;
 525         }
 526
 527         i2c->sys_freq = octeon_get_io_clock_rate();
 528
 529         if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
 530                                      res_mem->name)) {
 531                 dev_err(i2c->dev, "request_mem_region failed\n");
 532                 goto out;
 533         }
 534         i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);
 535
 536         init_waitqueue_head(&i2c->queue);
 537
 538         i2c->irq = irq;
 539
 540         result = devm_request_irq(&pdev->dev, i2c->irq,
 541                                   octeon_i2c_isr, 0, DRV_NAME, i2c);
 542         if (result < 0) {
 543                 dev_err(i2c->dev, "failed to attach interrupt\n");
 544                 goto out;
 545         }
 546
 547         result = octeon_i2c_init_lowlevel(i2c);
 548         if (result) {
 549                 dev_err(i2c->dev, "init low level failed\n");
 550                 goto  out;
 551         }
 552
 553         octeon_i2c_set_clock(i2c);
 554
 555         i2c->adap = octeon_i2c_ops;
 556         i2c->adap.dev.parent = &pdev->dev;
 557         i2c->adap.dev.of_node = node;
 558         i2c_set_adapdata(&i2c->adap, i2c);
 559         platform_set_drvdata(pdev, i2c);
 560
 561         result = i2c_add_adapter(&i2c->adap);
 562         if (result < 0) {
 563                 dev_err(i2c->dev, "failed to add adapter\n");
 564                 goto out;
 565         }
 566         dev_info(i2c->dev, "probed\n");
 567         return 0;
 568
 569 out:
 570         return result;
 571 };
 572
 573 static int octeon_i2c_remove(struct platform_device *pdev)
 574 {
 575         struct octeon_i2c *i2c = platform_get_drvdata(pdev);
 576
 577         i2c_del_adapter(&i2c->adap);
 578         return 0;
 579 };
 580
 581 static const struct of_device_id octeon_i2c_match[] = {
 582         { .compatible = "cavium,octeon-3860-twsi", },
 583         {},
 584 };
 585 MODULE_DEVICE_TABLE(of, octeon_i2c_match);
 586
 587 static struct platform_driver octeon_i2c_driver = {
 588         .probe          = octeon_i2c_probe,
 589         .remove         = octeon_i2c_remove,
 590         .driver         = {
 591                 .name   = DRV_NAME,
 592                 .of_match_table = octeon_i2c_match,
 593         },
 594 };
 595
 596 module_platform_driver(octeon_i2c_driver);
 597
 598 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
 599 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
 600 MODULE_LICENSE("GPL");