2 * Driver for I2C adapter in Rockchip RK3xxx SoC
4 * Max Schwarz <max.schwarz@online.de>
5 * based on the patches by Rockchip Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/platform_device.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/spinlock.h>
23 #include <linux/clk.h>
24 #include <linux/wait.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/regmap.h>
27 #include <linux/math64.h>
31 #define REG_CON 0x00 /* control register */
32 #define REG_CLKDIV 0x04 /* clock divisor register */
33 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
34 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
35 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
36 #define REG_MRXCNT 0x14 /* number of bytes to be received */
37 #define REG_IEN 0x18 /* interrupt enable */
38 #define REG_IPD 0x1c /* interrupt pending */
39 #define REG_FCNT 0x20 /* finished count */
41 /* Data buffer offsets */
42 #define TXBUFFER_BASE 0x100
43 #define RXBUFFER_BASE 0x200
46 #define REG_CON_EN BIT(0)
48 REG_CON_MOD_TX
= 0, /* transmit data */
49 REG_CON_MOD_REGISTER_TX
, /* select register and restart */
50 REG_CON_MOD_RX
, /* receive data */
51 REG_CON_MOD_REGISTER_RX
, /* broken: transmits read addr AND writes
54 #define REG_CON_MOD(mod) ((mod) << 1)
55 #define REG_CON_MOD_MASK (BIT(1) | BIT(2))
56 #define REG_CON_START BIT(3)
57 #define REG_CON_STOP BIT(4)
58 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
59 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
61 #define REG_CON_TUNING_MASK GENMASK(15, 8)
63 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
64 #define REG_CON_STA_CFG(cfg) ((cfg) << 12)
65 #define REG_CON_STO_CFG(cfg) ((cfg) << 14)
67 /* REG_MRXADDR bits */
68 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
70 /* REG_IEN/REG_IPD bits */
71 #define REG_INT_BTF BIT(0) /* a byte was transmitted */
72 #define REG_INT_BRF BIT(1) /* a byte was received */
73 #define REG_INT_MBTF BIT(2) /* master data transmit finished */
74 #define REG_INT_MBRF BIT(3) /* master data receive finished */
75 #define REG_INT_START BIT(4) /* START condition generated */
76 #define REG_INT_STOP BIT(5) /* STOP condition generated */
77 #define REG_INT_NAKRCV BIT(6) /* NACK received */
78 #define REG_INT_ALL 0x7f
81 #define WAIT_TIMEOUT 1000 /* ms */
82 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
85 * struct i2c_spec_values:
86 * @min_hold_start_ns: min hold time (repeated) START condition
87 * @min_low_ns: min LOW period of the SCL clock
88 * @min_high_ns: min HIGH period of the SCL cloc
89 * @min_setup_start_ns: min set-up time for a repeated START conditio
90 * @max_data_hold_ns: max data hold time
91 * @min_data_setup_ns: min data set-up time
92 * @min_setup_stop_ns: min set-up time for STOP condition
93 * @min_hold_buffer_ns: min bus free time between a STOP and
96 struct i2c_spec_values
{
97 unsigned long min_hold_start_ns
;
98 unsigned long min_low_ns
;
99 unsigned long min_high_ns
;
100 unsigned long min_setup_start_ns
;
101 unsigned long max_data_hold_ns
;
102 unsigned long min_data_setup_ns
;
103 unsigned long min_setup_stop_ns
;
104 unsigned long min_hold_buffer_ns
;
107 static const struct i2c_spec_values standard_mode_spec
= {
108 .min_hold_start_ns
= 4000,
111 .min_setup_start_ns
= 4700,
112 .max_data_hold_ns
= 3450,
113 .min_data_setup_ns
= 250,
114 .min_setup_stop_ns
= 4000,
115 .min_hold_buffer_ns
= 4700,
118 static const struct i2c_spec_values fast_mode_spec
= {
119 .min_hold_start_ns
= 600,
122 .min_setup_start_ns
= 600,
123 .max_data_hold_ns
= 900,
124 .min_data_setup_ns
= 100,
125 .min_setup_stop_ns
= 600,
126 .min_hold_buffer_ns
= 1300,
129 static const struct i2c_spec_values fast_mode_plus_spec
= {
130 .min_hold_start_ns
= 260,
133 .min_setup_start_ns
= 260,
134 .max_data_hold_ns
= 400,
135 .min_data_setup_ns
= 50,
136 .min_setup_stop_ns
= 260,
137 .min_hold_buffer_ns
= 500,
141 * struct rk3x_i2c_calced_timings:
142 * @div_low: Divider output for low
143 * @div_high: Divider output for high
144 * @tuning: Used to adjust setup/hold data time,
145 * setup/hold start time and setup stop time for
146 * v1's calc_timings, the tuning should all be 0
147 * for old hardware anyone using v0's calc_timings.
149 struct rk3x_i2c_calced_timings
{
150 unsigned long div_low
;
151 unsigned long div_high
;
155 enum rk3x_i2c_state
{
164 * @grf_offset: offset inside the grf regmap for setting the i2c type
165 * @calc_timings: Callback function for i2c timing information calculated
167 struct rk3x_i2c_soc_data
{
169 int (*calc_timings
)(unsigned long, struct i2c_timings
*,
170 struct rk3x_i2c_calced_timings
*);
174 * struct rk3x_i2c - private data of the controller
175 * @adap: corresponding I2C adapter
176 * @dev: device for this controller
177 * @soc_data: related soc data struct
178 * @regs: virtual memory area
179 * @clk: function clk for rk3399 or function & Bus clks for others
180 * @pclk: Bus clk for rk3399
181 * @clk_rate_nb: i2c clk rate change notify
182 * @t: I2C known timing information
183 * @lock: spinlock for the i2c bus
184 * @wait: the waitqueue to wait for i2c transfer
185 * @busy: the condition for the event to wait for
186 * @msg: current i2c message
187 * @addr: addr of i2c slave device
188 * @mode: mode of i2c transfer
189 * @is_last_msg: flag determines whether it is the last msg in this transfer
190 * @state: state of i2c transfer
191 * @processed: byte length which has been send or received
192 * @error: error code for i2c transfer
195 struct i2c_adapter adap
;
197 struct rk3x_i2c_soc_data
*soc_data
;
199 /* Hardware resources */
203 struct notifier_block clk_rate_nb
;
206 struct i2c_timings t
;
208 /* Synchronization & notification */
210 wait_queue_head_t wait
;
213 /* Current message */
219 /* I2C state machine */
220 enum rk3x_i2c_state state
;
221 unsigned int processed
;
225 static inline void i2c_writel(struct rk3x_i2c
*i2c
, u32 value
,
228 writel(value
, i2c
->regs
+ offset
);
231 static inline u32
i2c_readl(struct rk3x_i2c
*i2c
, unsigned int offset
)
233 return readl(i2c
->regs
+ offset
);
236 /* Reset all interrupt pending bits */
237 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c
*i2c
)
239 i2c_writel(i2c
, REG_INT_ALL
, REG_IPD
);
243 * Generate a START condition, which triggers a REG_INT_START interrupt.
245 static void rk3x_i2c_start(struct rk3x_i2c
*i2c
)
247 u32 val
= i2c_readl(i2c
, REG_CON
) & REG_CON_TUNING_MASK
;
249 i2c_writel(i2c
, REG_INT_START
, REG_IEN
);
251 /* enable adapter with correct mode, send START condition */
252 val
|= REG_CON_EN
| REG_CON_MOD(i2c
->mode
) | REG_CON_START
;
254 /* if we want to react to NACK, set ACTACK bit */
255 if (!(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
))
256 val
|= REG_CON_ACTACK
;
258 i2c_writel(i2c
, val
, REG_CON
);
262 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
264 * @error: Error code to return in rk3x_i2c_xfer
266 static void rk3x_i2c_stop(struct rk3x_i2c
*i2c
, int error
)
274 if (i2c
->is_last_msg
) {
275 /* Enable stop interrupt */
276 i2c_writel(i2c
, REG_INT_STOP
, REG_IEN
);
278 i2c
->state
= STATE_STOP
;
280 ctrl
= i2c_readl(i2c
, REG_CON
);
281 ctrl
|= REG_CON_STOP
;
282 i2c_writel(i2c
, ctrl
, REG_CON
);
284 /* Signal rk3x_i2c_xfer to start the next message. */
286 i2c
->state
= STATE_IDLE
;
289 * The HW is actually not capable of REPEATED START. But we can
290 * get the intended effect by resetting its internal state
291 * and issuing an ordinary START.
293 ctrl
= i2c_readl(i2c
, REG_CON
) & REG_CON_TUNING_MASK
;
294 i2c_writel(i2c
, ctrl
, REG_CON
);
296 /* signal that we are finished with the current msg */
302 * Setup a read according to i2c->msg
304 static void rk3x_i2c_prepare_read(struct rk3x_i2c
*i2c
)
306 unsigned int len
= i2c
->msg
->len
- i2c
->processed
;
309 con
= i2c_readl(i2c
, REG_CON
);
312 * The hw can read up to 32 bytes at a time. If we need more than one
313 * chunk, send an ACK after the last byte of the current chunk.
317 con
&= ~REG_CON_LASTACK
;
319 con
|= REG_CON_LASTACK
;
322 /* make sure we are in plain RX mode if we read a second chunk */
323 if (i2c
->processed
!= 0) {
324 con
&= ~REG_CON_MOD_MASK
;
325 con
|= REG_CON_MOD(REG_CON_MOD_RX
);
328 i2c_writel(i2c
, con
, REG_CON
);
329 i2c_writel(i2c
, len
, REG_MRXCNT
);
333 * Fill the transmit buffer with data from i2c->msg
335 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c
*i2c
)
342 for (i
= 0; i
< 8; ++i
) {
344 for (j
= 0; j
< 4; ++j
) {
345 if ((i2c
->processed
== i2c
->msg
->len
) && (cnt
!= 0))
348 if (i2c
->processed
== 0 && cnt
== 0)
349 byte
= (i2c
->addr
& 0x7f) << 1;
351 byte
= i2c
->msg
->buf
[i2c
->processed
++];
353 val
|= byte
<< (j
* 8);
357 i2c_writel(i2c
, val
, TXBUFFER_BASE
+ 4 * i
);
359 if (i2c
->processed
== i2c
->msg
->len
)
363 i2c_writel(i2c
, cnt
, REG_MTXCNT
);
367 /* IRQ handlers for individual states */
369 static void rk3x_i2c_handle_start(struct rk3x_i2c
*i2c
, unsigned int ipd
)
371 if (!(ipd
& REG_INT_START
)) {
372 rk3x_i2c_stop(i2c
, -EIO
);
373 dev_warn(i2c
->dev
, "unexpected irq in START: 0x%x\n", ipd
);
374 rk3x_i2c_clean_ipd(i2c
);
379 i2c_writel(i2c
, REG_INT_START
, REG_IPD
);
381 /* disable start bit */
382 i2c_writel(i2c
, i2c_readl(i2c
, REG_CON
) & ~REG_CON_START
, REG_CON
);
384 /* enable appropriate interrupts and transition */
385 if (i2c
->mode
== REG_CON_MOD_TX
) {
386 i2c_writel(i2c
, REG_INT_MBTF
| REG_INT_NAKRCV
, REG_IEN
);
387 i2c
->state
= STATE_WRITE
;
388 rk3x_i2c_fill_transmit_buf(i2c
);
390 /* in any other case, we are going to be reading. */
391 i2c_writel(i2c
, REG_INT_MBRF
| REG_INT_NAKRCV
, REG_IEN
);
392 i2c
->state
= STATE_READ
;
393 rk3x_i2c_prepare_read(i2c
);
397 static void rk3x_i2c_handle_write(struct rk3x_i2c
*i2c
, unsigned int ipd
)
399 if (!(ipd
& REG_INT_MBTF
)) {
400 rk3x_i2c_stop(i2c
, -EIO
);
401 dev_err(i2c
->dev
, "unexpected irq in WRITE: 0x%x\n", ipd
);
402 rk3x_i2c_clean_ipd(i2c
);
407 i2c_writel(i2c
, REG_INT_MBTF
, REG_IPD
);
409 /* are we finished? */
410 if (i2c
->processed
== i2c
->msg
->len
)
411 rk3x_i2c_stop(i2c
, i2c
->error
);
413 rk3x_i2c_fill_transmit_buf(i2c
);
416 static void rk3x_i2c_handle_read(struct rk3x_i2c
*i2c
, unsigned int ipd
)
419 unsigned int len
= i2c
->msg
->len
- i2c
->processed
;
420 u32
uninitialized_var(val
);
423 /* we only care for MBRF here. */
424 if (!(ipd
& REG_INT_MBRF
))
428 i2c_writel(i2c
, REG_INT_MBRF
, REG_IPD
);
430 /* Can only handle a maximum of 32 bytes at a time */
434 /* read the data from receive buffer */
435 for (i
= 0; i
< len
; ++i
) {
437 val
= i2c_readl(i2c
, RXBUFFER_BASE
+ (i
/ 4) * 4);
439 byte
= (val
>> ((i
% 4) * 8)) & 0xff;
440 i2c
->msg
->buf
[i2c
->processed
++] = byte
;
443 /* are we finished? */
444 if (i2c
->processed
== i2c
->msg
->len
)
445 rk3x_i2c_stop(i2c
, i2c
->error
);
447 rk3x_i2c_prepare_read(i2c
);
450 static void rk3x_i2c_handle_stop(struct rk3x_i2c
*i2c
, unsigned int ipd
)
454 if (!(ipd
& REG_INT_STOP
)) {
455 rk3x_i2c_stop(i2c
, -EIO
);
456 dev_err(i2c
->dev
, "unexpected irq in STOP: 0x%x\n", ipd
);
457 rk3x_i2c_clean_ipd(i2c
);
462 i2c_writel(i2c
, REG_INT_STOP
, REG_IPD
);
464 /* disable STOP bit */
465 con
= i2c_readl(i2c
, REG_CON
);
466 con
&= ~REG_CON_STOP
;
467 i2c_writel(i2c
, con
, REG_CON
);
470 i2c
->state
= STATE_IDLE
;
472 /* signal rk3x_i2c_xfer that we are finished */
476 static irqreturn_t
rk3x_i2c_irq(int irqno
, void *dev_id
)
478 struct rk3x_i2c
*i2c
= dev_id
;
481 spin_lock(&i2c
->lock
);
483 ipd
= i2c_readl(i2c
, REG_IPD
);
484 if (i2c
->state
== STATE_IDLE
) {
485 dev_warn(i2c
->dev
, "irq in STATE_IDLE, ipd = 0x%x\n", ipd
);
486 rk3x_i2c_clean_ipd(i2c
);
490 dev_dbg(i2c
->dev
, "IRQ: state %d, ipd: %x\n", i2c
->state
, ipd
);
492 /* Clean interrupt bits we don't care about */
493 ipd
&= ~(REG_INT_BRF
| REG_INT_BTF
);
495 if (ipd
& REG_INT_NAKRCV
) {
497 * We got a NACK in the last operation. Depending on whether
498 * IGNORE_NAK is set, we have to stop the operation and report
501 i2c_writel(i2c
, REG_INT_NAKRCV
, REG_IPD
);
503 ipd
&= ~REG_INT_NAKRCV
;
505 if (!(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
))
506 rk3x_i2c_stop(i2c
, -ENXIO
);
509 /* is there anything left to handle? */
510 if ((ipd
& REG_INT_ALL
) == 0)
513 switch (i2c
->state
) {
515 rk3x_i2c_handle_start(i2c
, ipd
);
518 rk3x_i2c_handle_write(i2c
, ipd
);
521 rk3x_i2c_handle_read(i2c
, ipd
);
524 rk3x_i2c_handle_stop(i2c
, ipd
);
531 spin_unlock(&i2c
->lock
);
536 * Get timing values of I2C specification
538 * @speed: Desired SCL frequency
540 * Returns: Matched i2c spec values.
542 static const struct i2c_spec_values
*rk3x_i2c_get_spec(unsigned int speed
)
545 return &standard_mode_spec
;
546 else if (speed
<= 400000)
547 return &fast_mode_spec
;
549 return &fast_mode_plus_spec
;
553 * Calculate divider values for desired SCL frequency
555 * @clk_rate: I2C input clock rate
556 * @t: Known I2C timing information
557 * @t_calc: Caculated rk3x private timings that would be written into regs
559 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
560 * a best-effort divider value is returned in divs. If the target rate is
561 * too high, we silently use the highest possible rate.
563 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate
,
564 struct i2c_timings
*t
,
565 struct rk3x_i2c_calced_timings
*t_calc
)
567 unsigned long min_low_ns
, min_high_ns
;
568 unsigned long max_low_ns
, min_total_ns
;
570 unsigned long clk_rate_khz
, scl_rate_khz
;
572 unsigned long min_low_div
, min_high_div
;
573 unsigned long max_low_div
;
575 unsigned long min_div_for_hold
, min_total_div
;
576 unsigned long extra_div
, extra_low_div
, ideal_low_div
;
578 unsigned long data_hold_buffer_ns
= 50;
579 const struct i2c_spec_values
*spec
;
582 /* Only support standard-mode and fast-mode */
583 if (WARN_ON(t
->bus_freq_hz
> 400000))
584 t
->bus_freq_hz
= 400000;
586 /* prevent scl_rate_khz from becoming 0 */
587 if (WARN_ON(t
->bus_freq_hz
< 1000))
588 t
->bus_freq_hz
= 1000;
591 * min_low_ns: The minimum number of ns we need to hold low to
592 * meet I2C specification, should include fall time.
593 * min_high_ns: The minimum number of ns we need to hold high to
594 * meet I2C specification, should include rise time.
595 * max_low_ns: The maximum number of ns we can hold low to meet
598 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
599 * This is because the i2c host on Rockchip holds the data line
600 * for half the low time.
602 spec
= rk3x_i2c_get_spec(t
->bus_freq_hz
);
603 min_high_ns
= t
->scl_rise_ns
+ spec
->min_high_ns
;
606 * Timings for repeated start:
607 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
608 * - controller appears to keep SCL high for 2x programmed clk high.
610 * We need to account for those rules in picking our "high" time so
611 * we meet tSU;STA and tHD;STA times.
613 min_high_ns
= max(min_high_ns
, DIV_ROUND_UP(
614 (t
->scl_rise_ns
+ spec
->min_setup_start_ns
) * 1000, 875));
615 min_high_ns
= max(min_high_ns
, DIV_ROUND_UP(
616 (t
->scl_rise_ns
+ spec
->min_setup_start_ns
+ t
->sda_fall_ns
+
617 spec
->min_high_ns
), 2));
619 min_low_ns
= t
->scl_fall_ns
+ spec
->min_low_ns
;
620 max_low_ns
= spec
->max_data_hold_ns
* 2 - data_hold_buffer_ns
;
621 min_total_ns
= min_low_ns
+ min_high_ns
;
623 /* Adjust to avoid overflow */
624 clk_rate_khz
= DIV_ROUND_UP(clk_rate
, 1000);
625 scl_rate_khz
= t
->bus_freq_hz
/ 1000;
628 * We need the total div to be >= this number
629 * so we don't clock too fast.
631 min_total_div
= DIV_ROUND_UP(clk_rate_khz
, scl_rate_khz
* 8);
633 /* These are the min dividers needed for min hold times. */
634 min_low_div
= DIV_ROUND_UP(clk_rate_khz
* min_low_ns
, 8 * 1000000);
635 min_high_div
= DIV_ROUND_UP(clk_rate_khz
* min_high_ns
, 8 * 1000000);
636 min_div_for_hold
= (min_low_div
+ min_high_div
);
639 * This is the maximum divider so we don't go over the maximum.
640 * We don't round up here (we round down) since this is a maximum.
642 max_low_div
= clk_rate_khz
* max_low_ns
/ (8 * 1000000);
644 if (min_low_div
> max_low_div
) {
646 "Conflicting, min_low_div %lu, max_low_div %lu\n",
647 min_low_div
, max_low_div
);
648 max_low_div
= min_low_div
;
651 if (min_div_for_hold
> min_total_div
) {
653 * Time needed to meet hold requirements is important.
656 t_calc
->div_low
= min_low_div
;
657 t_calc
->div_high
= min_high_div
;
660 * We've got to distribute some time among the low and high
661 * so we don't run too fast.
663 extra_div
= min_total_div
- min_div_for_hold
;
666 * We'll try to split things up perfectly evenly,
667 * biasing slightly towards having a higher div
668 * for low (spend more time low).
670 ideal_low_div
= DIV_ROUND_UP(clk_rate_khz
* min_low_ns
,
671 scl_rate_khz
* 8 * min_total_ns
);
673 /* Don't allow it to go over the maximum */
674 if (ideal_low_div
> max_low_div
)
675 ideal_low_div
= max_low_div
;
678 * Handle when the ideal low div is going to take up
681 if (ideal_low_div
> min_low_div
+ extra_div
)
682 ideal_low_div
= min_low_div
+ extra_div
;
684 /* Give low the "ideal" and give high whatever extra is left */
685 extra_low_div
= ideal_low_div
- min_low_div
;
686 t_calc
->div_low
= ideal_low_div
;
687 t_calc
->div_high
= min_high_div
+ (extra_div
- extra_low_div
);
691 * Adjust to the fact that the hardware has an implicit "+1".
692 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
697 /* Maximum divider supported by hw is 0xffff */
698 if (t_calc
->div_low
> 0xffff) {
699 t_calc
->div_low
= 0xffff;
703 if (t_calc
->div_high
> 0xffff) {
704 t_calc
->div_high
= 0xffff;
712 * Calculate timing values for desired SCL frequency
714 * @clk_rate: I2C input clock rate
715 * @t: Known I2C timing information
716 * @t_calc: Caculated rk3x private timings that would be written into regs
718 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
719 * a best-effort divider value is returned in divs. If the target rate is
720 * too high, we silently use the highest possible rate.
721 * The following formulas are v1's method to calculate timings.
725 * s = sda_update_config + 1;
726 * u = start_setup_config + 1;
727 * p = stop_setup_config + 1;
733 * tHD;sda = (l * s + 1) * T;
734 * tSU;sda = [(8 - s) * l + 1] * T;
735 * tI2C = 8 * (l + h) * T;
737 * tSU;sta = (8h * u + 1) * T;
738 * tHD;sta = [8h * (u + 1) - 1] * T;
739 * tSU;sto = (8h * p + 1) * T;
741 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate
,
742 struct i2c_timings
*t
,
743 struct rk3x_i2c_calced_timings
*t_calc
)
745 unsigned long min_low_ns
, min_high_ns
, min_total_ns
;
746 unsigned long min_setup_start_ns
, min_setup_data_ns
;
747 unsigned long min_setup_stop_ns
, max_hold_data_ns
;
749 unsigned long clk_rate_khz
, scl_rate_khz
;
751 unsigned long min_low_div
, min_high_div
;
753 unsigned long min_div_for_hold
, min_total_div
;
754 unsigned long extra_div
, extra_low_div
;
755 unsigned long sda_update_cfg
, stp_sta_cfg
, stp_sto_cfg
;
757 const struct i2c_spec_values
*spec
;
760 /* Support standard-mode, fast-mode and fast-mode plus */
761 if (WARN_ON(t
->bus_freq_hz
> 1000000))
762 t
->bus_freq_hz
= 1000000;
764 /* prevent scl_rate_khz from becoming 0 */
765 if (WARN_ON(t
->bus_freq_hz
< 1000))
766 t
->bus_freq_hz
= 1000;
769 * min_low_ns: The minimum number of ns we need to hold low to
770 * meet I2C specification, should include fall time.
771 * min_high_ns: The minimum number of ns we need to hold high to
772 * meet I2C specification, should include rise time.
774 spec
= rk3x_i2c_get_spec(t
->bus_freq_hz
);
776 /* calculate min-divh and min-divl */
777 clk_rate_khz
= DIV_ROUND_UP(clk_rate
, 1000);
778 scl_rate_khz
= t
->bus_freq_hz
/ 1000;
779 min_total_div
= DIV_ROUND_UP(clk_rate_khz
, scl_rate_khz
* 8);
781 min_high_ns
= t
->scl_rise_ns
+ spec
->min_high_ns
;
782 min_high_div
= DIV_ROUND_UP(clk_rate_khz
* min_high_ns
, 8 * 1000000);
784 min_low_ns
= t
->scl_fall_ns
+ spec
->min_low_ns
;
785 min_low_div
= DIV_ROUND_UP(clk_rate_khz
* min_low_ns
, 8 * 1000000);
788 * Final divh and divl must be greater than 0, otherwise the
789 * hardware would not output the i2c clk.
791 min_high_div
= (min_high_div
< 1) ? 2 : min_high_div
;
792 min_low_div
= (min_low_div
< 1) ? 2 : min_low_div
;
794 /* These are the min dividers needed for min hold times. */
795 min_div_for_hold
= (min_low_div
+ min_high_div
);
796 min_total_ns
= min_low_ns
+ min_high_ns
;
799 * This is the maximum divider so we don't go over the maximum.
800 * We don't round up here (we round down) since this is a maximum.
802 if (min_div_for_hold
>= min_total_div
) {
804 * Time needed to meet hold requirements is important.
807 t_calc
->div_low
= min_low_div
;
808 t_calc
->div_high
= min_high_div
;
811 * We've got to distribute some time among the low and high
812 * so we don't run too fast.
813 * We'll try to split things up by the scale of min_low_div and
814 * min_high_div, biasing slightly towards having a higher div
815 * for low (spend more time low).
817 extra_div
= min_total_div
- min_div_for_hold
;
818 extra_low_div
= DIV_ROUND_UP(min_low_div
* extra_div
,
821 t_calc
->div_low
= min_low_div
+ extra_low_div
;
822 t_calc
->div_high
= min_high_div
+ (extra_div
- extra_low_div
);
826 * calculate sda data hold count by the rules, data_upd_st:3
827 * is a appropriate value to reduce calculated times.
829 for (sda_update_cfg
= 3; sda_update_cfg
> 0; sda_update_cfg
--) {
830 max_hold_data_ns
= DIV_ROUND_UP((sda_update_cfg
831 * (t_calc
->div_low
) + 1)
832 * 1000000, clk_rate_khz
);
833 min_setup_data_ns
= DIV_ROUND_UP(((8 - sda_update_cfg
)
834 * (t_calc
->div_low
) + 1)
835 * 1000000, clk_rate_khz
);
836 if ((max_hold_data_ns
< spec
->max_data_hold_ns
) &&
837 (min_setup_data_ns
> spec
->min_data_setup_ns
))
841 /* calculate setup start config */
842 min_setup_start_ns
= t
->scl_rise_ns
+ spec
->min_setup_start_ns
;
843 stp_sta_cfg
= DIV_ROUND_UP(clk_rate_khz
* min_setup_start_ns
844 - 1000000, 8 * 1000000 * (t_calc
->div_high
));
846 /* calculate setup stop config */
847 min_setup_stop_ns
= t
->scl_rise_ns
+ spec
->min_setup_stop_ns
;
848 stp_sto_cfg
= DIV_ROUND_UP(clk_rate_khz
* min_setup_stop_ns
849 - 1000000, 8 * 1000000 * (t_calc
->div_high
));
851 t_calc
->tuning
= REG_CON_SDA_CFG(--sda_update_cfg
) |
852 REG_CON_STA_CFG(--stp_sta_cfg
) |
853 REG_CON_STO_CFG(--stp_sto_cfg
);
858 /* Maximum divider supported by hw is 0xffff */
859 if (t_calc
->div_low
> 0xffff) {
860 t_calc
->div_low
= 0xffff;
864 if (t_calc
->div_high
> 0xffff) {
865 t_calc
->div_high
= 0xffff;
872 static void rk3x_i2c_adapt_div(struct rk3x_i2c
*i2c
, unsigned long clk_rate
)
874 struct i2c_timings
*t
= &i2c
->t
;
875 struct rk3x_i2c_calced_timings calc
;
876 u64 t_low_ns
, t_high_ns
;
881 ret
= i2c
->soc_data
->calc_timings(clk_rate
, t
, &calc
);
882 WARN_ONCE(ret
!= 0, "Could not reach SCL freq %u", t
->bus_freq_hz
);
884 clk_enable(i2c
->pclk
);
886 spin_lock_irqsave(&i2c
->lock
, flags
);
887 val
= i2c_readl(i2c
, REG_CON
);
888 val
&= ~REG_CON_TUNING_MASK
;
890 i2c_writel(i2c
, val
, REG_CON
);
891 i2c_writel(i2c
, (calc
.div_high
<< 16) | (calc
.div_low
& 0xffff),
893 spin_unlock_irqrestore(&i2c
->lock
, flags
);
895 clk_disable(i2c
->pclk
);
897 t_low_ns
= div_u64(((u64
)calc
.div_low
+ 1) * 8 * 1000000000, clk_rate
);
898 t_high_ns
= div_u64(((u64
)calc
.div_high
+ 1) * 8 * 1000000000,
901 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
903 1000000000 / t
->bus_freq_hz
,
904 t_low_ns
, t_high_ns
);
908 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
909 * @nb: Pointer to notifier block
910 * @event: Notification reason
911 * @data: Pointer to notification data object
913 * The callback checks whether a valid bus frequency can be generated after the
914 * change. If so, the change is acknowledged, otherwise the change is aborted.
915 * New dividers are written to the HW in the pre- or post change notification
916 * depending on the scaling direction.
918 * Code adapted from i2c-cadence.c.
920 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
921 * to acknowledge the change, NOTIFY_DONE if the notification is
922 * considered irrelevant.
924 static int rk3x_i2c_clk_notifier_cb(struct notifier_block
*nb
, unsigned long
927 struct clk_notifier_data
*ndata
= data
;
928 struct rk3x_i2c
*i2c
= container_of(nb
, struct rk3x_i2c
, clk_rate_nb
);
929 struct rk3x_i2c_calced_timings calc
;
932 case PRE_RATE_CHANGE
:
934 * Try the calculation (but don't store the result) ahead of
935 * time to see if we need to block the clock change. Timings
936 * shouldn't actually take effect until rk3x_i2c_adapt_div().
938 if (i2c
->soc_data
->calc_timings(ndata
->new_rate
, &i2c
->t
,
943 if (ndata
->new_rate
> ndata
->old_rate
)
944 rk3x_i2c_adapt_div(i2c
, ndata
->new_rate
);
947 case POST_RATE_CHANGE
:
949 if (ndata
->new_rate
< ndata
->old_rate
)
950 rk3x_i2c_adapt_div(i2c
, ndata
->new_rate
);
952 case ABORT_RATE_CHANGE
:
954 if (ndata
->new_rate
> ndata
->old_rate
)
955 rk3x_i2c_adapt_div(i2c
, ndata
->old_rate
);
963 * Setup I2C registers for an I2C operation specified by msgs, num.
965 * Must be called with i2c->lock held.
967 * @msgs: I2C msgs to process
968 * @num: Number of msgs
970 * returns: Number of I2C msgs processed or negative in case of error
972 static int rk3x_i2c_setup(struct rk3x_i2c
*i2c
, struct i2c_msg
*msgs
, int num
)
974 u32 addr
= (msgs
[0].addr
& 0x7f) << 1;
978 * The I2C adapter can issue a small (len < 4) write packet before
979 * reading. This speeds up SMBus-style register reads.
980 * The MRXADDR/MRXRADDR hold the slave address and the slave register
981 * address in this case.
984 if (num
>= 2 && msgs
[0].len
< 4 &&
985 !(msgs
[0].flags
& I2C_M_RD
) && (msgs
[1].flags
& I2C_M_RD
)) {
989 dev_dbg(i2c
->dev
, "Combined write/read from addr 0x%x\n",
992 /* Fill MRXRADDR with the register address(es) */
993 for (i
= 0; i
< msgs
[0].len
; ++i
) {
994 reg_addr
|= msgs
[0].buf
[i
] << (i
* 8);
995 reg_addr
|= REG_MRXADDR_VALID(i
);
998 /* msgs[0] is handled by hw. */
1001 i2c
->mode
= REG_CON_MOD_REGISTER_TX
;
1003 i2c_writel(i2c
, addr
| REG_MRXADDR_VALID(0), REG_MRXADDR
);
1004 i2c_writel(i2c
, reg_addr
, REG_MRXRADDR
);
1009 * We'll have to do it the boring way and process the msgs
1013 if (msgs
[0].flags
& I2C_M_RD
) {
1014 addr
|= 1; /* set read bit */
1017 * We have to transmit the slave addr first. Use
1018 * MOD_REGISTER_TX for that purpose.
1020 i2c
->mode
= REG_CON_MOD_REGISTER_TX
;
1021 i2c_writel(i2c
, addr
| REG_MRXADDR_VALID(0),
1023 i2c_writel(i2c
, 0, REG_MRXRADDR
);
1025 i2c
->mode
= REG_CON_MOD_TX
;
1028 i2c
->msg
= &msgs
[0];
1033 i2c
->addr
= msgs
[0].addr
;
1035 i2c
->state
= STATE_START
;
1039 rk3x_i2c_clean_ipd(i2c
);
1044 static int rk3x_i2c_xfer(struct i2c_adapter
*adap
,
1045 struct i2c_msg
*msgs
, int num
)
1047 struct rk3x_i2c
*i2c
= (struct rk3x_i2c
*)adap
->algo_data
;
1048 unsigned long timeout
, flags
;
1053 spin_lock_irqsave(&i2c
->lock
, flags
);
1055 clk_enable(i2c
->clk
);
1056 clk_enable(i2c
->pclk
);
1058 i2c
->is_last_msg
= false;
1061 * Process msgs. We can handle more than one message at once (see
1062 * rk3x_i2c_setup()).
1064 for (i
= 0; i
< num
; i
+= ret
) {
1065 ret
= rk3x_i2c_setup(i2c
, msgs
+ i
, num
- i
);
1068 dev_err(i2c
->dev
, "rk3x_i2c_setup() failed\n");
1073 i2c
->is_last_msg
= true;
1075 spin_unlock_irqrestore(&i2c
->lock
, flags
);
1077 rk3x_i2c_start(i2c
);
1079 timeout
= wait_event_timeout(i2c
->wait
, !i2c
->busy
,
1080 msecs_to_jiffies(WAIT_TIMEOUT
));
1082 spin_lock_irqsave(&i2c
->lock
, flags
);
1085 dev_err(i2c
->dev
, "timeout, ipd: 0x%02x, state: %d\n",
1086 i2c_readl(i2c
, REG_IPD
), i2c
->state
);
1088 /* Force a STOP condition without interrupt */
1089 i2c_writel(i2c
, 0, REG_IEN
);
1090 val
= i2c_readl(i2c
, REG_CON
) & REG_CON_TUNING_MASK
;
1091 val
|= REG_CON_EN
| REG_CON_STOP
;
1092 i2c_writel(i2c
, val
, REG_CON
);
1094 i2c
->state
= STATE_IDLE
;
1106 clk_disable(i2c
->pclk
);
1107 clk_disable(i2c
->clk
);
1109 spin_unlock_irqrestore(&i2c
->lock
, flags
);
1111 return ret
< 0 ? ret
: num
;
1114 static __maybe_unused
int rk3x_i2c_resume(struct device
*dev
)
1116 struct rk3x_i2c
*i2c
= dev_get_drvdata(dev
);
1118 rk3x_i2c_adapt_div(i2c
, clk_get_rate(i2c
->clk
));
1123 static u32
rk3x_i2c_func(struct i2c_adapter
*adap
)
1125 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
| I2C_FUNC_PROTOCOL_MANGLING
;
1128 static const struct i2c_algorithm rk3x_i2c_algorithm
= {
1129 .master_xfer
= rk3x_i2c_xfer
,
1130 .functionality
= rk3x_i2c_func
,
1133 static const struct rk3x_i2c_soc_data rk3066_soc_data
= {
1134 .grf_offset
= 0x154,
1135 .calc_timings
= rk3x_i2c_v0_calc_timings
,
1138 static const struct rk3x_i2c_soc_data rk3188_soc_data
= {
1139 .grf_offset
= 0x0a4,
1140 .calc_timings
= rk3x_i2c_v0_calc_timings
,
1143 static const struct rk3x_i2c_soc_data rk3228_soc_data
= {
1145 .calc_timings
= rk3x_i2c_v0_calc_timings
,
1148 static const struct rk3x_i2c_soc_data rk3288_soc_data
= {
1150 .calc_timings
= rk3x_i2c_v0_calc_timings
,
1153 static const struct rk3x_i2c_soc_data rk3399_soc_data
= {
1155 .calc_timings
= rk3x_i2c_v1_calc_timings
,
1158 static const struct of_device_id rk3x_i2c_match
[] = {
1160 .compatible
= "rockchip,rk3066-i2c",
1161 .data
= (void *)&rk3066_soc_data
1164 .compatible
= "rockchip,rk3188-i2c",
1165 .data
= (void *)&rk3188_soc_data
1168 .compatible
= "rockchip,rk3228-i2c",
1169 .data
= (void *)&rk3228_soc_data
1172 .compatible
= "rockchip,rk3288-i2c",
1173 .data
= (void *)&rk3288_soc_data
1176 .compatible
= "rockchip,rk3399-i2c",
1177 .data
= (void *)&rk3399_soc_data
1181 MODULE_DEVICE_TABLE(of
, rk3x_i2c_match
);
1183 static int rk3x_i2c_probe(struct platform_device
*pdev
)
1185 struct device_node
*np
= pdev
->dev
.of_node
;
1186 const struct of_device_id
*match
;
1187 struct rk3x_i2c
*i2c
;
1188 struct resource
*mem
;
1193 unsigned long clk_rate
;
1195 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(struct rk3x_i2c
), GFP_KERNEL
);
1199 match
= of_match_node(rk3x_i2c_match
, np
);
1200 i2c
->soc_data
= (struct rk3x_i2c_soc_data
*)match
->data
;
1202 /* use common interface to get I2C timing properties */
1203 i2c_parse_fw_timings(&pdev
->dev
, &i2c
->t
, true);
1205 strlcpy(i2c
->adap
.name
, "rk3x-i2c", sizeof(i2c
->adap
.name
));
1206 i2c
->adap
.owner
= THIS_MODULE
;
1207 i2c
->adap
.algo
= &rk3x_i2c_algorithm
;
1208 i2c
->adap
.retries
= 3;
1209 i2c
->adap
.dev
.of_node
= np
;
1210 i2c
->adap
.algo_data
= i2c
;
1211 i2c
->adap
.dev
.parent
= &pdev
->dev
;
1213 i2c
->dev
= &pdev
->dev
;
1215 spin_lock_init(&i2c
->lock
);
1216 init_waitqueue_head(&i2c
->wait
);
1218 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1219 i2c
->regs
= devm_ioremap_resource(&pdev
->dev
, mem
);
1220 if (IS_ERR(i2c
->regs
))
1221 return PTR_ERR(i2c
->regs
);
1223 /* Try to set the I2C adapter number from dt */
1224 bus_nr
= of_alias_get_id(np
, "i2c");
1227 * Switch to new interface if the SoC also offers the old one.
1228 * The control bit is located in the GRF register space.
1230 if (i2c
->soc_data
->grf_offset
>= 0) {
1233 grf
= syscon_regmap_lookup_by_phandle(np
, "rockchip,grf");
1236 "rk3x-i2c needs 'rockchip,grf' property\n");
1237 return PTR_ERR(grf
);
1241 dev_err(&pdev
->dev
, "rk3x-i2c needs i2cX alias");
1245 /* 27+i: write mask, 11+i: value */
1246 value
= BIT(27 + bus_nr
) | BIT(11 + bus_nr
);
1248 ret
= regmap_write(grf
, i2c
->soc_data
->grf_offset
, value
);
1250 dev_err(i2c
->dev
, "Could not write to GRF: %d\n", ret
);
1256 irq
= platform_get_irq(pdev
, 0);
1258 dev_err(&pdev
->dev
, "cannot find rk3x IRQ\n");
1262 ret
= devm_request_irq(&pdev
->dev
, irq
, rk3x_i2c_irq
,
1263 0, dev_name(&pdev
->dev
), i2c
);
1265 dev_err(&pdev
->dev
, "cannot request IRQ\n");
1269 platform_set_drvdata(pdev
, i2c
);
1271 if (i2c
->soc_data
->calc_timings
== rk3x_i2c_v0_calc_timings
) {
1272 /* Only one clock to use for bus clock and peripheral clock */
1273 i2c
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1274 i2c
->pclk
= i2c
->clk
;
1276 i2c
->clk
= devm_clk_get(&pdev
->dev
, "i2c");
1277 i2c
->pclk
= devm_clk_get(&pdev
->dev
, "pclk");
1280 if (IS_ERR(i2c
->clk
)) {
1281 ret
= PTR_ERR(i2c
->clk
);
1282 if (ret
!= -EPROBE_DEFER
)
1283 dev_err(&pdev
->dev
, "Can't get bus clk: %d\n", ret
);
1286 if (IS_ERR(i2c
->pclk
)) {
1287 ret
= PTR_ERR(i2c
->pclk
);
1288 if (ret
!= -EPROBE_DEFER
)
1289 dev_err(&pdev
->dev
, "Can't get periph clk: %d\n", ret
);
1293 ret
= clk_prepare(i2c
->clk
);
1295 dev_err(&pdev
->dev
, "Can't prepare bus clk: %d\n", ret
);
1298 ret
= clk_prepare(i2c
->pclk
);
1300 dev_err(&pdev
->dev
, "Can't prepare periph clock: %d\n", ret
);
1304 i2c
->clk_rate_nb
.notifier_call
= rk3x_i2c_clk_notifier_cb
;
1305 ret
= clk_notifier_register(i2c
->clk
, &i2c
->clk_rate_nb
);
1307 dev_err(&pdev
->dev
, "Unable to register clock notifier\n");
1311 clk_rate
= clk_get_rate(i2c
->clk
);
1312 rk3x_i2c_adapt_div(i2c
, clk_rate
);
1314 ret
= i2c_add_adapter(&i2c
->adap
);
1316 dev_err(&pdev
->dev
, "Could not register adapter\n");
1317 goto err_clk_notifier
;
1320 dev_info(&pdev
->dev
, "Initialized RK3xxx I2C bus at %p\n", i2c
->regs
);
1325 clk_notifier_unregister(i2c
->clk
, &i2c
->clk_rate_nb
);
1327 clk_unprepare(i2c
->pclk
);
1329 clk_unprepare(i2c
->clk
);
1333 static int rk3x_i2c_remove(struct platform_device
*pdev
)
1335 struct rk3x_i2c
*i2c
= platform_get_drvdata(pdev
);
1337 i2c_del_adapter(&i2c
->adap
);
1339 clk_notifier_unregister(i2c
->clk
, &i2c
->clk_rate_nb
);
1340 clk_unprepare(i2c
->pclk
);
1341 clk_unprepare(i2c
->clk
);
1346 static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops
, NULL
, rk3x_i2c_resume
);
1348 static struct platform_driver rk3x_i2c_driver
= {
1349 .probe
= rk3x_i2c_probe
,
1350 .remove
= rk3x_i2c_remove
,
1353 .of_match_table
= rk3x_i2c_match
,
1354 .pm
= &rk3x_i2c_pm_ops
,
1358 module_platform_driver(rk3x_i2c_driver
);
1360 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1361 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1362 MODULE_LICENSE("GPL v2");