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i2c: sh_mobile: add devicetree documentation
[deliverable/linux.git] / drivers / i2c / busses / i2c-sh_mobile.c
1 /*
2 * SuperH Mobile I2C Controller
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * Portions of the code based on out-of-tree driver i2c-sh7343.c
7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/clk.h>
33 #include <linux/io.h>
34 #include <linux/slab.h>
35 #include <linux/i2c/i2c-sh_mobile.h>
36
37 /* Transmit operation: */
38 /* */
39 /* 0 byte transmit */
40 /* BUS: S A8 ACK P(*) */
41 /* IRQ: DTE WAIT */
42 /* ICIC: */
43 /* ICCR: 0x94 0x90 */
44 /* ICDR: A8 */
45 /* */
46 /* 1 byte transmit */
47 /* BUS: S A8 ACK D8(1) ACK P(*) */
48 /* IRQ: DTE WAIT WAIT */
49 /* ICIC: -DTE */
50 /* ICCR: 0x94 0x90 */
51 /* ICDR: A8 D8(1) */
52 /* */
53 /* 2 byte transmit */
54 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
55 /* IRQ: DTE WAIT WAIT WAIT */
56 /* ICIC: -DTE */
57 /* ICCR: 0x94 0x90 */
58 /* ICDR: A8 D8(1) D8(2) */
59 /* */
60 /* 3 bytes or more, +---------+ gets repeated */
61 /* */
62 /* */
63 /* Receive operation: */
64 /* */
65 /* 0 byte receive - not supported since slave may hold SDA low */
66 /* */
67 /* 1 byte receive [TX] | [RX] */
68 /* BUS: S A8 ACK | D8(1) ACK P(*) */
69 /* IRQ: DTE WAIT | WAIT DTE */
70 /* ICIC: -DTE | +DTE */
71 /* ICCR: 0x94 0x81 | 0xc0 */
72 /* ICDR: A8 | D8(1) */
73 /* */
74 /* 2 byte receive [TX]| [RX] */
75 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
76 /* IRQ: DTE WAIT | WAIT WAIT DTE */
77 /* ICIC: -DTE | +DTE */
78 /* ICCR: 0x94 0x81 | 0xc0 */
79 /* ICDR: A8 | D8(1) D8(2) */
80 /* */
81 /* 3 byte receive [TX] | [RX] (*) */
82 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
83 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
84 /* ICIC: -DTE | +DTE */
85 /* ICCR: 0x94 0x81 | 0xc0 */
86 /* ICDR: A8 | D8(1) D8(2) D8(3) */
87 /* */
88 /* 4 bytes or more, this part is repeated +---------+ */
89 /* */
90 /* */
91 /* Interrupt order and BUSY flag */
92 /* ___ _ */
93 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
94 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
95 /* */
96 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
97 /* ___ */
98 /* WAIT IRQ ________________________________/ \___________ */
99 /* TACK IRQ ____________________________________/ \_______ */
100 /* DTE IRQ __________________________________________/ \_ */
101 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
102 /* _______________________________________________ */
103 /* BUSY __/ \_ */
104 /* */
105 /* (*) The STOP condition is only sent by the master at the end of the last */
106 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
107 /* only cleared after the STOP condition, so, between messages we have to */
108 /* poll for the DTE bit. */
109 /* */
110
111 enum sh_mobile_i2c_op {
112 OP_START = 0,
113 OP_TX_FIRST,
114 OP_TX,
115 OP_TX_STOP,
116 OP_TX_TO_RX,
117 OP_RX,
118 OP_RX_STOP,
119 OP_RX_STOP_DATA,
120 };
121
122 struct sh_mobile_i2c_data {
123 struct device *dev;
124 void __iomem *reg;
125 struct i2c_adapter adap;
126 unsigned long bus_speed;
127 unsigned int clks_per_count;
128 struct clk *clk;
129 u_int8_t icic;
130 u_int8_t flags;
131 u_int16_t iccl;
132 u_int16_t icch;
133
134 spinlock_t lock;
135 wait_queue_head_t wait;
136 struct i2c_msg *msg;
137 int pos;
138 int sr;
139 bool send_stop;
140 };
141
142 #define IIC_FLAG_HAS_ICIC67 (1 << 0)
143
144 #define STANDARD_MODE 100000
145 #define FAST_MODE 400000
146
147 /* Register offsets */
148 #define ICDR 0x00
149 #define ICCR 0x04
150 #define ICSR 0x08
151 #define ICIC 0x0c
152 #define ICCL 0x10
153 #define ICCH 0x14
154
155 /* Register bits */
156 #define ICCR_ICE 0x80
157 #define ICCR_RACK 0x40
158 #define ICCR_TRS 0x10
159 #define ICCR_BBSY 0x04
160 #define ICCR_SCP 0x01
161
162 #define ICSR_SCLM 0x80
163 #define ICSR_SDAM 0x40
164 #define SW_DONE 0x20
165 #define ICSR_BUSY 0x10
166 #define ICSR_AL 0x08
167 #define ICSR_TACK 0x04
168 #define ICSR_WAIT 0x02
169 #define ICSR_DTE 0x01
170
171 #define ICIC_ICCLB8 0x80
172 #define ICIC_ICCHB8 0x40
173 #define ICIC_ALE 0x08
174 #define ICIC_TACKE 0x04
175 #define ICIC_WAITE 0x02
176 #define ICIC_DTEE 0x01
177
178 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
179 {
180 if (offs == ICIC)
181 data |= pd->icic;
182
183 iowrite8(data, pd->reg + offs);
184 }
185
186 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
187 {
188 return ioread8(pd->reg + offs);
189 }
190
191 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
192 unsigned char set, unsigned char clr)
193 {
194 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
195 }
196
197 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf, int offset)
198 {
199 /*
200 * Conditional expression:
201 * ICCL >= COUNT_CLK * (tLOW + tf)
202 *
203 * SH-Mobile IIC hardware starts counting the LOW period of
204 * the SCL signal (tLOW) as soon as it pulls the SCL line.
205 * In order to meet the tLOW timing spec, we need to take into
206 * account the fall time of SCL signal (tf). Default tf value
207 * should be 0.3 us, for safety.
208 */
209 return (((count_khz * (tLOW + tf)) + 5000) / 10000) + offset;
210 }
211
212 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf, int offset)
213 {
214 /*
215 * Conditional expression:
216 * ICCH >= COUNT_CLK * (tHIGH + tf)
217 *
218 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
219 * and can ignore it. SH-Mobile IIC controller starts counting
220 * the HIGH period of the SCL signal (tHIGH) after the SCL input
221 * voltage increases at VIH.
222 *
223 * Afterward it turned out calculating ICCH using only tHIGH spec
224 * will result in violation of the tHD;STA timing spec. We need
225 * to take into account the fall time of SDA signal (tf) at START
226 * condition, in order to meet both tHIGH and tHD;STA specs.
227 */
228 return (((count_khz * (tHIGH + tf)) + 5000) / 10000) + offset;
229 }
230
231 static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
232 {
233 unsigned long i2c_clk_khz;
234 u32 tHIGH, tLOW, tf;
235 int offset;
236
237 /* Get clock rate after clock is enabled */
238 clk_prepare_enable(pd->clk);
239 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
240 i2c_clk_khz /= pd->clks_per_count;
241
242 if (pd->bus_speed == STANDARD_MODE) {
243 tLOW = 47; /* tLOW = 4.7 us */
244 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
245 tf = 3; /* tf = 0.3 us */
246 offset = 0; /* No offset */
247 } else if (pd->bus_speed == FAST_MODE) {
248 tLOW = 13; /* tLOW = 1.3 us */
249 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
250 tf = 3; /* tf = 0.3 us */
251 offset = 0; /* No offset */
252 } else {
253 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
254 pd->bus_speed);
255 goto out;
256 }
257
258 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf, offset);
259 /* one more bit of ICCL in ICIC */
260 if ((pd->iccl > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
261 pd->icic |= ICIC_ICCLB8;
262 else
263 pd->icic &= ~ICIC_ICCLB8;
264
265 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf, offset);
266 /* one more bit of ICCH in ICIC */
267 if ((pd->icch > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
268 pd->icic |= ICIC_ICCHB8;
269 else
270 pd->icic &= ~ICIC_ICCHB8;
271
272 out:
273 clk_disable_unprepare(pd->clk);
274 }
275
276 static void activate_ch(struct sh_mobile_i2c_data *pd)
277 {
278 /* Wake up device and enable clock */
279 pm_runtime_get_sync(pd->dev);
280 clk_prepare_enable(pd->clk);
281
282 /* Enable channel and configure rx ack */
283 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
284
285 /* Mask all interrupts */
286 iic_wr(pd, ICIC, 0);
287
288 /* Set the clock */
289 iic_wr(pd, ICCL, pd->iccl & 0xff);
290 iic_wr(pd, ICCH, pd->icch & 0xff);
291 }
292
293 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
294 {
295 /* Clear/disable interrupts */
296 iic_wr(pd, ICSR, 0);
297 iic_wr(pd, ICIC, 0);
298
299 /* Disable channel */
300 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
301
302 /* Disable clock and mark device as idle */
303 clk_disable_unprepare(pd->clk);
304 pm_runtime_put_sync(pd->dev);
305 }
306
307 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
308 enum sh_mobile_i2c_op op, unsigned char data)
309 {
310 unsigned char ret = 0;
311 unsigned long flags;
312
313 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
314
315 spin_lock_irqsave(&pd->lock, flags);
316
317 switch (op) {
318 case OP_START: /* issue start and trigger DTE interrupt */
319 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
320 break;
321 case OP_TX_FIRST: /* disable DTE interrupt and write data */
322 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
323 iic_wr(pd, ICDR, data);
324 break;
325 case OP_TX: /* write data */
326 iic_wr(pd, ICDR, data);
327 break;
328 case OP_TX_STOP: /* write data and issue a stop afterwards */
329 iic_wr(pd, ICDR, data);
330 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
331 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
332 break;
333 case OP_TX_TO_RX: /* select read mode */
334 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
335 break;
336 case OP_RX: /* just read data */
337 ret = iic_rd(pd, ICDR);
338 break;
339 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
340 iic_wr(pd, ICIC,
341 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
342 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
343 break;
344 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
345 iic_wr(pd, ICIC,
346 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
347 ret = iic_rd(pd, ICDR);
348 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
349 break;
350 }
351
352 spin_unlock_irqrestore(&pd->lock, flags);
353
354 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
355 return ret;
356 }
357
358 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
359 {
360 return pd->pos == -1;
361 }
362
363 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
364 {
365 return pd->pos == pd->msg->len - 1;
366 }
367
368 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
369 unsigned char *buf)
370 {
371 switch (pd->pos) {
372 case -1:
373 *buf = (pd->msg->addr & 0x7f) << 1;
374 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
375 break;
376 default:
377 *buf = pd->msg->buf[pd->pos];
378 }
379 }
380
381 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
382 {
383 unsigned char data;
384
385 if (pd->pos == pd->msg->len)
386 return 1;
387
388 sh_mobile_i2c_get_data(pd, &data);
389
390 if (sh_mobile_i2c_is_last_byte(pd))
391 i2c_op(pd, OP_TX_STOP, data);
392 else if (sh_mobile_i2c_is_first_byte(pd))
393 i2c_op(pd, OP_TX_FIRST, data);
394 else
395 i2c_op(pd, OP_TX, data);
396
397 pd->pos++;
398 return 0;
399 }
400
401 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
402 {
403 unsigned char data;
404 int real_pos;
405
406 do {
407 if (pd->pos <= -1) {
408 sh_mobile_i2c_get_data(pd, &data);
409
410 if (sh_mobile_i2c_is_first_byte(pd))
411 i2c_op(pd, OP_TX_FIRST, data);
412 else
413 i2c_op(pd, OP_TX, data);
414 break;
415 }
416
417 if (pd->pos == 0) {
418 i2c_op(pd, OP_TX_TO_RX, 0);
419 break;
420 }
421
422 real_pos = pd->pos - 2;
423
424 if (pd->pos == pd->msg->len) {
425 if (real_pos < 0) {
426 i2c_op(pd, OP_RX_STOP, 0);
427 break;
428 }
429 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
430 } else
431 data = i2c_op(pd, OP_RX, 0);
432
433 if (real_pos >= 0)
434 pd->msg->buf[real_pos] = data;
435 } while (0);
436
437 pd->pos++;
438 return pd->pos == (pd->msg->len + 2);
439 }
440
441 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
442 {
443 struct platform_device *dev = dev_id;
444 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
445 unsigned char sr;
446 int wakeup;
447
448 sr = iic_rd(pd, ICSR);
449 pd->sr |= sr; /* remember state */
450
451 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
452 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
453 pd->pos, pd->msg->len);
454
455 if (sr & (ICSR_AL | ICSR_TACK)) {
456 /* don't interrupt transaction - continue to issue stop */
457 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
458 wakeup = 0;
459 } else if (pd->msg->flags & I2C_M_RD)
460 wakeup = sh_mobile_i2c_isr_rx(pd);
461 else
462 wakeup = sh_mobile_i2c_isr_tx(pd);
463
464 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
465 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
466
467 if (wakeup) {
468 pd->sr |= SW_DONE;
469 wake_up(&pd->wait);
470 }
471
472 /* defeat write posting to avoid spurious WAIT interrupts */
473 iic_rd(pd, ICSR);
474
475 return IRQ_HANDLED;
476 }
477
478 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
479 bool do_init)
480 {
481 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
482 dev_err(pd->dev, "Unsupported zero length i2c read\n");
483 return -EOPNOTSUPP;
484 }
485
486 if (do_init) {
487 /* Initialize channel registers */
488 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
489
490 /* Enable channel and configure rx ack */
491 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
492
493 /* Set the clock */
494 iic_wr(pd, ICCL, pd->iccl & 0xff);
495 iic_wr(pd, ICCH, pd->icch & 0xff);
496 }
497
498 pd->msg = usr_msg;
499 pd->pos = -1;
500 pd->sr = 0;
501
502 /* Enable all interrupts to begin with */
503 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
504 return 0;
505 }
506
507 static int poll_dte(struct sh_mobile_i2c_data *pd)
508 {
509 int i;
510
511 for (i = 1000; i; i--) {
512 u_int8_t val = iic_rd(pd, ICSR);
513
514 if (val & ICSR_DTE)
515 break;
516
517 if (val & ICSR_TACK)
518 return -ENXIO;
519
520 udelay(10);
521 }
522
523 return i ? 0 : -ETIMEDOUT;
524 }
525
526 static int poll_busy(struct sh_mobile_i2c_data *pd)
527 {
528 int i;
529
530 for (i = 1000; i; i--) {
531 u_int8_t val = iic_rd(pd, ICSR);
532
533 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
534
535 /* the interrupt handler may wake us up before the
536 * transfer is finished, so poll the hardware
537 * until we're done.
538 */
539 if (!(val & ICSR_BUSY)) {
540 /* handle missing acknowledge and arbitration lost */
541 val |= pd->sr;
542 if (val & ICSR_TACK)
543 return -ENXIO;
544 if (val & ICSR_AL)
545 return -EAGAIN;
546 break;
547 }
548
549 udelay(10);
550 }
551
552 return i ? 0 : -ETIMEDOUT;
553 }
554
555 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
556 struct i2c_msg *msgs,
557 int num)
558 {
559 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
560 struct i2c_msg *msg;
561 int err = 0;
562 int i, k;
563
564 activate_ch(pd);
565
566 /* Process all messages */
567 for (i = 0; i < num; i++) {
568 bool do_start = pd->send_stop || !i;
569 msg = &msgs[i];
570 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
571
572 err = start_ch(pd, msg, do_start);
573 if (err)
574 break;
575
576 if (do_start)
577 i2c_op(pd, OP_START, 0);
578
579 /* The interrupt handler takes care of the rest... */
580 k = wait_event_timeout(pd->wait,
581 pd->sr & (ICSR_TACK | SW_DONE),
582 5 * HZ);
583 if (!k) {
584 dev_err(pd->dev, "Transfer request timed out\n");
585 err = -ETIMEDOUT;
586 break;
587 }
588
589 if (pd->send_stop)
590 err = poll_busy(pd);
591 else
592 err = poll_dte(pd);
593 if (err < 0)
594 break;
595 }
596
597 deactivate_ch(pd);
598
599 if (!err)
600 err = num;
601 return err;
602 }
603
604 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
605 {
606 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
607 }
608
609 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
610 .functionality = sh_mobile_i2c_func,
611 .master_xfer = sh_mobile_i2c_xfer,
612 };
613
614 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
615 {
616 struct resource *res;
617 int ret = -ENXIO;
618 int n, k = 0;
619
620 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
621 for (n = res->start; hook && n <= res->end; n++) {
622 if (request_irq(n, sh_mobile_i2c_isr, 0,
623 dev_name(&dev->dev), dev)) {
624 for (n--; n >= res->start; n--)
625 free_irq(n, dev);
626
627 goto rollback;
628 }
629 }
630 k++;
631 }
632
633 if (hook)
634 return k > 0 ? 0 : -ENOENT;
635
636 ret = 0;
637
638 rollback:
639 k--;
640
641 while (k >= 0) {
642 res = platform_get_resource(dev, IORESOURCE_IRQ, k);
643 for (n = res->start; n <= res->end; n++)
644 free_irq(n, dev);
645
646 k--;
647 }
648
649 return ret;
650 }
651
652 static int sh_mobile_i2c_probe(struct platform_device *dev)
653 {
654 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
655 struct sh_mobile_i2c_data *pd;
656 struct i2c_adapter *adap;
657 struct resource *res;
658 int size;
659 int ret;
660 u32 bus_speed;
661
662 pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
663 if (pd == NULL) {
664 dev_err(&dev->dev, "cannot allocate private data\n");
665 return -ENOMEM;
666 }
667
668 pd->clk = clk_get(&dev->dev, NULL);
669 if (IS_ERR(pd->clk)) {
670 dev_err(&dev->dev, "cannot get clock\n");
671 ret = PTR_ERR(pd->clk);
672 goto err;
673 }
674
675 ret = sh_mobile_i2c_hook_irqs(dev, 1);
676 if (ret) {
677 dev_err(&dev->dev, "cannot request IRQ\n");
678 goto err_clk;
679 }
680
681 pd->dev = &dev->dev;
682 platform_set_drvdata(dev, pd);
683
684 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
685 if (res == NULL) {
686 dev_err(&dev->dev, "cannot find IO resource\n");
687 ret = -ENOENT;
688 goto err_irq;
689 }
690
691 size = resource_size(res);
692
693 pd->reg = ioremap(res->start, size);
694 if (pd->reg == NULL) {
695 dev_err(&dev->dev, "cannot map IO\n");
696 ret = -ENXIO;
697 goto err_irq;
698 }
699
700 /* Use platform data bus speed or STANDARD_MODE */
701 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
702 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
703
704 if (pdata && pdata->bus_speed)
705 pd->bus_speed = pdata->bus_speed;
706 pd->clks_per_count = 1;
707 if (pdata && pdata->clks_per_count)
708 pd->clks_per_count = pdata->clks_per_count;
709
710 /* The IIC blocks on SH-Mobile ARM processors
711 * come with two new bits in ICIC.
712 */
713 if (size > 0x17)
714 pd->flags |= IIC_FLAG_HAS_ICIC67;
715
716 sh_mobile_i2c_init(pd);
717
718 /* Enable Runtime PM for this device.
719 *
720 * Also tell the Runtime PM core to ignore children
721 * for this device since it is valid for us to suspend
722 * this I2C master driver even though the slave devices
723 * on the I2C bus may not be suspended.
724 *
725 * The state of the I2C hardware bus is unaffected by
726 * the Runtime PM state.
727 */
728 pm_suspend_ignore_children(&dev->dev, true);
729 pm_runtime_enable(&dev->dev);
730
731 /* setup the private data */
732 adap = &pd->adap;
733 i2c_set_adapdata(adap, pd);
734
735 adap->owner = THIS_MODULE;
736 adap->algo = &sh_mobile_i2c_algorithm;
737 adap->dev.parent = &dev->dev;
738 adap->retries = 5;
739 adap->nr = dev->id;
740 adap->dev.of_node = dev->dev.of_node;
741
742 strlcpy(adap->name, dev->name, sizeof(adap->name));
743
744 spin_lock_init(&pd->lock);
745 init_waitqueue_head(&pd->wait);
746
747 ret = i2c_add_numbered_adapter(adap);
748 if (ret < 0) {
749 dev_err(&dev->dev, "cannot add numbered adapter\n");
750 goto err_all;
751 }
752
753 dev_info(&dev->dev,
754 "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n",
755 adap->nr, pd->bus_speed, pd->iccl, pd->icch);
756
757 return 0;
758
759 err_all:
760 iounmap(pd->reg);
761 err_irq:
762 sh_mobile_i2c_hook_irqs(dev, 0);
763 err_clk:
764 clk_put(pd->clk);
765 err:
766 kfree(pd);
767 return ret;
768 }
769
770 static int sh_mobile_i2c_remove(struct platform_device *dev)
771 {
772 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
773
774 i2c_del_adapter(&pd->adap);
775 iounmap(pd->reg);
776 sh_mobile_i2c_hook_irqs(dev, 0);
777 clk_put(pd->clk);
778 pm_runtime_disable(&dev->dev);
779 kfree(pd);
780 return 0;
781 }
782
783 static int sh_mobile_i2c_runtime_nop(struct device *dev)
784 {
785 /* Runtime PM callback shared between ->runtime_suspend()
786 * and ->runtime_resume(). Simply returns success.
787 *
788 * This driver re-initializes all registers after
789 * pm_runtime_get_sync() anyway so there is no need
790 * to save and restore registers here.
791 */
792 return 0;
793 }
794
795 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
796 .runtime_suspend = sh_mobile_i2c_runtime_nop,
797 .runtime_resume = sh_mobile_i2c_runtime_nop,
798 };
799
800 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
801 { .compatible = "renesas,rmobile-iic", },
802 {},
803 };
804 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
805
806 static struct platform_driver sh_mobile_i2c_driver = {
807 .driver = {
808 .name = "i2c-sh_mobile",
809 .owner = THIS_MODULE,
810 .pm = &sh_mobile_i2c_dev_pm_ops,
811 .of_match_table = sh_mobile_i2c_dt_ids,
812 },
813 .probe = sh_mobile_i2c_probe,
814 .remove = sh_mobile_i2c_remove,
815 };
816
817 static int __init sh_mobile_i2c_adap_init(void)
818 {
819 return platform_driver_register(&sh_mobile_i2c_driver);
820 }
821
822 static void __exit sh_mobile_i2c_adap_exit(void)
823 {
824 platform_driver_unregister(&sh_mobile_i2c_driver);
825 }
826
827 subsys_initcall(sh_mobile_i2c_adap_init);
828 module_exit(sh_mobile_i2c_adap_exit);
829
830 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
831 MODULE_AUTHOR("Magnus Damm");
832 MODULE_LICENSE("GPL v2");
833 MODULE_ALIAS("platform:i2c-sh_mobile");
Linux kernel - Deliverables
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