2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
20 * Note that final HPT370 support was done by force extraction of GPL.
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * Alan Cox <alan@lxorguk.ukuu.org.uk>
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
122 #include <linux/types.h>
123 #include <linux/module.h>
124 #include <linux/kernel.h>
125 #include <linux/delay.h>
126 #include <linux/blkdev.h>
127 #include <linux/interrupt.h>
128 #include <linux/pci.h>
129 #include <linux/init.h>
130 #include <linux/ide.h>
132 #include <asm/uaccess.h>
135 #define DRV_NAME "hpt366"
137 /* various tuning parameters */
138 #undef HPT_RESET_STATE_ENGINE
139 #undef HPT_DELAY_INTERRUPT
141 static const char *quirk_drives
[] = {
142 "QUANTUM FIREBALLlct08 08",
143 "QUANTUM FIREBALLP KA6.4",
144 "QUANTUM FIREBALLP KA9.1",
145 "QUANTUM FIREBALLP KX13.6",
146 "QUANTUM FIREBALLP KX20.5",
147 "QUANTUM FIREBALLP KX27.3",
148 "QUANTUM FIREBALLP LM20.4",
149 "QUANTUM FIREBALLP LM20.5",
153 static const char *bad_ata100_5
[] = {
172 static const char *bad_ata66_4
[] = {
188 "MAXTOR STM3320620A",
192 static const char *bad_ata66_3
[] = {
197 static const char *bad_ata33
[] = {
198 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
199 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
200 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
202 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
203 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
204 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
208 static u8 xfer_speeds
[] = {
228 /* Key for bus clock timings
231 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
233 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
235 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
237 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
239 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
240 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
241 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
243 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
244 * task file register access.
247 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
252 static u32 forty_base_hpt36x
[] = {
253 /* XFER_UDMA_6 */ 0x900fd943,
254 /* XFER_UDMA_5 */ 0x900fd943,
255 /* XFER_UDMA_4 */ 0x900fd943,
256 /* XFER_UDMA_3 */ 0x900ad943,
257 /* XFER_UDMA_2 */ 0x900bd943,
258 /* XFER_UDMA_1 */ 0x9008d943,
259 /* XFER_UDMA_0 */ 0x9008d943,
261 /* XFER_MW_DMA_2 */ 0xa008d943,
262 /* XFER_MW_DMA_1 */ 0xa010d955,
263 /* XFER_MW_DMA_0 */ 0xa010d9fc,
265 /* XFER_PIO_4 */ 0xc008d963,
266 /* XFER_PIO_3 */ 0xc010d974,
267 /* XFER_PIO_2 */ 0xc010d997,
268 /* XFER_PIO_1 */ 0xc010d9c7,
269 /* XFER_PIO_0 */ 0xc018d9d9
272 static u32 thirty_three_base_hpt36x
[] = {
273 /* XFER_UDMA_6 */ 0x90c9a731,
274 /* XFER_UDMA_5 */ 0x90c9a731,
275 /* XFER_UDMA_4 */ 0x90c9a731,
276 /* XFER_UDMA_3 */ 0x90cfa731,
277 /* XFER_UDMA_2 */ 0x90caa731,
278 /* XFER_UDMA_1 */ 0x90cba731,
279 /* XFER_UDMA_0 */ 0x90c8a731,
281 /* XFER_MW_DMA_2 */ 0xa0c8a731,
282 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
283 /* XFER_MW_DMA_0 */ 0xa0c8a797,
285 /* XFER_PIO_4 */ 0xc0c8a731,
286 /* XFER_PIO_3 */ 0xc0c8a742,
287 /* XFER_PIO_2 */ 0xc0d0a753,
288 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
289 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
292 static u32 twenty_five_base_hpt36x
[] = {
293 /* XFER_UDMA_6 */ 0x90c98521,
294 /* XFER_UDMA_5 */ 0x90c98521,
295 /* XFER_UDMA_4 */ 0x90c98521,
296 /* XFER_UDMA_3 */ 0x90cf8521,
297 /* XFER_UDMA_2 */ 0x90cf8521,
298 /* XFER_UDMA_1 */ 0x90cb8521,
299 /* XFER_UDMA_0 */ 0x90cb8521,
301 /* XFER_MW_DMA_2 */ 0xa0ca8521,
302 /* XFER_MW_DMA_1 */ 0xa0ca8532,
303 /* XFER_MW_DMA_0 */ 0xa0ca8575,
305 /* XFER_PIO_4 */ 0xc0ca8521,
306 /* XFER_PIO_3 */ 0xc0ca8532,
307 /* XFER_PIO_2 */ 0xc0ca8542,
308 /* XFER_PIO_1 */ 0xc0d08572,
309 /* XFER_PIO_0 */ 0xc0d08585
313 /* These are the timing tables from the HighPoint open source drivers... */
314 static u32 thirty_three_base_hpt37x
[] = {
315 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
316 /* XFER_UDMA_5 */ 0x12446231,
317 /* XFER_UDMA_4 */ 0x12446231,
318 /* XFER_UDMA_3 */ 0x126c6231,
319 /* XFER_UDMA_2 */ 0x12486231,
320 /* XFER_UDMA_1 */ 0x124c6233,
321 /* XFER_UDMA_0 */ 0x12506297,
323 /* XFER_MW_DMA_2 */ 0x22406c31,
324 /* XFER_MW_DMA_1 */ 0x22406c33,
325 /* XFER_MW_DMA_0 */ 0x22406c97,
327 /* XFER_PIO_4 */ 0x06414e31,
328 /* XFER_PIO_3 */ 0x06414e42,
329 /* XFER_PIO_2 */ 0x06414e53,
330 /* XFER_PIO_1 */ 0x06814e93,
331 /* XFER_PIO_0 */ 0x06814ea7
334 static u32 fifty_base_hpt37x
[] = {
335 /* XFER_UDMA_6 */ 0x12848242,
336 /* XFER_UDMA_5 */ 0x12848242,
337 /* XFER_UDMA_4 */ 0x12ac8242,
338 /* XFER_UDMA_3 */ 0x128c8242,
339 /* XFER_UDMA_2 */ 0x120c8242,
340 /* XFER_UDMA_1 */ 0x12148254,
341 /* XFER_UDMA_0 */ 0x121882ea,
343 /* XFER_MW_DMA_2 */ 0x22808242,
344 /* XFER_MW_DMA_1 */ 0x22808254,
345 /* XFER_MW_DMA_0 */ 0x228082ea,
347 /* XFER_PIO_4 */ 0x0a81f442,
348 /* XFER_PIO_3 */ 0x0a81f443,
349 /* XFER_PIO_2 */ 0x0a81f454,
350 /* XFER_PIO_1 */ 0x0ac1f465,
351 /* XFER_PIO_0 */ 0x0ac1f48a
354 static u32 sixty_six_base_hpt37x
[] = {
355 /* XFER_UDMA_6 */ 0x1c869c62,
356 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
357 /* XFER_UDMA_4 */ 0x1c8a9c62,
358 /* XFER_UDMA_3 */ 0x1c8e9c62,
359 /* XFER_UDMA_2 */ 0x1c929c62,
360 /* XFER_UDMA_1 */ 0x1c9a9c62,
361 /* XFER_UDMA_0 */ 0x1c829c62,
363 /* XFER_MW_DMA_2 */ 0x2c829c62,
364 /* XFER_MW_DMA_1 */ 0x2c829c66,
365 /* XFER_MW_DMA_0 */ 0x2c829d2e,
367 /* XFER_PIO_4 */ 0x0c829c62,
368 /* XFER_PIO_3 */ 0x0c829c84,
369 /* XFER_PIO_2 */ 0x0c829ca6,
370 /* XFER_PIO_1 */ 0x0d029d26,
371 /* XFER_PIO_0 */ 0x0d029d5e
375 * The following are the new timing tables with PIO mode data/taskfile transfer
376 * overclocking fixed...
379 /* This table is taken from the HPT370 data manual rev. 1.02 */
380 static u32 thirty_three_base_hpt37x
[] = {
381 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
382 /* XFER_UDMA_5 */ 0x16455031,
383 /* XFER_UDMA_4 */ 0x16455031,
384 /* XFER_UDMA_3 */ 0x166d5031,
385 /* XFER_UDMA_2 */ 0x16495031,
386 /* XFER_UDMA_1 */ 0x164d5033,
387 /* XFER_UDMA_0 */ 0x16515097,
389 /* XFER_MW_DMA_2 */ 0x26515031,
390 /* XFER_MW_DMA_1 */ 0x26515033,
391 /* XFER_MW_DMA_0 */ 0x26515097,
393 /* XFER_PIO_4 */ 0x06515021,
394 /* XFER_PIO_3 */ 0x06515022,
395 /* XFER_PIO_2 */ 0x06515033,
396 /* XFER_PIO_1 */ 0x06915065,
397 /* XFER_PIO_0 */ 0x06d1508a
400 static u32 fifty_base_hpt37x
[] = {
401 /* XFER_UDMA_6 */ 0x1a861842,
402 /* XFER_UDMA_5 */ 0x1a861842,
403 /* XFER_UDMA_4 */ 0x1aae1842,
404 /* XFER_UDMA_3 */ 0x1a8e1842,
405 /* XFER_UDMA_2 */ 0x1a0e1842,
406 /* XFER_UDMA_1 */ 0x1a161854,
407 /* XFER_UDMA_0 */ 0x1a1a18ea,
409 /* XFER_MW_DMA_2 */ 0x2a821842,
410 /* XFER_MW_DMA_1 */ 0x2a821854,
411 /* XFER_MW_DMA_0 */ 0x2a8218ea,
413 /* XFER_PIO_4 */ 0x0a821842,
414 /* XFER_PIO_3 */ 0x0a821843,
415 /* XFER_PIO_2 */ 0x0a821855,
416 /* XFER_PIO_1 */ 0x0ac218a8,
417 /* XFER_PIO_0 */ 0x0b02190c
420 static u32 sixty_six_base_hpt37x
[] = {
421 /* XFER_UDMA_6 */ 0x1c86fe62,
422 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
423 /* XFER_UDMA_4 */ 0x1c8afe62,
424 /* XFER_UDMA_3 */ 0x1c8efe62,
425 /* XFER_UDMA_2 */ 0x1c92fe62,
426 /* XFER_UDMA_1 */ 0x1c9afe62,
427 /* XFER_UDMA_0 */ 0x1c82fe62,
429 /* XFER_MW_DMA_2 */ 0x2c82fe62,
430 /* XFER_MW_DMA_1 */ 0x2c82fe66,
431 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
433 /* XFER_PIO_4 */ 0x0c82fe62,
434 /* XFER_PIO_3 */ 0x0c82fe84,
435 /* XFER_PIO_2 */ 0x0c82fea6,
436 /* XFER_PIO_1 */ 0x0d02ff26,
437 /* XFER_PIO_0 */ 0x0d42ff7f
441 #define HPT366_DEBUG_DRIVE_INFO 0
442 #define HPT371_ALLOW_ATA133_6 1
443 #define HPT302_ALLOW_ATA133_6 1
444 #define HPT372_ALLOW_ATA133_6 1
445 #define HPT370_ALLOW_ATA100_5 0
446 #define HPT366_ALLOW_ATA66_4 1
447 #define HPT366_ALLOW_ATA66_3 1
448 #define HPT366_MAX_DEVS 8
450 /* Supported ATA clock frequencies */
464 u32
*clock_table
[NUM_ATA_CLOCKS
];
468 * Hold all the HighPoint chip information in one place.
472 char *chip_name
; /* Chip name */
473 u8 chip_type
; /* Chip type */
474 u8 udma_mask
; /* Allowed UltraDMA modes mask. */
475 u8 dpll_clk
; /* DPLL clock in MHz */
476 u8 pci_clk
; /* PCI clock in MHz */
477 struct hpt_timings
*timings
; /* Chipset timing data */
478 u8 clock
; /* ATA clock selected */
481 /* Supported HighPoint chips */
496 static struct hpt_timings hpt36x_timings
= {
497 .pio_mask
= 0xc1f8ffff,
498 .dma_mask
= 0x303800ff,
499 .ultra_mask
= 0x30070000,
501 [ATA_CLOCK_25MHZ
] = twenty_five_base_hpt36x
,
502 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt36x
,
503 [ATA_CLOCK_40MHZ
] = forty_base_hpt36x
,
504 [ATA_CLOCK_50MHZ
] = NULL
,
505 [ATA_CLOCK_66MHZ
] = NULL
509 static struct hpt_timings hpt37x_timings
= {
510 .pio_mask
= 0xcfc3ffff,
511 .dma_mask
= 0x31c001ff,
512 .ultra_mask
= 0x303c0000,
514 [ATA_CLOCK_25MHZ
] = NULL
,
515 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt37x
,
516 [ATA_CLOCK_40MHZ
] = NULL
,
517 [ATA_CLOCK_50MHZ
] = fifty_base_hpt37x
,
518 [ATA_CLOCK_66MHZ
] = sixty_six_base_hpt37x
522 static const struct hpt_info hpt36x __devinitdata
= {
523 .chip_name
= "HPT36x",
525 .udma_mask
= HPT366_ALLOW_ATA66_3
? (HPT366_ALLOW_ATA66_4
? ATA_UDMA4
: ATA_UDMA3
) : ATA_UDMA2
,
526 .dpll_clk
= 0, /* no DPLL */
527 .timings
= &hpt36x_timings
530 static const struct hpt_info hpt370 __devinitdata
= {
531 .chip_name
= "HPT370",
533 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
535 .timings
= &hpt37x_timings
538 static const struct hpt_info hpt370a __devinitdata
= {
539 .chip_name
= "HPT370A",
540 .chip_type
= HPT370A
,
541 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
543 .timings
= &hpt37x_timings
546 static const struct hpt_info hpt374 __devinitdata
= {
547 .chip_name
= "HPT374",
549 .udma_mask
= ATA_UDMA5
,
551 .timings
= &hpt37x_timings
554 static const struct hpt_info hpt372 __devinitdata
= {
555 .chip_name
= "HPT372",
557 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
559 .timings
= &hpt37x_timings
562 static const struct hpt_info hpt372a __devinitdata
= {
563 .chip_name
= "HPT372A",
564 .chip_type
= HPT372A
,
565 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
567 .timings
= &hpt37x_timings
570 static const struct hpt_info hpt302 __devinitdata
= {
571 .chip_name
= "HPT302",
573 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
575 .timings
= &hpt37x_timings
578 static const struct hpt_info hpt371 __devinitdata
= {
579 .chip_name
= "HPT371",
581 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
583 .timings
= &hpt37x_timings
586 static const struct hpt_info hpt372n __devinitdata
= {
587 .chip_name
= "HPT372N",
588 .chip_type
= HPT372N
,
589 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
591 .timings
= &hpt37x_timings
594 static const struct hpt_info hpt302n __devinitdata
= {
595 .chip_name
= "HPT302N",
596 .chip_type
= HPT302N
,
597 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
599 .timings
= &hpt37x_timings
602 static const struct hpt_info hpt371n __devinitdata
= {
603 .chip_name
= "HPT371N",
604 .chip_type
= HPT371N
,
605 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
607 .timings
= &hpt37x_timings
610 static int check_in_drive_list(ide_drive_t
*drive
, const char **list
)
612 char *m
= (char *)&drive
->id
[ATA_ID_PROD
];
615 if (!strcmp(*list
++, m
))
620 static struct hpt_info
*hpt3xx_get_info(struct device
*dev
)
622 struct ide_host
*host
= dev_get_drvdata(dev
);
623 struct hpt_info
*info
= (struct hpt_info
*)host
->host_priv
;
625 return dev
== host
->dev
[1] ? info
+ 1 : info
;
629 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
630 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
633 static u8
hpt3xx_udma_filter(ide_drive_t
*drive
)
635 ide_hwif_t
*hwif
= drive
->hwif
;
636 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
637 u8 mask
= hwif
->ultra_mask
;
639 switch (info
->chip_type
) {
641 if (!HPT366_ALLOW_ATA66_4
||
642 check_in_drive_list(drive
, bad_ata66_4
))
645 if (!HPT366_ALLOW_ATA66_3
||
646 check_in_drive_list(drive
, bad_ata66_3
))
650 if (!HPT370_ALLOW_ATA100_5
||
651 check_in_drive_list(drive
, bad_ata100_5
))
655 if (!HPT370_ALLOW_ATA100_5
||
656 check_in_drive_list(drive
, bad_ata100_5
))
662 if (ata_id_is_sata(drive
->id
))
669 return check_in_drive_list(drive
, bad_ata33
) ? 0x00 : mask
;
672 static u8
hpt3xx_mdma_filter(ide_drive_t
*drive
)
674 ide_hwif_t
*hwif
= drive
->hwif
;
675 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
677 switch (info
->chip_type
) {
682 if (ata_id_is_sata(drive
->id
))
690 static u32
get_speed_setting(u8 speed
, struct hpt_info
*info
)
695 * Lookup the transfer mode table to get the index into
698 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
700 for (i
= 0; i
< ARRAY_SIZE(xfer_speeds
) - 1; i
++)
701 if (xfer_speeds
[i
] == speed
)
704 return info
->timings
->clock_table
[info
->clock
][i
];
707 static void hpt3xx_set_mode(ide_drive_t
*drive
, const u8 speed
)
709 ide_hwif_t
*hwif
= drive
->hwif
;
710 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
711 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
712 struct hpt_timings
*t
= info
->timings
;
713 u8 itr_addr
= 0x40 + (drive
->dn
* 4);
715 u32 new_itr
= get_speed_setting(speed
, info
);
716 u32 itr_mask
= speed
< XFER_MW_DMA_0
? t
->pio_mask
:
717 (speed
< XFER_UDMA_0
? t
->dma_mask
:
720 pci_read_config_dword(dev
, itr_addr
, &old_itr
);
721 new_itr
= (old_itr
& ~itr_mask
) | (new_itr
& itr_mask
);
723 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
724 * to avoid problems handling I/O errors later
726 new_itr
&= ~0xc0000000;
728 pci_write_config_dword(dev
, itr_addr
, new_itr
);
731 static void hpt3xx_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
733 hpt3xx_set_mode(drive
, XFER_PIO_0
+ pio
);
736 static void hpt3xx_quirkproc(ide_drive_t
*drive
)
738 char *m
= (char *)&drive
->id
[ATA_ID_PROD
];
739 const char **list
= quirk_drives
;
742 if (strstr(m
, *list
++)) {
743 drive
->quirk_list
= 2;
747 drive
->quirk_list
= 0;
750 static void hpt3xx_maskproc(ide_drive_t
*drive
, int mask
)
752 ide_hwif_t
*hwif
= drive
->hwif
;
753 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
754 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
756 if (drive
->quirk_list
== 0)
759 if (info
->chip_type
>= HPT370
) {
762 pci_read_config_byte(dev
, 0x5a, &scr1
);
763 if (((scr1
& 0x10) >> 4) != mask
) {
768 pci_write_config_byte(dev
, 0x5a, scr1
);
771 disable_irq(hwif
->irq
);
773 enable_irq(hwif
->irq
);
777 * This is specific to the HPT366 UDMA chipset
778 * by HighPoint|Triones Technologies, Inc.
780 static void hpt366_dma_lost_irq(ide_drive_t
*drive
)
782 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
783 u8 mcr1
= 0, mcr3
= 0, scr1
= 0;
785 pci_read_config_byte(dev
, 0x50, &mcr1
);
786 pci_read_config_byte(dev
, 0x52, &mcr3
);
787 pci_read_config_byte(dev
, 0x5a, &scr1
);
788 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
789 drive
->name
, __func__
, mcr1
, mcr3
, scr1
);
791 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
792 ide_dma_lost_irq(drive
);
795 static void hpt370_clear_engine(ide_drive_t
*drive
)
797 ide_hwif_t
*hwif
= drive
->hwif
;
798 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
800 pci_write_config_byte(dev
, hwif
->select_data
, 0x37);
804 static void hpt370_irq_timeout(ide_drive_t
*drive
)
806 ide_hwif_t
*hwif
= drive
->hwif
;
807 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
811 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
812 printk(KERN_DEBUG
"%s: %d bytes in FIFO\n", drive
->name
, bfifo
& 0x1ff);
814 /* get DMA command mode */
815 dma_cmd
= inb(hwif
->dma_base
+ ATA_DMA_CMD
);
817 outb(dma_cmd
& ~ATA_DMA_START
, hwif
->dma_base
+ ATA_DMA_CMD
);
818 hpt370_clear_engine(drive
);
821 static void hpt370_dma_start(ide_drive_t
*drive
)
823 #ifdef HPT_RESET_STATE_ENGINE
824 hpt370_clear_engine(drive
);
826 ide_dma_start(drive
);
829 static int hpt370_dma_end(ide_drive_t
*drive
)
831 ide_hwif_t
*hwif
= drive
->hwif
;
832 u8 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
834 if (dma_stat
& ATA_DMA_ACTIVE
) {
837 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
838 if (dma_stat
& ATA_DMA_ACTIVE
)
839 hpt370_irq_timeout(drive
);
841 return ide_dma_end(drive
);
844 /* returns 1 if DMA IRQ issued, 0 otherwise */
845 static int hpt374_dma_test_irq(ide_drive_t
*drive
)
847 ide_hwif_t
*hwif
= drive
->hwif
;
848 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
852 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
854 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
858 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
859 /* return 1 if INTR asserted */
860 if (dma_stat
& ATA_DMA_INTR
)
866 static int hpt374_dma_end(ide_drive_t
*drive
)
868 ide_hwif_t
*hwif
= drive
->hwif
;
869 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
870 u8 mcr
= 0, mcr_addr
= hwif
->select_data
;
871 u8 bwsr
= 0, mask
= hwif
->channel
? 0x02 : 0x01;
873 pci_read_config_byte(dev
, 0x6a, &bwsr
);
874 pci_read_config_byte(dev
, mcr_addr
, &mcr
);
876 pci_write_config_byte(dev
, mcr_addr
, mcr
| 0x30);
877 return ide_dma_end(drive
);
881 * hpt3xxn_set_clock - perform clock switching dance
882 * @hwif: hwif to switch
883 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
885 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
888 static void hpt3xxn_set_clock(ide_hwif_t
*hwif
, u8 mode
)
890 unsigned long base
= hwif
->extra_base
;
891 u8 scr2
= inb(base
+ 0x6b);
893 if ((scr2
& 0x7f) == mode
)
896 /* Tristate the bus */
897 outb(0x80, base
+ 0x63);
898 outb(0x80, base
+ 0x67);
900 /* Switch clock and reset channels */
901 outb(mode
, base
+ 0x6b);
902 outb(0xc0, base
+ 0x69);
905 * Reset the state machines.
906 * NOTE: avoid accidentally enabling the disabled channels.
908 outb(inb(base
+ 0x60) | 0x32, base
+ 0x60);
909 outb(inb(base
+ 0x64) | 0x32, base
+ 0x64);
912 outb(0x00, base
+ 0x69);
914 /* Reconnect channels to bus */
915 outb(0x00, base
+ 0x63);
916 outb(0x00, base
+ 0x67);
920 * hpt3xxn_rw_disk - prepare for I/O
921 * @drive: drive for command
922 * @rq: block request structure
924 * This is called when a disk I/O is issued to HPT3xxN.
925 * We need it because of the clock switching.
928 static void hpt3xxn_rw_disk(ide_drive_t
*drive
, struct request
*rq
)
930 hpt3xxn_set_clock(drive
->hwif
, rq_data_dir(rq
) ? 0x23 : 0x21);
934 * hpt37x_calibrate_dpll - calibrate the DPLL
937 * Perform a calibration cycle on the DPLL.
938 * Returns 1 if this succeeds
940 static int hpt37x_calibrate_dpll(struct pci_dev
*dev
, u16 f_low
, u16 f_high
)
942 u32 dpll
= (f_high
<< 16) | f_low
| 0x100;
946 pci_write_config_dword(dev
, 0x5c, dpll
);
948 /* Wait for oscillator ready */
949 for(i
= 0; i
< 0x5000; ++i
) {
951 pci_read_config_byte(dev
, 0x5b, &scr2
);
955 /* See if it stays ready (we'll just bail out if it's not yet) */
956 for(i
= 0; i
< 0x1000; ++i
) {
957 pci_read_config_byte(dev
, 0x5b, &scr2
);
958 /* DPLL destabilized? */
962 /* Turn off tuning, we have the DPLL set */
963 pci_read_config_dword (dev
, 0x5c, &dpll
);
964 pci_write_config_dword(dev
, 0x5c, (dpll
& ~0x100));
968 static void hpt3xx_disable_fast_irq(struct pci_dev
*dev
, u8 mcr_addr
)
970 struct ide_host
*host
= pci_get_drvdata(dev
);
971 struct hpt_info
*info
= host
->host_priv
+ (&dev
->dev
== host
->dev
[1]);
972 u8 chip_type
= info
->chip_type
;
973 u8 new_mcr
, old_mcr
= 0;
976 * Disable the "fast interrupt" prediction. Don't hold off
977 * on interrupts. (== 0x01 despite what the docs say)
979 pci_read_config_byte(dev
, mcr_addr
+ 1, &old_mcr
);
981 if (chip_type
>= HPT374
)
982 new_mcr
= old_mcr
& ~0x07;
983 else if (chip_type
>= HPT370
) {
986 #ifdef HPT_DELAY_INTERRUPT
991 } else /* HPT366 and HPT368 */
992 new_mcr
= old_mcr
& ~0x80;
994 if (new_mcr
!= old_mcr
)
995 pci_write_config_byte(dev
, mcr_addr
+ 1, new_mcr
);
998 static int init_chipset_hpt366(struct pci_dev
*dev
)
1000 unsigned long io_base
= pci_resource_start(dev
, 4);
1001 struct hpt_info
*info
= hpt3xx_get_info(&dev
->dev
);
1002 const char *name
= DRV_NAME
;
1003 u8 pci_clk
, dpll_clk
= 0; /* PCI and DPLL clock in MHz */
1005 enum ata_clock clock
;
1007 chip_type
= info
->chip_type
;
1009 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (L1_CACHE_BYTES
/ 4));
1010 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x78);
1011 pci_write_config_byte(dev
, PCI_MIN_GNT
, 0x08);
1012 pci_write_config_byte(dev
, PCI_MAX_LAT
, 0x08);
1015 * First, try to estimate the PCI clock frequency...
1017 if (chip_type
>= HPT370
) {
1022 /* Interrupt force enable. */
1023 pci_read_config_byte(dev
, 0x5a, &scr1
);
1025 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
1028 * HighPoint does this for HPT372A.
1029 * NOTE: This register is only writeable via I/O space.
1031 if (chip_type
== HPT372A
)
1032 outb(0x0e, io_base
+ 0x9c);
1035 * Default to PCI clock. Make sure MA15/16 are set to output
1036 * to prevent drives having problems with 40-pin cables.
1038 pci_write_config_byte(dev
, 0x5b, 0x23);
1041 * We'll have to read f_CNT value in order to determine
1042 * the PCI clock frequency according to the following ratio:
1044 * f_CNT = Fpci * 192 / Fdpll
1046 * First try reading the register in which the HighPoint BIOS
1047 * saves f_CNT value before reprogramming the DPLL from its
1048 * default setting (which differs for the various chips).
1050 * NOTE: This register is only accessible via I/O space;
1051 * HPT374 BIOS only saves it for the function 0, so we have to
1052 * always read it from there -- no need to check the result of
1053 * pci_get_slot() for the function 0 as the whole device has
1054 * been already "pinned" (via function 1) in init_setup_hpt374()
1056 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1057 struct pci_dev
*dev1
= pci_get_slot(dev
->bus
,
1059 unsigned long io_base
= pci_resource_start(dev1
, 4);
1061 temp
= inl(io_base
+ 0x90);
1064 temp
= inl(io_base
+ 0x90);
1067 * In case the signature check fails, we'll have to
1068 * resort to reading the f_CNT register itself in hopes
1069 * that nobody has touched the DPLL yet...
1071 if ((temp
& 0xFFFFF000) != 0xABCDE000) {
1074 printk(KERN_WARNING
"%s %s: no clock data saved by "
1075 "BIOS\n", name
, pci_name(dev
));
1077 /* Calculate the average value of f_CNT. */
1078 for (temp
= i
= 0; i
< 128; i
++) {
1079 pci_read_config_word(dev
, 0x78, &f_cnt
);
1080 temp
+= f_cnt
& 0x1ff;
1085 f_cnt
= temp
& 0x1ff;
1087 dpll_clk
= info
->dpll_clk
;
1088 pci_clk
= (f_cnt
* dpll_clk
) / 192;
1090 /* Clamp PCI clock to bands. */
1093 else if(pci_clk
< 45)
1095 else if(pci_clk
< 55)
1100 printk(KERN_INFO
"%s %s: DPLL base: %d MHz, f_CNT: %d, "
1101 "assuming %d MHz PCI\n", name
, pci_name(dev
),
1102 dpll_clk
, f_cnt
, pci_clk
);
1106 pci_read_config_dword(dev
, 0x40, &itr1
);
1108 /* Detect PCI clock by looking at cmd_high_time. */
1109 switch((itr1
>> 8) & 0x07) {
1123 /* Let's assume we'll use PCI clock for the ATA clock... */
1126 clock
= ATA_CLOCK_25MHZ
;
1130 clock
= ATA_CLOCK_33MHZ
;
1133 clock
= ATA_CLOCK_40MHZ
;
1136 clock
= ATA_CLOCK_50MHZ
;
1139 clock
= ATA_CLOCK_66MHZ
;
1144 * Only try the DPLL if we don't have a table for the PCI clock that
1145 * we are running at for HPT370/A, always use it for anything newer...
1147 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1148 * We also don't like using the DPLL because this causes glitches
1149 * on PRST-/SRST- when the state engine gets reset...
1151 if (chip_type
>= HPT374
|| info
->timings
->clock_table
[clock
] == NULL
) {
1152 u16 f_low
, delta
= pci_clk
< 50 ? 2 : 4;
1156 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1157 * supported/enabled, use 50 MHz DPLL clock otherwise...
1159 if (info
->udma_mask
== ATA_UDMA6
) {
1161 clock
= ATA_CLOCK_66MHZ
;
1162 } else if (dpll_clk
) { /* HPT36x chips don't have DPLL */
1164 clock
= ATA_CLOCK_50MHZ
;
1167 if (info
->timings
->clock_table
[clock
] == NULL
) {
1168 printk(KERN_ERR
"%s %s: unknown bus timing!\n",
1169 name
, pci_name(dev
));
1173 /* Select the DPLL clock. */
1174 pci_write_config_byte(dev
, 0x5b, 0x21);
1177 * Adjust the DPLL based upon PCI clock, enable it,
1178 * and wait for stabilization...
1180 f_low
= (pci_clk
* 48) / dpll_clk
;
1182 for (adjust
= 0; adjust
< 8; adjust
++) {
1183 if(hpt37x_calibrate_dpll(dev
, f_low
, f_low
+ delta
))
1187 * See if it'll settle at a fractionally different clock
1190 f_low
-= adjust
>> 1;
1192 f_low
+= adjust
>> 1;
1195 printk(KERN_ERR
"%s %s: DPLL did not stabilize!\n",
1196 name
, pci_name(dev
));
1200 printk(KERN_INFO
"%s %s: using %d MHz DPLL clock\n",
1201 name
, pci_name(dev
), dpll_clk
);
1203 /* Mark the fact that we're not using the DPLL. */
1206 printk(KERN_INFO
"%s %s: using %d MHz PCI clock\n",
1207 name
, pci_name(dev
), pci_clk
);
1210 /* Store the clock frequencies. */
1211 info
->dpll_clk
= dpll_clk
;
1212 info
->pci_clk
= pci_clk
;
1213 info
->clock
= clock
;
1215 if (chip_type
>= HPT370
) {
1219 * Reset the state engines.
1220 * NOTE: Avoid accidentally enabling the disabled channels.
1222 pci_read_config_byte (dev
, 0x50, &mcr1
);
1223 pci_read_config_byte (dev
, 0x54, &mcr4
);
1224 pci_write_config_byte(dev
, 0x50, (mcr1
| 0x32));
1225 pci_write_config_byte(dev
, 0x54, (mcr4
| 0x32));
1230 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1231 * the MISC. register to stretch the UltraDMA Tss timing.
1232 * NOTE: This register is only writeable via I/O space.
1234 if (chip_type
== HPT371N
&& clock
== ATA_CLOCK_66MHZ
)
1235 outb(inb(io_base
+ 0x9c) | 0x04, io_base
+ 0x9c);
1237 hpt3xx_disable_fast_irq(dev
, 0x50);
1238 hpt3xx_disable_fast_irq(dev
, 0x54);
1243 static u8
hpt3xx_cable_detect(ide_hwif_t
*hwif
)
1245 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1246 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
1247 u8 chip_type
= info
->chip_type
;
1248 u8 scr1
= 0, ata66
= hwif
->channel
? 0x01 : 0x02;
1251 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1252 * address lines to access an external EEPROM. To read valid
1253 * cable detect state the pins must be enabled as inputs.
1255 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1257 * HPT374 PCI function 1
1258 * - set bit 15 of reg 0x52 to enable TCBLID as input
1259 * - set bit 15 of reg 0x56 to enable FCBLID as input
1261 u8 mcr_addr
= hwif
->select_data
+ 2;
1264 pci_read_config_word(dev
, mcr_addr
, &mcr
);
1265 pci_write_config_word(dev
, mcr_addr
, (mcr
| 0x8000));
1266 /* now read cable id register */
1267 pci_read_config_byte(dev
, 0x5a, &scr1
);
1268 pci_write_config_word(dev
, mcr_addr
, mcr
);
1269 } else if (chip_type
>= HPT370
) {
1271 * HPT370/372 and 374 pcifn 0
1272 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1276 pci_read_config_byte(dev
, 0x5b, &scr2
);
1277 pci_write_config_byte(dev
, 0x5b, (scr2
& ~1));
1278 /* now read cable id register */
1279 pci_read_config_byte(dev
, 0x5a, &scr1
);
1280 pci_write_config_byte(dev
, 0x5b, scr2
);
1282 pci_read_config_byte(dev
, 0x5a, &scr1
);
1284 return (scr1
& ata66
) ? ATA_CBL_PATA40
: ATA_CBL_PATA80
;
1287 static void __devinit
init_hwif_hpt366(ide_hwif_t
*hwif
)
1289 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
1290 u8 chip_type
= info
->chip_type
;
1292 /* Cache the channel's MISC. control registers' offset */
1293 hwif
->select_data
= hwif
->channel
? 0x54 : 0x50;
1296 * HPT3xxN chips have some complications:
1298 * - on 33 MHz PCI we must clock switch
1299 * - on 66 MHz PCI we must NOT use the PCI clock
1301 if (chip_type
>= HPT372N
&& info
->dpll_clk
&& info
->pci_clk
< 66) {
1303 * Clock is shared between the channels,
1304 * so we'll have to serialize them... :-(
1306 hwif
->host
->host_flags
|= IDE_HFLAG_SERIALIZE
;
1307 hwif
->rw_disk
= &hpt3xxn_rw_disk
;
1311 static int __devinit
init_dma_hpt366(ide_hwif_t
*hwif
,
1312 const struct ide_port_info
*d
)
1314 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1315 unsigned long flags
, base
= ide_pci_dma_base(hwif
, d
);
1316 u8 dma_old
, dma_new
, masterdma
= 0, slavedma
= 0;
1321 hwif
->dma_base
= base
;
1323 if (ide_pci_check_simplex(hwif
, d
) < 0)
1326 if (ide_pci_set_master(dev
, d
->name
) < 0)
1329 dma_old
= inb(base
+ 2);
1331 local_irq_save(flags
);
1334 pci_read_config_byte(dev
, hwif
->channel
? 0x4b : 0x43, &masterdma
);
1335 pci_read_config_byte(dev
, hwif
->channel
? 0x4f : 0x47, &slavedma
);
1337 if (masterdma
& 0x30) dma_new
|= 0x20;
1338 if ( slavedma
& 0x30) dma_new
|= 0x40;
1339 if (dma_new
!= dma_old
)
1340 outb(dma_new
, base
+ 2);
1342 local_irq_restore(flags
);
1344 printk(KERN_INFO
" %s: BM-DMA at 0x%04lx-0x%04lx\n",
1345 hwif
->name
, base
, base
+ 7);
1347 hwif
->extra_base
= base
+ (hwif
->channel
? 8 : 16);
1349 if (ide_allocate_dma_engine(hwif
))
1355 static void __devinit
hpt374_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1357 if (dev2
->irq
!= dev
->irq
) {
1358 /* FIXME: we need a core pci_set_interrupt() */
1359 dev2
->irq
= dev
->irq
;
1360 printk(KERN_INFO DRV_NAME
" %s: PCI config space interrupt "
1361 "fixed\n", pci_name(dev2
));
1365 static void __devinit
hpt371_init(struct pci_dev
*dev
)
1370 * HPT371 chips physically have only one channel, the secondary one,
1371 * but the primary channel registers do exist! Go figure...
1372 * So, we manually disable the non-existing channel here
1373 * (if the BIOS hasn't done this already).
1375 pci_read_config_byte(dev
, 0x50, &mcr1
);
1377 pci_write_config_byte(dev
, 0x50, mcr1
& ~0x04);
1380 static int __devinit
hpt36x_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1382 u8 mcr1
= 0, pin1
= 0, pin2
= 0;
1385 * Now we'll have to force both channels enabled if
1386 * at least one of them has been enabled by BIOS...
1388 pci_read_config_byte(dev
, 0x50, &mcr1
);
1390 pci_write_config_byte(dev
, 0x50, mcr1
| 0x30);
1392 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin1
);
1393 pci_read_config_byte(dev2
, PCI_INTERRUPT_PIN
, &pin2
);
1395 if (pin1
!= pin2
&& dev
->irq
== dev2
->irq
) {
1396 printk(KERN_INFO DRV_NAME
" %s: onboard version of chipset, "
1397 "pin1=%d pin2=%d\n", pci_name(dev
), pin1
, pin2
);
1404 #define IDE_HFLAGS_HPT3XX \
1405 (IDE_HFLAG_NO_ATAPI_DMA | \
1406 IDE_HFLAG_OFF_BOARD)
1408 static const struct ide_port_ops hpt3xx_port_ops
= {
1409 .set_pio_mode
= hpt3xx_set_pio_mode
,
1410 .set_dma_mode
= hpt3xx_set_mode
,
1411 .quirkproc
= hpt3xx_quirkproc
,
1412 .maskproc
= hpt3xx_maskproc
,
1413 .mdma_filter
= hpt3xx_mdma_filter
,
1414 .udma_filter
= hpt3xx_udma_filter
,
1415 .cable_detect
= hpt3xx_cable_detect
,
1418 static const struct ide_dma_ops hpt37x_dma_ops
= {
1419 .dma_host_set
= ide_dma_host_set
,
1420 .dma_setup
= ide_dma_setup
,
1421 .dma_start
= ide_dma_start
,
1422 .dma_end
= hpt374_dma_end
,
1423 .dma_test_irq
= hpt374_dma_test_irq
,
1424 .dma_lost_irq
= ide_dma_lost_irq
,
1425 .dma_timer_expiry
= ide_dma_sff_timer_expiry
,
1426 .dma_sff_read_status
= ide_dma_sff_read_status
,
1429 static const struct ide_dma_ops hpt370_dma_ops
= {
1430 .dma_host_set
= ide_dma_host_set
,
1431 .dma_setup
= ide_dma_setup
,
1432 .dma_start
= hpt370_dma_start
,
1433 .dma_end
= hpt370_dma_end
,
1434 .dma_test_irq
= ide_dma_test_irq
,
1435 .dma_lost_irq
= ide_dma_lost_irq
,
1436 .dma_timer_expiry
= ide_dma_sff_timer_expiry
,
1437 .dma_clear
= hpt370_irq_timeout
,
1438 .dma_sff_read_status
= ide_dma_sff_read_status
,
1441 static const struct ide_dma_ops hpt36x_dma_ops
= {
1442 .dma_host_set
= ide_dma_host_set
,
1443 .dma_setup
= ide_dma_setup
,
1444 .dma_start
= ide_dma_start
,
1445 .dma_end
= ide_dma_end
,
1446 .dma_test_irq
= ide_dma_test_irq
,
1447 .dma_lost_irq
= hpt366_dma_lost_irq
,
1448 .dma_timer_expiry
= ide_dma_sff_timer_expiry
,
1449 .dma_sff_read_status
= ide_dma_sff_read_status
,
1452 static const struct ide_port_info hpt366_chipsets
[] __devinitdata
= {
1455 .init_chipset
= init_chipset_hpt366
,
1456 .init_hwif
= init_hwif_hpt366
,
1457 .init_dma
= init_dma_hpt366
,
1459 * HPT36x chips have one channel per function and have
1460 * both channel enable bits located differently and visible
1461 * to both functions -- really stupid design decision... :-(
1462 * Bit 4 is for the primary channel, bit 5 for the secondary.
1464 .enablebits
= {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1465 .port_ops
= &hpt3xx_port_ops
,
1466 .dma_ops
= &hpt36x_dma_ops
,
1467 .host_flags
= IDE_HFLAGS_HPT3XX
| IDE_HFLAG_SINGLE
,
1468 .pio_mask
= ATA_PIO4
,
1469 .mwdma_mask
= ATA_MWDMA2
,
1473 .init_chipset
= init_chipset_hpt366
,
1474 .init_hwif
= init_hwif_hpt366
,
1475 .init_dma
= init_dma_hpt366
,
1476 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1477 .port_ops
= &hpt3xx_port_ops
,
1478 .dma_ops
= &hpt37x_dma_ops
,
1479 .host_flags
= IDE_HFLAGS_HPT3XX
,
1480 .pio_mask
= ATA_PIO4
,
1481 .mwdma_mask
= ATA_MWDMA2
,
1486 * hpt366_init_one - called when an HPT366 is found
1487 * @dev: the hpt366 device
1488 * @id: the matching pci id
1490 * Called when the PCI registration layer (or the IDE initialization)
1491 * finds a device matching our IDE device tables.
1493 static int __devinit
hpt366_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1495 const struct hpt_info
*info
= NULL
;
1496 struct hpt_info
*dyn_info
;
1497 struct pci_dev
*dev2
= NULL
;
1498 struct ide_port_info d
;
1499 u8 idx
= id
->driver_data
;
1500 u8 rev
= dev
->revision
;
1503 if ((idx
== 0 || idx
== 4) && (PCI_FUNC(dev
->devfn
) & 1))
1511 switch (min_t(u8
, rev
, 6)) {
1512 case 3: info
= &hpt370
; break;
1513 case 4: info
= &hpt370a
; break;
1514 case 5: info
= &hpt372
; break;
1515 case 6: info
= &hpt372n
; break;
1521 info
= (rev
> 1) ? &hpt372n
: &hpt372a
;
1524 info
= (rev
> 1) ? &hpt302n
: &hpt302
;
1528 info
= (rev
> 1) ? &hpt371n
: &hpt371
;
1538 printk(KERN_INFO DRV_NAME
": %s chipset detected\n", info
->chip_name
);
1540 d
= hpt366_chipsets
[min_t(u8
, idx
, 1)];
1542 d
.udma_mask
= info
->udma_mask
;
1544 /* fixup ->dma_ops for HPT370/HPT370A */
1545 if (info
== &hpt370
|| info
== &hpt370a
)
1546 d
.dma_ops
= &hpt370_dma_ops
;
1548 if (info
== &hpt36x
|| info
== &hpt374
)
1549 dev2
= pci_get_slot(dev
->bus
, dev
->devfn
+ 1);
1551 dyn_info
= kzalloc(sizeof(*dyn_info
) * (dev2
? 2 : 1), GFP_KERNEL
);
1552 if (dyn_info
== NULL
) {
1553 printk(KERN_ERR
"%s %s: out of memory!\n",
1554 d
.name
, pci_name(dev
));
1560 * Copy everything from a static "template" structure
1561 * to just allocated per-chip hpt_info structure.
1563 memcpy(dyn_info
, info
, sizeof(*dyn_info
));
1566 memcpy(dyn_info
+ 1, info
, sizeof(*dyn_info
));
1568 if (info
== &hpt374
)
1569 hpt374_init(dev
, dev2
);
1571 if (hpt36x_init(dev
, dev2
))
1572 d
.host_flags
&= ~IDE_HFLAG_NON_BOOTABLE
;
1575 ret
= ide_pci_init_two(dev
, dev2
, &d
, dyn_info
);
1583 ret
= ide_pci_init_one(dev
, &d
, dyn_info
);
1590 static void __devexit
hpt366_remove(struct pci_dev
*dev
)
1592 struct ide_host
*host
= pci_get_drvdata(dev
);
1593 struct ide_info
*info
= host
->host_priv
;
1594 struct pci_dev
*dev2
= host
->dev
[1] ? to_pci_dev(host
->dev
[1]) : NULL
;
1596 ide_pci_remove(dev
);
1601 static const struct pci_device_id hpt366_pci_tbl
[] __devinitconst
= {
1602 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT366
), 0 },
1603 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372
), 1 },
1604 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT302
), 2 },
1605 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT371
), 3 },
1606 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT374
), 4 },
1607 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372N
), 5 },
1610 MODULE_DEVICE_TABLE(pci
, hpt366_pci_tbl
);
1612 static struct pci_driver hpt366_pci_driver
= {
1613 .name
= "HPT366_IDE",
1614 .id_table
= hpt366_pci_tbl
,
1615 .probe
= hpt366_init_one
,
1616 .remove
= __devexit_p(hpt366_remove
),
1617 .suspend
= ide_pci_suspend
,
1618 .resume
= ide_pci_resume
,
1621 static int __init
hpt366_ide_init(void)
1623 return ide_pci_register_driver(&hpt366_pci_driver
);
1626 static void __exit
hpt366_ide_exit(void)
1628 pci_unregister_driver(&hpt366_pci_driver
);
1631 module_init(hpt366_ide_init
);
1632 module_exit(hpt366_ide_exit
);
1634 MODULE_AUTHOR("Andre Hedrick");
1635 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1636 MODULE_LICENSE("GPL");