1 #include <linux/types.h>
2 #include <linux/kernel.h>
4 #include <linux/scatterlist.h>
5 #include <linux/dma-mapping.h>
9 * config_drive_for_dma - attempt to activate IDE DMA
10 * @drive: the drive to place in DMA mode
12 * If the drive supports at least mode 2 DMA or UDMA of any kind
13 * then attempt to place it into DMA mode. Drives that are known to
14 * support DMA but predate the DMA properties or that are known
15 * to have DMA handling bugs are also set up appropriately based
16 * on the good/bad drive lists.
19 int config_drive_for_dma(ide_drive_t
*drive
)
21 ide_hwif_t
*hwif
= drive
->hwif
;
24 if (drive
->media
!= ide_disk
) {
25 if (hwif
->host_flags
& IDE_HFLAG_NO_ATAPI_DMA
)
30 * Enable DMA on any drive that has
31 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
33 if ((id
[ATA_ID_FIELD_VALID
] & 4) &&
34 ((id
[ATA_ID_UDMA_MODES
] >> 8) & 0x7f))
38 * Enable DMA on any drive that has mode2 DMA
39 * (multi or single) enabled
41 if (id
[ATA_ID_FIELD_VALID
] & 2) /* regular DMA */
42 if ((id
[ATA_ID_MWDMA_MODES
] & 0x404) == 0x404 ||
43 (id
[ATA_ID_SWDMA_MODES
] & 0x404) == 0x404)
46 /* Consult the list of known "good" drives */
47 if (ide_dma_good_drive(drive
))
53 u8
ide_dma_sff_read_status(ide_hwif_t
*hwif
)
55 unsigned long addr
= hwif
->dma_base
+ ATA_DMA_STATUS
;
57 if (hwif
->host_flags
& IDE_HFLAG_MMIO
)
58 return readb((void __iomem
*)addr
);
62 EXPORT_SYMBOL_GPL(ide_dma_sff_read_status
);
64 static void ide_dma_sff_write_status(ide_hwif_t
*hwif
, u8 val
)
66 unsigned long addr
= hwif
->dma_base
+ ATA_DMA_STATUS
;
68 if (hwif
->host_flags
& IDE_HFLAG_MMIO
)
69 writeb(val
, (void __iomem
*)addr
);
75 * ide_dma_host_set - Enable/disable DMA on a host
76 * @drive: drive to control
78 * Enable/disable DMA on an IDE controller following generic
79 * bus-mastering IDE controller behaviour.
82 void ide_dma_host_set(ide_drive_t
*drive
, int on
)
84 ide_hwif_t
*hwif
= drive
->hwif
;
85 u8 unit
= drive
->dn
& 1;
86 u8 dma_stat
= hwif
->dma_ops
->dma_sff_read_status(hwif
);
89 dma_stat
|= (1 << (5 + unit
));
91 dma_stat
&= ~(1 << (5 + unit
));
93 ide_dma_sff_write_status(hwif
, dma_stat
);
95 EXPORT_SYMBOL_GPL(ide_dma_host_set
);
98 * ide_build_dmatable - build IDE DMA table
100 * ide_build_dmatable() prepares a dma request. We map the command
101 * to get the pci bus addresses of the buffers and then build up
102 * the PRD table that the IDE layer wants to be fed.
104 * Most chipsets correctly interpret a length of 0x0000 as 64KB,
105 * but at least one (e.g. CS5530) misinterprets it as zero (!).
106 * So we break the 64KB entry into two 32KB entries instead.
108 * Returns the number of built PRD entries if all went okay,
109 * returns 0 otherwise.
111 * May also be invoked from trm290.c
114 int ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
)
116 ide_hwif_t
*hwif
= drive
->hwif
;
117 __le32
*table
= (__le32
*)hwif
->dmatable_cpu
;
118 unsigned int count
= 0;
120 struct scatterlist
*sg
;
121 u8 is_trm290
= !!(hwif
->host_flags
& IDE_HFLAG_TRM290
);
123 hwif
->sg_nents
= ide_build_sglist(drive
, rq
);
124 if (hwif
->sg_nents
== 0)
127 for_each_sg(hwif
->sg_table
, sg
, hwif
->sg_nents
, i
) {
128 u32 cur_addr
, cur_len
, xcount
, bcount
;
130 cur_addr
= sg_dma_address(sg
);
131 cur_len
= sg_dma_len(sg
);
134 * Fill in the dma table, without crossing any 64kB boundaries.
135 * Most hardware requires 16-bit alignment of all blocks,
136 * but the trm290 requires 32-bit alignment.
140 if (count
++ >= PRD_ENTRIES
)
141 goto use_pio_instead
;
143 bcount
= 0x10000 - (cur_addr
& 0xffff);
144 if (bcount
> cur_len
)
146 *table
++ = cpu_to_le32(cur_addr
);
147 xcount
= bcount
& 0xffff;
149 xcount
= ((xcount
>> 2) - 1) << 16;
150 else if (xcount
== 0x0000) {
151 if (count
++ >= PRD_ENTRIES
)
152 goto use_pio_instead
;
153 *table
++ = cpu_to_le32(0x8000);
154 *table
++ = cpu_to_le32(cur_addr
+ 0x8000);
157 *table
++ = cpu_to_le32(xcount
);
165 *--table
|= cpu_to_le32(0x80000000);
170 printk(KERN_ERR
"%s: %s\n", drive
->name
,
171 count
? "DMA table too small" : "empty DMA table?");
173 ide_destroy_dmatable(drive
);
175 return 0; /* revert to PIO for this request */
177 EXPORT_SYMBOL_GPL(ide_build_dmatable
);
180 * ide_dma_setup - begin a DMA phase
181 * @drive: target device
183 * Build an IDE DMA PRD (IDE speak for scatter gather table)
184 * and then set up the DMA transfer registers for a device
185 * that follows generic IDE PCI DMA behaviour. Controllers can
186 * override this function if they need to
188 * Returns 0 on success. If a PIO fallback is required then 1
192 int ide_dma_setup(ide_drive_t
*drive
)
194 ide_hwif_t
*hwif
= drive
->hwif
;
195 struct request
*rq
= hwif
->rq
;
196 unsigned int reading
= rq_data_dir(rq
) ? 0 : ATA_DMA_WR
;
197 u8 mmio
= (hwif
->host_flags
& IDE_HFLAG_MMIO
) ? 1 : 0;
200 /* fall back to pio! */
201 if (!ide_build_dmatable(drive
, rq
)) {
202 ide_map_sg(drive
, rq
);
208 writel(hwif
->dmatable_dma
,
209 (void __iomem
*)(hwif
->dma_base
+ ATA_DMA_TABLE_OFS
));
211 outl(hwif
->dmatable_dma
, hwif
->dma_base
+ ATA_DMA_TABLE_OFS
);
215 writeb(reading
, (void __iomem
*)(hwif
->dma_base
+ ATA_DMA_CMD
));
217 outb(reading
, hwif
->dma_base
+ ATA_DMA_CMD
);
219 /* read DMA status for INTR & ERROR flags */
220 dma_stat
= hwif
->dma_ops
->dma_sff_read_status(hwif
);
222 /* clear INTR & ERROR flags */
223 ide_dma_sff_write_status(hwif
, dma_stat
| ATA_DMA_ERR
| ATA_DMA_INTR
);
225 drive
->waiting_for_dma
= 1;
228 EXPORT_SYMBOL_GPL(ide_dma_setup
);
231 * dma_timer_expiry - handle a DMA timeout
232 * @drive: Drive that timed out
234 * An IDE DMA transfer timed out. In the event of an error we ask
235 * the driver to resolve the problem, if a DMA transfer is still
236 * in progress we continue to wait (arguably we need to add a
237 * secondary 'I don't care what the drive thinks' timeout here)
238 * Finally if we have an interrupt we let it complete the I/O.
239 * But only one time - we clear expiry and if it's still not
240 * completed after WAIT_CMD, we error and retry in PIO.
241 * This can occur if an interrupt is lost or due to hang or bugs.
244 static int dma_timer_expiry(ide_drive_t
*drive
)
246 ide_hwif_t
*hwif
= drive
->hwif
;
247 u8 dma_stat
= hwif
->dma_ops
->dma_sff_read_status(hwif
);
249 printk(KERN_WARNING
"%s: %s: DMA status (0x%02x)\n",
250 drive
->name
, __func__
, dma_stat
);
252 if ((dma_stat
& 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
255 hwif
->expiry
= NULL
; /* one free ride for now */
257 if (dma_stat
& ATA_DMA_ERR
) /* ERROR */
260 if (dma_stat
& ATA_DMA_ACTIVE
) /* DMAing */
263 if (dma_stat
& ATA_DMA_INTR
) /* Got an Interrupt */
266 return 0; /* Status is unknown -- reset the bus */
269 void ide_dma_exec_cmd(ide_drive_t
*drive
, u8 command
)
271 /* issue cmd to drive */
272 ide_execute_command(drive
, command
, &ide_dma_intr
, 2 * WAIT_CMD
,
275 EXPORT_SYMBOL_GPL(ide_dma_exec_cmd
);
277 void ide_dma_start(ide_drive_t
*drive
)
279 ide_hwif_t
*hwif
= drive
->hwif
;
282 /* Note that this is done *after* the cmd has
283 * been issued to the drive, as per the BM-IDE spec.
284 * The Promise Ultra33 doesn't work correctly when
285 * we do this part before issuing the drive cmd.
287 if (hwif
->host_flags
& IDE_HFLAG_MMIO
) {
288 dma_cmd
= readb((void __iomem
*)(hwif
->dma_base
+ ATA_DMA_CMD
));
289 writeb(dma_cmd
| ATA_DMA_START
,
290 (void __iomem
*)(hwif
->dma_base
+ ATA_DMA_CMD
));
292 dma_cmd
= inb(hwif
->dma_base
+ ATA_DMA_CMD
);
293 outb(dma_cmd
| ATA_DMA_START
, hwif
->dma_base
+ ATA_DMA_CMD
);
298 EXPORT_SYMBOL_GPL(ide_dma_start
);
300 /* returns 1 on error, 0 otherwise */
301 int ide_dma_end(ide_drive_t
*drive
)
303 ide_hwif_t
*hwif
= drive
->hwif
;
304 u8 dma_stat
= 0, dma_cmd
= 0, mask
;
306 drive
->waiting_for_dma
= 0;
309 if (hwif
->host_flags
& IDE_HFLAG_MMIO
) {
310 dma_cmd
= readb((void __iomem
*)(hwif
->dma_base
+ ATA_DMA_CMD
));
311 writeb(dma_cmd
& ~ATA_DMA_START
,
312 (void __iomem
*)(hwif
->dma_base
+ ATA_DMA_CMD
));
314 dma_cmd
= inb(hwif
->dma_base
+ ATA_DMA_CMD
);
315 outb(dma_cmd
& ~ATA_DMA_START
, hwif
->dma_base
+ ATA_DMA_CMD
);
319 dma_stat
= hwif
->dma_ops
->dma_sff_read_status(hwif
);
321 /* clear INTR & ERROR bits */
322 ide_dma_sff_write_status(hwif
, dma_stat
| ATA_DMA_ERR
| ATA_DMA_INTR
);
324 /* purge DMA mappings */
325 ide_destroy_dmatable(drive
);
328 /* verify good DMA status */
329 mask
= ATA_DMA_ACTIVE
| ATA_DMA_ERR
| ATA_DMA_INTR
;
330 if ((dma_stat
& mask
) != ATA_DMA_INTR
)
331 return 0x10 | dma_stat
;
334 EXPORT_SYMBOL_GPL(ide_dma_end
);
336 /* returns 1 if dma irq issued, 0 otherwise */
337 int ide_dma_test_irq(ide_drive_t
*drive
)
339 ide_hwif_t
*hwif
= drive
->hwif
;
340 u8 dma_stat
= hwif
->dma_ops
->dma_sff_read_status(hwif
);
342 return (dma_stat
& ATA_DMA_INTR
) ? 1 : 0;
344 EXPORT_SYMBOL_GPL(ide_dma_test_irq
);
346 const struct ide_dma_ops sff_dma_ops
= {
347 .dma_host_set
= ide_dma_host_set
,
348 .dma_setup
= ide_dma_setup
,
349 .dma_exec_cmd
= ide_dma_exec_cmd
,
350 .dma_start
= ide_dma_start
,
351 .dma_end
= ide_dma_end
,
352 .dma_test_irq
= ide_dma_test_irq
,
353 .dma_timeout
= ide_dma_timeout
,
354 .dma_lost_irq
= ide_dma_lost_irq
,
355 .dma_sff_read_status
= ide_dma_sff_read_status
,
357 EXPORT_SYMBOL_GPL(sff_dma_ops
);
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