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[deliverable/linux.git] / drivers / ide / mips / au1xxx-ide.c
1 /*
2 * BRIEF MODULE DESCRIPTION
3 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
4 *
5 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
14 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
15 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
21 * POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along with
24 * this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
28 * Interface and Linux Device Driver" Application Note.
29 */
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <linux/scatterlist.h>
38
39 #include <asm/mach-au1x00/au1xxx.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41 #include <asm/mach-au1x00/au1xxx_ide.h>
42
43 #define DRV_NAME "au1200-ide"
44 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
45
46 /* enable the burstmode in the dbdma */
47 #define IDE_AU1XXX_BURSTMODE 1
48
49 static _auide_hwif auide_hwif;
50
51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
52
53 void auide_insw(unsigned long port, void *addr, u32 count)
54 {
55 _auide_hwif *ahwif = &auide_hwif;
56 chan_tab_t *ctp;
57 au1x_ddma_desc_t *dp;
58
59 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
60 DDMA_FLAGS_NOIE)) {
61 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
62 return;
63 }
64 ctp = *((chan_tab_t **)ahwif->rx_chan);
65 dp = ctp->cur_ptr;
66 while (dp->dscr_cmd0 & DSCR_CMD0_V)
67 ;
68 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
69 }
70
71 void auide_outsw(unsigned long port, void *addr, u32 count)
72 {
73 _auide_hwif *ahwif = &auide_hwif;
74 chan_tab_t *ctp;
75 au1x_ddma_desc_t *dp;
76
77 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
78 count << 1, DDMA_FLAGS_NOIE)) {
79 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
80 return;
81 }
82 ctp = *((chan_tab_t **)ahwif->tx_chan);
83 dp = ctp->cur_ptr;
84 while (dp->dscr_cmd0 & DSCR_CMD0_V)
85 ;
86 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
87 }
88
89 static void au1xxx_input_data(ide_drive_t *drive, struct request *rq,
90 void *buf, unsigned int len)
91 {
92 auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
93 }
94
95 static void au1xxx_output_data(ide_drive_t *drive, struct request *rq,
96 void *buf, unsigned int len)
97 {
98 auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
99 }
100 #endif
101
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
105
106 /* set pio mode! */
107 switch(pio) {
108 case 0:
109 mem_sttime = SBC_IDE_TIMING(PIO0);
110
111 /* set configuration for RCS2# */
112 mem_stcfg |= TS_MASK;
113 mem_stcfg &= ~TCSOE_MASK;
114 mem_stcfg &= ~TOECS_MASK;
115 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
116 break;
117
118 case 1:
119 mem_sttime = SBC_IDE_TIMING(PIO1);
120
121 /* set configuration for RCS2# */
122 mem_stcfg |= TS_MASK;
123 mem_stcfg &= ~TCSOE_MASK;
124 mem_stcfg &= ~TOECS_MASK;
125 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
126 break;
127
128 case 2:
129 mem_sttime = SBC_IDE_TIMING(PIO2);
130
131 /* set configuration for RCS2# */
132 mem_stcfg &= ~TS_MASK;
133 mem_stcfg &= ~TCSOE_MASK;
134 mem_stcfg &= ~TOECS_MASK;
135 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
136 break;
137
138 case 3:
139 mem_sttime = SBC_IDE_TIMING(PIO3);
140
141 /* set configuration for RCS2# */
142 mem_stcfg &= ~TS_MASK;
143 mem_stcfg &= ~TCSOE_MASK;
144 mem_stcfg &= ~TOECS_MASK;
145 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
146
147 break;
148
149 case 4:
150 mem_sttime = SBC_IDE_TIMING(PIO4);
151
152 /* set configuration for RCS2# */
153 mem_stcfg &= ~TS_MASK;
154 mem_stcfg &= ~TCSOE_MASK;
155 mem_stcfg &= ~TOECS_MASK;
156 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
157 break;
158 }
159
160 au_writel(mem_sttime,MEM_STTIME2);
161 au_writel(mem_stcfg,MEM_STCFG2);
162 }
163
164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
165 {
166 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
167
168 switch(speed) {
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170 case XFER_MW_DMA_2:
171 mem_sttime = SBC_IDE_TIMING(MDMA2);
172
173 /* set configuration for RCS2# */
174 mem_stcfg &= ~TS_MASK;
175 mem_stcfg &= ~TCSOE_MASK;
176 mem_stcfg &= ~TOECS_MASK;
177 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
178
179 break;
180 case XFER_MW_DMA_1:
181 mem_sttime = SBC_IDE_TIMING(MDMA1);
182
183 /* set configuration for RCS2# */
184 mem_stcfg &= ~TS_MASK;
185 mem_stcfg &= ~TCSOE_MASK;
186 mem_stcfg &= ~TOECS_MASK;
187 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
188
189 break;
190 case XFER_MW_DMA_0:
191 mem_sttime = SBC_IDE_TIMING(MDMA0);
192
193 /* set configuration for RCS2# */
194 mem_stcfg |= TS_MASK;
195 mem_stcfg &= ~TCSOE_MASK;
196 mem_stcfg &= ~TOECS_MASK;
197 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
198
199 break;
200 #endif
201 }
202
203 au_writel(mem_sttime,MEM_STTIME2);
204 au_writel(mem_stcfg,MEM_STCFG2);
205 }
206
207 /*
208 * Multi-Word DMA + DbDMA functions
209 */
210
211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
212 static int auide_build_dmatable(ide_drive_t *drive)
213 {
214 int i, iswrite, count = 0;
215 ide_hwif_t *hwif = HWIF(drive);
216 struct request *rq = HWGROUP(drive)->rq;
217 _auide_hwif *ahwif = &auide_hwif;
218 struct scatterlist *sg;
219
220 iswrite = (rq_data_dir(rq) == WRITE);
221 /* Save for interrupt context */
222 ahwif->drive = drive;
223
224 hwif->sg_nents = i = ide_build_sglist(drive, rq);
225
226 if (!i)
227 return 0;
228
229 /* fill the descriptors */
230 sg = hwif->sg_table;
231 while (i && sg_dma_len(sg)) {
232 u32 cur_addr;
233 u32 cur_len;
234
235 cur_addr = sg_dma_address(sg);
236 cur_len = sg_dma_len(sg);
237
238 while (cur_len) {
239 u32 flags = DDMA_FLAGS_NOIE;
240 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
241
242 if (++count >= PRD_ENTRIES) {
243 printk(KERN_WARNING "%s: DMA table too small\n",
244 drive->name);
245 goto use_pio_instead;
246 }
247
248 /* Lets enable intr for the last descriptor only */
249 if (1==i)
250 flags = DDMA_FLAGS_IE;
251 else
252 flags = DDMA_FLAGS_NOIE;
253
254 if (iswrite) {
255 if(!put_source_flags(ahwif->tx_chan,
256 (void*) sg_virt(sg),
257 tc, flags)) {
258 printk(KERN_ERR "%s failed %d\n",
259 __func__, __LINE__);
260 }
261 } else
262 {
263 if(!put_dest_flags(ahwif->rx_chan,
264 (void*) sg_virt(sg),
265 tc, flags)) {
266 printk(KERN_ERR "%s failed %d\n",
267 __func__, __LINE__);
268 }
269 }
270
271 cur_addr += tc;
272 cur_len -= tc;
273 }
274 sg = sg_next(sg);
275 i--;
276 }
277
278 if (count)
279 return 1;
280
281 use_pio_instead:
282 ide_destroy_dmatable(drive);
283
284 return 0; /* revert to PIO for this request */
285 }
286
287 static int auide_dma_end(ide_drive_t *drive)
288 {
289 ide_hwif_t *hwif = HWIF(drive);
290
291 if (hwif->sg_nents) {
292 ide_destroy_dmatable(drive);
293 hwif->sg_nents = 0;
294 }
295
296 return 0;
297 }
298
299 static void auide_dma_start(ide_drive_t *drive )
300 {
301 }
302
303
304 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
305 {
306 /* issue cmd to drive */
307 ide_execute_command(drive, command, &ide_dma_intr,
308 (2*WAIT_CMD), NULL);
309 }
310
311 static int auide_dma_setup(ide_drive_t *drive)
312 {
313 struct request *rq = HWGROUP(drive)->rq;
314
315 if (!auide_build_dmatable(drive)) {
316 ide_map_sg(drive, rq);
317 return 1;
318 }
319
320 drive->waiting_for_dma = 1;
321 return 0;
322 }
323
324 static int auide_dma_test_irq(ide_drive_t *drive)
325 {
326 /* If dbdma didn't execute the STOP command yet, the
327 * active bit is still set
328 */
329 drive->waiting_for_dma++;
330 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
331 printk(KERN_WARNING "%s: timeout waiting for ddma to \
332 complete\n", drive->name);
333 return 1;
334 }
335 udelay(10);
336 return 0;
337 }
338
339 static void auide_dma_host_set(ide_drive_t *drive, int on)
340 {
341 }
342
343 static void auide_dma_lost_irq(ide_drive_t *drive)
344 {
345 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
346 }
347
348 static void auide_ddma_tx_callback(int irq, void *param)
349 {
350 _auide_hwif *ahwif = (_auide_hwif*)param;
351 ahwif->drive->waiting_for_dma = 0;
352 }
353
354 static void auide_ddma_rx_callback(int irq, void *param)
355 {
356 _auide_hwif *ahwif = (_auide_hwif*)param;
357 ahwif->drive->waiting_for_dma = 0;
358 }
359
360 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
361
362 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
363 {
364 dev->dev_id = dev_id;
365 dev->dev_physaddr = (u32)IDE_PHYS_ADDR;
366 dev->dev_intlevel = 0;
367 dev->dev_intpolarity = 0;
368 dev->dev_tsize = tsize;
369 dev->dev_devwidth = devwidth;
370 dev->dev_flags = flags;
371 }
372
373 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
374 static void auide_dma_timeout(ide_drive_t *drive)
375 {
376 ide_hwif_t *hwif = HWIF(drive);
377
378 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
379
380 if (auide_dma_test_irq(drive))
381 return;
382
383 auide_dma_end(drive);
384 }
385
386 static const struct ide_dma_ops au1xxx_dma_ops = {
387 .dma_host_set = auide_dma_host_set,
388 .dma_setup = auide_dma_setup,
389 .dma_exec_cmd = auide_dma_exec_cmd,
390 .dma_start = auide_dma_start,
391 .dma_end = auide_dma_end,
392 .dma_test_irq = auide_dma_test_irq,
393 .dma_lost_irq = auide_dma_lost_irq,
394 .dma_timeout = auide_dma_timeout,
395 };
396
397 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
398 {
399 _auide_hwif *auide = &auide_hwif;
400 dbdev_tab_t source_dev_tab, target_dev_tab;
401 u32 dev_id, tsize, devwidth, flags;
402
403 dev_id = IDE_DDMA_REQ;
404
405 tsize = 8; /* 1 */
406 devwidth = 32; /* 16 */
407
408 #ifdef IDE_AU1XXX_BURSTMODE
409 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
410 #else
411 flags = DEV_FLAGS_SYNC;
412 #endif
413
414 /* setup dev_tab for tx channel */
415 auide_init_dbdma_dev( &source_dev_tab,
416 dev_id,
417 tsize, devwidth, DEV_FLAGS_OUT | flags);
418 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
419
420 auide_init_dbdma_dev( &source_dev_tab,
421 dev_id,
422 tsize, devwidth, DEV_FLAGS_IN | flags);
423 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
424
425 /* We also need to add a target device for the DMA */
426 auide_init_dbdma_dev( &target_dev_tab,
427 (u32)DSCR_CMD0_ALWAYS,
428 tsize, devwidth, DEV_FLAGS_ANYUSE);
429 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
430
431 /* Get a channel for TX */
432 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
433 auide->tx_dev_id,
434 auide_ddma_tx_callback,
435 (void*)auide);
436
437 /* Get a channel for RX */
438 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
439 auide->target_dev_id,
440 auide_ddma_rx_callback,
441 (void*)auide);
442
443 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
444 NUM_DESCRIPTORS);
445 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
446 NUM_DESCRIPTORS);
447
448 hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
449 PRD_ENTRIES * PRD_BYTES, /* 1 Page */
450 &hwif->dmatable_dma, GFP_KERNEL);
451
452 au1xxx_dbdma_start( auide->tx_chan );
453 au1xxx_dbdma_start( auide->rx_chan );
454
455 return 0;
456 }
457 #else
458 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
459 {
460 _auide_hwif *auide = &auide_hwif;
461 dbdev_tab_t source_dev_tab;
462 int flags;
463
464 #ifdef IDE_AU1XXX_BURSTMODE
465 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
466 #else
467 flags = DEV_FLAGS_SYNC;
468 #endif
469
470 /* setup dev_tab for tx channel */
471 auide_init_dbdma_dev( &source_dev_tab,
472 (u32)DSCR_CMD0_ALWAYS,
473 8, 32, DEV_FLAGS_OUT | flags);
474 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
475
476 auide_init_dbdma_dev( &source_dev_tab,
477 (u32)DSCR_CMD0_ALWAYS,
478 8, 32, DEV_FLAGS_IN | flags);
479 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
480
481 /* Get a channel for TX */
482 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
483 auide->tx_dev_id,
484 NULL,
485 (void*)auide);
486
487 /* Get a channel for RX */
488 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
489 DSCR_CMD0_ALWAYS,
490 NULL,
491 (void*)auide);
492
493 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
494 NUM_DESCRIPTORS);
495 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
496 NUM_DESCRIPTORS);
497
498 au1xxx_dbdma_start( auide->tx_chan );
499 au1xxx_dbdma_start( auide->rx_chan );
500
501 return 0;
502 }
503 #endif
504
505 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
506 {
507 int i;
508 unsigned long *ata_regs = hw->io_ports_array;
509
510 /* FIXME? */
511 for (i = 0; i < 8; i++)
512 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
513
514 /* set the Alternative Status register */
515 *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
516 }
517
518 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
519 static const struct ide_tp_ops au1xxx_tp_ops = {
520 .exec_command = ide_exec_command,
521 .read_status = ide_read_status,
522 .read_altstatus = ide_read_altstatus,
523 .read_sff_dma_status = ide_read_sff_dma_status,
524
525 .set_irq = ide_set_irq,
526
527 .tf_load = ide_tf_load,
528 .tf_read = ide_tf_read,
529
530 .input_data = au1xxx_input_data,
531 .output_data = au1xxx_output_data,
532 };
533 #endif
534
535 static const struct ide_port_ops au1xxx_port_ops = {
536 .set_pio_mode = au1xxx_set_pio_mode,
537 .set_dma_mode = auide_set_dma_mode,
538 };
539
540 static const struct ide_port_info au1xxx_port_info = {
541 .init_dma = auide_ddma_init,
542 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
543 .tp_ops = &au1xxx_tp_ops,
544 #endif
545 .port_ops = &au1xxx_port_ops,
546 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
547 .dma_ops = &au1xxx_dma_ops,
548 #endif
549 .host_flags = IDE_HFLAG_POST_SET_MODE |
550 IDE_HFLAG_NO_IO_32BIT |
551 IDE_HFLAG_UNMASK_IRQS,
552 .pio_mask = ATA_PIO4,
553 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
554 .mwdma_mask = ATA_MWDMA2,
555 #endif
556 };
557
558 static int au_ide_probe(struct device *dev)
559 {
560 struct platform_device *pdev = to_platform_device(dev);
561 _auide_hwif *ahwif = &auide_hwif;
562 struct resource *res;
563 struct ide_host *host;
564 int ret = 0;
565 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
566
567 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
568 char *mode = "MWDMA2";
569 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
570 char *mode = "PIO+DDMA(offload)";
571 #endif
572
573 memset(&auide_hwif, 0, sizeof(_auide_hwif));
574 ahwif->irq = platform_get_irq(pdev, 0);
575
576 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
577
578 if (res == NULL) {
579 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
580 ret = -ENODEV;
581 goto out;
582 }
583 if (ahwif->irq < 0) {
584 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
585 ret = -ENODEV;
586 goto out;
587 }
588
589 if (!request_mem_region(res->start, res->end - res->start + 1,
590 pdev->name)) {
591 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
592 ret = -EBUSY;
593 goto out;
594 }
595
596 ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
597 if (ahwif->regbase == 0) {
598 ret = -ENOMEM;
599 goto out;
600 }
601
602 memset(&hw, 0, sizeof(hw));
603 auide_setup_ports(&hw, ahwif);
604 hw.irq = ahwif->irq;
605 hw.dev = dev;
606 hw.chipset = ide_au1xxx;
607
608 ret = ide_host_add(&au1xxx_port_info, hws, &host);
609 if (ret)
610 goto out;
611
612 auide_hwif.hwif = host->ports[0];
613
614 dev_set_drvdata(dev, host);
615
616 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
617
618 out:
619 return ret;
620 }
621
622 static int au_ide_remove(struct device *dev)
623 {
624 struct platform_device *pdev = to_platform_device(dev);
625 struct resource *res;
626 struct ide_host *host = dev_get_drvdata(dev);
627 _auide_hwif *ahwif = &auide_hwif;
628
629 ide_host_remove(host);
630
631 iounmap((void *)ahwif->regbase);
632
633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
634 release_mem_region(res->start, res->end - res->start + 1);
635
636 return 0;
637 }
638
639 static struct device_driver au1200_ide_driver = {
640 .name = "au1200-ide",
641 .bus = &platform_bus_type,
642 .probe = au_ide_probe,
643 .remove = au_ide_remove,
644 };
645
646 static int __init au_ide_init(void)
647 {
648 return driver_register(&au1200_ide_driver);
649 }
650
651 static void __exit au_ide_exit(void)
652 {
653 driver_unregister(&au1200_ide_driver);
654 }
655
656 MODULE_LICENSE("GPL");
657 MODULE_DESCRIPTION("AU1200 IDE driver");
658
659 module_init(au_ide_init);
660 module_exit(au_ide_exit);
Linux kernel - Deliverables
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