drivers/ide/pci/aec62xx.c

   1 /*
   2  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
   3  * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/types.h>
   9 #include <linux/pci.h>
  10 #include <linux/hdreg.h>
  11 #include <linux/ide.h>
  12 #include <linux/init.h>
  13
  14 #include <asm/io.h>
  15
  16 struct chipset_bus_clock_list_entry {
  17         u8 xfer_speed;
  18         u8 chipset_settings;
  19         u8 ultra_settings;
  20 };
  21
  22 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
  23         {       XFER_UDMA_6,    0x31,   0x07    },
  24         {       XFER_UDMA_5,    0x31,   0x06    },
  25         {       XFER_UDMA_4,    0x31,   0x05    },
  26         {       XFER_UDMA_3,    0x31,   0x04    },
  27         {       XFER_UDMA_2,    0x31,   0x03    },
  28         {       XFER_UDMA_1,    0x31,   0x02    },
  29         {       XFER_UDMA_0,    0x31,   0x01    },
  30
  31         {       XFER_MW_DMA_2,  0x31,   0x00    },
  32         {       XFER_MW_DMA_1,  0x31,   0x00    },
  33         {       XFER_MW_DMA_0,  0x0a,   0x00    },
  34         {       XFER_PIO_4,     0x31,   0x00    },
  35         {       XFER_PIO_3,     0x33,   0x00    },
  36         {       XFER_PIO_2,     0x08,   0x00    },
  37         {       XFER_PIO_1,     0x0a,   0x00    },
  38         {       XFER_PIO_0,     0x00,   0x00    },
  39         {       0,              0x00,   0x00    }
  40 };
  41
  42 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
  43         {       XFER_UDMA_6,    0x41,   0x06    },
  44         {       XFER_UDMA_5,    0x41,   0x05    },
  45         {       XFER_UDMA_4,    0x41,   0x04    },
  46         {       XFER_UDMA_3,    0x41,   0x03    },
  47         {       XFER_UDMA_2,    0x41,   0x02    },
  48         {       XFER_UDMA_1,    0x41,   0x01    },
  49         {       XFER_UDMA_0,    0x41,   0x01    },
  50
  51         {       XFER_MW_DMA_2,  0x41,   0x00    },
  52         {       XFER_MW_DMA_1,  0x42,   0x00    },
  53         {       XFER_MW_DMA_0,  0x7a,   0x00    },
  54         {       XFER_PIO_4,     0x41,   0x00    },
  55         {       XFER_PIO_3,     0x43,   0x00    },
  56         {       XFER_PIO_2,     0x78,   0x00    },
  57         {       XFER_PIO_1,     0x7a,   0x00    },
  58         {       XFER_PIO_0,     0x70,   0x00    },
  59         {       0,              0x00,   0x00    }
  60 };
  61
  62 #define BUSCLOCK(D)     \
  63         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
  64
  65
  66 /*
  67  * TO DO: active tuning and correction of cards without a bios.
  68  */
  69 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  70 {
  71         for ( ; chipset_table->xfer_speed ; chipset_table++)
  72                 if (chipset_table->xfer_speed == speed) {
  73                         return chipset_table->chipset_settings;
  74                 }
  75         return chipset_table->chipset_settings;
  76 }
  77
  78 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  79 {
  80         for ( ; chipset_table->xfer_speed ; chipset_table++)
  81                 if (chipset_table->xfer_speed == speed) {
  82                         return chipset_table->ultra_settings;
  83                 }
  84         return chipset_table->ultra_settings;
  85 }
  86
  87 static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
  88 {
  89         ide_hwif_t *hwif        = HWIF(drive);
  90         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  91         u16 d_conf              = 0;
  92         u8 ultra = 0, ultra_conf = 0;
  93         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
  94         unsigned long flags;
  95
  96         local_irq_save(flags);
  97         /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
  98         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
  99         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
 100         d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
 101         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 102
 103         tmp1 = 0x00;
 104         tmp2 = 0x00;
 105         pci_read_config_byte(dev, 0x54, &ultra);
 106         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
 107         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 108         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
 109         pci_write_config_byte(dev, 0x54, tmp2);
 110         local_irq_restore(flags);
 111 }
 112
 113 static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
 114 {
 115         ide_hwif_t *hwif        = HWIF(drive);
 116         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 117         u8 unit         = (drive->select.b.unit & 0x01);
 118         u8 tmp1 = 0, tmp2 = 0;
 119         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
 120         unsigned long flags;
 121
 122         local_irq_save(flags);
 123         /* high 4-bits: Active, low 4-bits: Recovery */
 124         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
 125         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
 126         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
 127
 128         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
 129         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
 130         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 131         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
 132         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
 133         local_irq_restore(flags);
 134 }
 135
 136 static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
 137 {
 138         drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0);
 139 }
 140
 141 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
 142 {
 143         int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
 144
 145         if (bus_speed <= 33)
 146                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
 147         else
 148                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
 149
 150         /* These are necessary to get AEC6280 Macintosh cards to work */
 151         if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
 152             (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
 153                 u8 reg49h = 0, reg4ah = 0;
 154                 /* Clear reset and test bits.  */
 155                 pci_read_config_byte(dev, 0x49, &reg49h);
 156                 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
 157                 /* Enable chip interrupt output.  */
 158                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 159                 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
 160                 /* Enable burst mode. */
 161                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 162                 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
 163         }
 164
 165         return dev->irq;
 166 }
 167
 168 static u8 __devinit atp86x_cable_detect(ide_hwif_t *hwif)
 169 {
 170         struct pci_dev *dev = to_pci_dev(hwif->dev);
 171         u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
 172
 173         pci_read_config_byte(dev, 0x49, &ata66);
 174
 175         return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 176 }
 177
 178 static const struct ide_port_ops atp850_port_ops = {
 179         .set_pio_mode           = aec_set_pio_mode,
 180         .set_dma_mode           = aec6210_set_mode,
 181 };
 182
 183 static const struct ide_port_ops atp86x_port_ops = {
 184         .set_pio_mode           = aec_set_pio_mode,
 185         .set_dma_mode           = aec6260_set_mode,
 186         .cable_detect           = atp86x_cable_detect,
 187 };
 188
 189 static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
 190         {       /* 0 */
 191                 .name           = "AEC6210",
 192                 .init_chipset   = init_chipset_aec62xx,
 193                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 194                 .port_ops       = &atp850_port_ops,
 195                 .host_flags     = IDE_HFLAG_SERIALIZE |
 196                                   IDE_HFLAG_NO_ATAPI_DMA |
 197                                   IDE_HFLAG_NO_DSC |
 198                                   IDE_HFLAG_ABUSE_SET_DMA_MODE |
 199                                   IDE_HFLAG_OFF_BOARD,
 200                 .pio_mask       = ATA_PIO4,
 201                 .mwdma_mask     = ATA_MWDMA2,
 202                 .udma_mask      = ATA_UDMA2,
 203         },{     /* 1 */
 204                 .name           = "AEC6260",
 205                 .init_chipset   = init_chipset_aec62xx,
 206                 .port_ops       = &atp86x_port_ops,
 207                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
 208                                   IDE_HFLAG_ABUSE_SET_DMA_MODE |
 209                                   IDE_HFLAG_OFF_BOARD,
 210                 .pio_mask       = ATA_PIO4,
 211                 .mwdma_mask     = ATA_MWDMA2,
 212                 .udma_mask      = ATA_UDMA4,
 213         },{     /* 2 */
 214                 .name           = "AEC6260R",
 215                 .init_chipset   = init_chipset_aec62xx,
 216                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 217                 .port_ops       = &atp86x_port_ops,
 218                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
 219                                   IDE_HFLAG_ABUSE_SET_DMA_MODE |
 220                                   IDE_HFLAG_NON_BOOTABLE,
 221                 .pio_mask       = ATA_PIO4,
 222                 .mwdma_mask     = ATA_MWDMA2,
 223                 .udma_mask      = ATA_UDMA4,
 224         },{     /* 3 */
 225                 .name           = "AEC6280",
 226                 .init_chipset   = init_chipset_aec62xx,
 227                 .port_ops       = &atp86x_port_ops,
 228                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
 229                                   IDE_HFLAG_ABUSE_SET_DMA_MODE |
 230                                   IDE_HFLAG_OFF_BOARD,
 231                 .pio_mask       = ATA_PIO4,
 232                 .mwdma_mask     = ATA_MWDMA2,
 233                 .udma_mask      = ATA_UDMA5,
 234         },{     /* 4 */
 235                 .name           = "AEC6280R",
 236                 .init_chipset   = init_chipset_aec62xx,
 237                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 238                 .port_ops       = &atp86x_port_ops,
 239                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
 240                                   IDE_HFLAG_ABUSE_SET_DMA_MODE |
 241                                   IDE_HFLAG_OFF_BOARD,
 242                 .pio_mask       = ATA_PIO4,
 243                 .mwdma_mask     = ATA_MWDMA2,
 244                 .udma_mask      = ATA_UDMA5,
 245         }
 246 };
 247
 248 /**
 249  *      aec62xx_init_one        -       called when a AEC is found
 250  *      @dev: the aec62xx device
 251  *      @id: the matching pci id
 252  *
 253  *      Called when the PCI registration layer (or the IDE initialization)
 254  *      finds a device matching our IDE device tables.
 255  *
 256  *      NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 257  *      chips, pass a local copy of 'struct ide_port_info' down the call chain.
 258  */
 259
 260 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 261 {
 262         struct ide_port_info d;
 263         u8 idx = id->driver_data;
 264         int err;
 265
 266         err = pci_enable_device(dev);
 267         if (err)
 268                 return err;
 269
 270         d = aec62xx_chipsets[idx];
 271
 272         if (idx == 3 || idx == 4) {
 273                 unsigned long dma_base = pci_resource_start(dev, 4);
 274
 275                 if (inb(dma_base + 2) & 0x10) {
 276                         d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
 277                         d.udma_mask = ATA_UDMA6;
 278                 }
 279         }
 280
 281         err = ide_setup_pci_device(dev, &d);
 282         if (err)
 283                 pci_disable_device(dev);
 284
 285         return err;
 286 }
 287
 288 static const struct pci_device_id aec62xx_pci_tbl[] = {
 289         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
 290         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
 291         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
 292         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
 293         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
 294         { 0, },
 295 };
 296 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
 297
 298 static struct pci_driver driver = {
 299         .name           = "AEC62xx_IDE",
 300         .id_table       = aec62xx_pci_tbl,
 301         .probe          = aec62xx_init_one,
 302 };
 303
 304 static int __init aec62xx_ide_init(void)
 305 {
 306         return ide_pci_register_driver(&driver);
 307 }
 308
 309 module_init(aec62xx_ide_init);
 310
 311 MODULE_AUTHOR("Andre Hedrick");
 312 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
 313 MODULE_LICENSE("GPL");