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Merge git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6
[deliverable/linux.git] / drivers / ide / pci / amd74xx.c
1 /*
2 * Version 2.23
3 *
4 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
5 * IDE driver for Linux.
6 *
7 * Copyright (c) 2000-2002 Vojtech Pavlik
8 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
9 *
10 * Based on the work of:
11 * Andre Hedrick
12 */
13
14 /*
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published by
17 * the Free Software Foundation.
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/ide.h>
27 #include <asm/io.h>
28
29 #include "ide-timing.h"
30
31 #define DISPLAY_AMD_TIMINGS
32
33 #define AMD_IDE_ENABLE (0x00 + amd_config->base)
34 #define AMD_IDE_CONFIG (0x01 + amd_config->base)
35 #define AMD_CABLE_DETECT (0x02 + amd_config->base)
36 #define AMD_DRIVE_TIMING (0x08 + amd_config->base)
37 #define AMD_8BIT_TIMING (0x0e + amd_config->base)
38 #define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
39 #define AMD_UDMA_TIMING (0x10 + amd_config->base)
40
41 #define AMD_CHECK_SWDMA 0x08
42 #define AMD_BAD_SWDMA 0x10
43 #define AMD_BAD_FIFO 0x20
44 #define AMD_CHECK_SERENADE 0x40
45
46 /*
47 * AMD SouthBridge chips.
48 */
49
50 static struct amd_ide_chip {
51 unsigned short id;
52 u8 base;
53 u8 udma_mask;
54 u8 flags;
55 } amd_ide_chips[] = {
56 { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, ATA_UDMA2, AMD_BAD_SWDMA },
57 { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, ATA_UDMA4, AMD_CHECK_SWDMA },
58 { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, ATA_UDMA5, AMD_BAD_FIFO },
59 { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, ATA_UDMA5, },
60 { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, ATA_UDMA6, AMD_CHECK_SERENADE },
61 { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, ATA_UDMA5, },
62 { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, ATA_UDMA6, },
63 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, ATA_UDMA6, },
64 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, ATA_UDMA6, },
65 { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, ATA_UDMA6, },
66 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, ATA_UDMA6, },
67 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, ATA_UDMA6, },
68 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, ATA_UDMA6, },
69 { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, ATA_UDMA6, },
70 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, ATA_UDMA6, },
71 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, ATA_UDMA6, },
72 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, ATA_UDMA6, },
73 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, 0x50, ATA_UDMA6, },
74 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, 0x50, ATA_UDMA6, },
75 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, 0x50, ATA_UDMA6, },
76 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, 0x50, ATA_UDMA6, },
77 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, 0x50, ATA_UDMA6, },
78 { PCI_DEVICE_ID_AMD_CS5536_IDE, 0x40, ATA_UDMA5, },
79 { 0 }
80 };
81
82 static struct amd_ide_chip *amd_config;
83 static ide_pci_device_t *amd_chipset;
84 static unsigned int amd_80w;
85 static unsigned int amd_clock;
86
87 static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
88 static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
89
90 /*
91 * AMD /proc entry.
92 */
93
94 #ifdef CONFIG_IDE_PROC_FS
95
96 #include <linux/stat.h>
97 #include <linux/proc_fs.h>
98
99 static u8 amd74xx_proc;
100
101 static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
102 static unsigned long amd_base;
103 static struct pci_dev *bmide_dev;
104 extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
105
106 #define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
107 #define amd_print_drive(name, format, arg...)\
108 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
109
110 static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
111 {
112 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
113 uen[4], udma[4], active8b[4], recover8b[4];
114 struct pci_dev *dev = bmide_dev;
115 unsigned int v, u, i;
116 unsigned short c, w;
117 unsigned char t;
118 int len;
119 char *p = buffer;
120
121 amd_print("----------AMD BusMastering IDE Configuration----------------");
122
123 amd_print("Driver Version: 2.13");
124 amd_print("South Bridge: %s", pci_name(bmide_dev));
125
126 amd_print("Revision: IDE %#x", dev->revision);
127 amd_print("Highest DMA rate: UDMA%s", amd_dma[fls(amd_config->udma_mask) - 1]);
128
129 amd_print("BM-DMA base: %#lx", amd_base);
130 amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
131
132 amd_print("-----------------------Primary IDE-------Secondary IDE------");
133
134 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
135 amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
136 amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
137
138 pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
139 amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
140
141 c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
142 amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
143
144 amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
145
146 if (!amd_clock)
147 return p - buffer;
148
149 amd_print("-------------------drive0----drive1----drive2----drive3-----");
150
151 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
152 pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
153 pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
154 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
155
156 for (i = 0; i < 4; i++) {
157 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
158 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
159 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
160 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
161 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
162
163 udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
164 uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
165 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
166
167 if (den[i] && uen[i] && udma[i] == 1) {
168 speed[i] = amd_clock * 3;
169 cycle[i] = 666666 / amd_clock;
170 continue;
171 }
172
173 if (den[i] && uen[i] && udma[i] == 15) {
174 speed[i] = amd_clock * 4;
175 cycle[i] = 500000 / amd_clock;
176 continue;
177 }
178
179 speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
180 cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
181 }
182
183 amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
184
185 amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
186 amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock);
187 amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock);
188 amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock);
189 amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
190 amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
191 amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
192
193 /* hoping p - buffer is less than 4K... */
194 len = (p - buffer) - offset;
195 *addr = buffer + offset;
196
197 return len > count ? count : len;
198 }
199
200 #endif
201
202 /*
203 * amd_set_speed() writes timing values to the chipset registers
204 */
205
206 static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
207 {
208 unsigned char t;
209
210 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
211 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
212 pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
213
214 pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
215 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
216
217 pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
218 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
219
220 switch (amd_config->udma_mask) {
221 case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
222 case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
223 case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
224 case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
225 default: return;
226 }
227
228 pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
229 }
230
231 /*
232 * amd_set_drive() computes timing values and configures the chipset
233 * to a desired transfer mode. It also can be called by upper layers.
234 */
235
236 static void amd_set_drive(ide_drive_t *drive, const u8 speed)
237 {
238 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
239 struct ide_timing t, p;
240 int T, UT;
241
242 T = 1000000000 / amd_clock;
243 UT = (amd_config->udma_mask == ATA_UDMA2) ? T : (T / 2);
244
245 ide_timing_compute(drive, speed, &t, T, UT);
246
247 if (peer->present) {
248 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
249 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
250 }
251
252 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
253 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
254
255 amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
256 }
257
258 /*
259 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
260 */
261
262 static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
263 {
264 amd_set_drive(drive, XFER_PIO_0 + pio);
265 }
266
267 static int amd74xx_ide_dma_check(ide_drive_t *drive)
268 {
269 if (ide_tune_dma(drive))
270 return 0;
271
272 ide_set_max_pio(drive);
273
274 return -1;
275 }
276
277 /*
278 * The initialization callback. Here we determine the IDE chip type
279 * and initialize its drive independent registers.
280 */
281
282 static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const char *name)
283 {
284 unsigned char t;
285 unsigned int u;
286 int i;
287
288 /*
289 * Check for bad SWDMA.
290 */
291
292 if (amd_config->flags & AMD_CHECK_SWDMA) {
293 if (dev->revision <= 7)
294 amd_config->flags |= AMD_BAD_SWDMA;
295 }
296
297 /*
298 * Check 80-wire cable presence.
299 */
300
301 switch (amd_config->udma_mask) {
302
303 case ATA_UDMA6:
304 case ATA_UDMA5:
305 pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
306 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
307 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
308 for (i = 24; i >= 0; i -= 8)
309 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
310 printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
311 amd_chipset->name);
312 amd_80w |= (1 << (1 - (i >> 4)));
313 }
314 break;
315
316 case ATA_UDMA4:
317 /* no host side cable detection */
318 amd_80w = 0x03;
319 break;
320 }
321
322 /*
323 * Take care of prefetch & postwrite.
324 */
325
326 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
327 pci_write_config_byte(dev, AMD_IDE_CONFIG,
328 (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
329
330 /*
331 * Take care of incorrectly wired Serenade mainboards.
332 */
333
334 if ((amd_config->flags & AMD_CHECK_SERENADE) &&
335 dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
336 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
337 amd_config->udma_mask = ATA_UDMA5;
338
339 /*
340 * Determine the system bus clock.
341 */
342
343 amd_clock = system_bus_clock() * 1000;
344
345 switch (amd_clock) {
346 case 33000: amd_clock = 33333; break;
347 case 37000: amd_clock = 37500; break;
348 case 41000: amd_clock = 41666; break;
349 }
350
351 if (amd_clock < 20000 || amd_clock > 50000) {
352 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
353 amd_chipset->name, amd_clock);
354 amd_clock = 33333;
355 }
356
357 /*
358 * Print the boot message.
359 */
360
361 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
362 printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
363 amd_chipset->name, pci_name(dev), dev->revision,
364 amd_dma[fls(amd_config->udma_mask) - 1]);
365
366 /*
367 * Register /proc/ide/amd74xx entry
368 */
369
370 #if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
371 if (!amd74xx_proc) {
372 amd_base = pci_resource_start(dev, 4);
373 bmide_dev = dev;
374 ide_pci_create_host_proc("amd74xx", amd74xx_get_info);
375 amd74xx_proc = 1;
376 }
377 #endif /* DISPLAY_AMD_TIMINGS && CONFIG_IDE_PROC_FS */
378
379 return dev->irq;
380 }
381
382 static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
383 {
384 int i;
385
386 if (hwif->irq == 0) /* 0 is bogus but will do for now */
387 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
388
389 hwif->autodma = 0;
390
391 hwif->set_pio_mode = &amd_set_pio_mode;
392 hwif->set_dma_mode = &amd_set_drive;
393
394 for (i = 0; i < 2; i++) {
395 hwif->drives[i].io_32bit = 1;
396 hwif->drives[i].unmask = 1;
397 hwif->drives[i].autotune = 1;
398 hwif->drives[i].dn = hwif->channel * 2 + i;
399 }
400
401 if (!hwif->dma_base)
402 return;
403
404 hwif->atapi_dma = 1;
405
406 hwif->ultra_mask = amd_config->udma_mask;
407 hwif->mwdma_mask = 0x07;
408 if ((amd_config->flags & AMD_BAD_SWDMA) == 0)
409 hwif->swdma_mask = 0x07;
410
411 if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
412 if ((amd_80w >> hwif->channel) & 1)
413 hwif->cbl = ATA_CBL_PATA80;
414 else
415 hwif->cbl = ATA_CBL_PATA40;
416 }
417
418 hwif->ide_dma_check = &amd74xx_ide_dma_check;
419 if (!noautodma)
420 hwif->autodma = 1;
421 hwif->drives[0].autodma = hwif->autodma;
422 hwif->drives[1].autodma = hwif->autodma;
423 }
424
425 #define DECLARE_AMD_DEV(name_str) \
426 { \
427 .name = name_str, \
428 .init_chipset = init_chipset_amd74xx, \
429 .init_hwif = init_hwif_amd74xx, \
430 .autodma = AUTODMA, \
431 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
432 .bootable = ON_BOARD, \
433 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \
434 | IDE_HFLAG_PIO_NO_DOWNGRADE \
435 | IDE_HFLAG_POST_SET_MODE, \
436 .pio_mask = ATA_PIO5, \
437 }
438
439 #define DECLARE_NV_DEV(name_str) \
440 { \
441 .name = name_str, \
442 .init_chipset = init_chipset_amd74xx, \
443 .init_hwif = init_hwif_amd74xx, \
444 .autodma = AUTODMA, \
445 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
446 .bootable = ON_BOARD, \
447 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \
448 | IDE_HFLAG_PIO_NO_DOWNGRADE \
449 | IDE_HFLAG_POST_SET_MODE, \
450 .pio_mask = ATA_PIO5, \
451 }
452
453 static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
454 /* 0 */ DECLARE_AMD_DEV("AMD7401"),
455 /* 1 */ DECLARE_AMD_DEV("AMD7409"),
456 /* 2 */ DECLARE_AMD_DEV("AMD7411"),
457 /* 3 */ DECLARE_AMD_DEV("AMD7441"),
458 /* 4 */ DECLARE_AMD_DEV("AMD8111"),
459
460 /* 5 */ DECLARE_NV_DEV("NFORCE"),
461 /* 6 */ DECLARE_NV_DEV("NFORCE2"),
462 /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
463 /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
464 /* 9 */ DECLARE_NV_DEV("NFORCE3-150"),
465 /* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
466 /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
467 /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
468 /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
469 /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
470 /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
471 /* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
472 /* 17 */ DECLARE_NV_DEV("NFORCE-MCP61"),
473 /* 18 */ DECLARE_NV_DEV("NFORCE-MCP65"),
474 /* 19 */ DECLARE_NV_DEV("NFORCE-MCP67"),
475 /* 20 */ DECLARE_NV_DEV("NFORCE-MCP73"),
476 /* 21 */ DECLARE_NV_DEV("NFORCE-MCP77"),
477 /* 22 */ DECLARE_AMD_DEV("AMD5536"),
478 };
479
480 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
481 {
482 amd_chipset = amd74xx_chipsets + id->driver_data;
483 amd_config = amd_ide_chips + id->driver_data;
484 if (dev->device != amd_config->id) {
485 printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
486 pci_name(dev), dev->device, amd_config->id);
487 return -ENODEV;
488 }
489 return ide_setup_pci_device(dev, amd_chipset);
490 }
491
492 static struct pci_device_id amd74xx_pci_tbl[] = {
493 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
494 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
495 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
496 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
497 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
498 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
499 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
500 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
501 #ifdef CONFIG_BLK_DEV_IDE_SATA
502 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
503 #endif
504 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
505 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
506 #ifdef CONFIG_BLK_DEV_IDE_SATA
507 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
508 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
509 #endif
510 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 },
511 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
512 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15 },
513 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16 },
514 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17 },
515 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18 },
516 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19 },
517 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20 },
518 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21 },
519 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22 },
520 { 0, },
521 };
522 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
523
524 static struct pci_driver driver = {
525 .name = "AMD_IDE",
526 .id_table = amd74xx_pci_tbl,
527 .probe = amd74xx_probe,
528 };
529
530 static int __init amd74xx_ide_init(void)
531 {
532 return ide_pci_register_driver(&driver);
533 }
534
535 module_init(amd74xx_ide_init);
536
537 MODULE_AUTHOR("Vojtech Pavlik");
538 MODULE_DESCRIPTION("AMD PCI IDE driver");
539 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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