drivers/ide/pci/amd74xx.c

   1 /*
   2  * Version 2.24
   3  *
   4  * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
   5  * IDE driver for Linux.
   6  *
   7  * Copyright (c) 2000-2002 Vojtech Pavlik
   8  * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
   9  *
  10  * Based on the work of:
  11  *      Andre Hedrick
  12  */
  13
  14 /*
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License version 2 as published by
  17  * the Free Software Foundation.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/ioport.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/pci.h>
  25 #include <linux/init.h>
  26 #include <linux/ide.h>
  27 #include <asm/io.h>
  28
  29 #include "ide-timing.h"
  30
  31 #define AMD_IDE_CONFIG          (0x01 + amd_config->base)
  32 #define AMD_CABLE_DETECT        (0x02 + amd_config->base)
  33 #define AMD_DRIVE_TIMING        (0x08 + amd_config->base)
  34 #define AMD_8BIT_TIMING         (0x0e + amd_config->base)
  35 #define AMD_ADDRESS_SETUP       (0x0c + amd_config->base)
  36 #define AMD_UDMA_TIMING         (0x10 + amd_config->base)
  37
  38 #define AMD_CHECK_SWDMA         0x08
  39 #define AMD_BAD_SWDMA           0x10
  40 #define AMD_BAD_FIFO            0x20
  41 #define AMD_CHECK_SERENADE      0x40
  42
  43 /*
  44  * AMD SouthBridge chips.
  45  */
  46
  47 static struct amd_ide_chip {
  48         unsigned short id;
  49         u8 base;
  50         u8 udma_mask;
  51         u8 flags;
  52 } amd_ide_chips[] = {
  53         { PCI_DEVICE_ID_AMD_COBRA_7401,          0x40, ATA_UDMA2, AMD_BAD_SWDMA },
  54         { PCI_DEVICE_ID_AMD_VIPER_7409,          0x40, ATA_UDMA4, AMD_CHECK_SWDMA },
  55         { PCI_DEVICE_ID_AMD_VIPER_7411,          0x40, ATA_UDMA5, AMD_BAD_FIFO },
  56         { PCI_DEVICE_ID_AMD_OPUS_7441,           0x40, ATA_UDMA5, },
  57         { PCI_DEVICE_ID_AMD_8111_IDE,            0x40, ATA_UDMA6, AMD_CHECK_SERENADE },
  58         { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE,       0x50, ATA_UDMA5, },
  59         { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE,      0x50, ATA_UDMA6, },
  60         { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE,     0x50, ATA_UDMA6, },
  61         { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,    0x50, ATA_UDMA6, },
  62         { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE,      0x50, ATA_UDMA6, },
  63         { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE,     0x50, ATA_UDMA6, },
  64         { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,    0x50, ATA_UDMA6, },
  65         { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,   0x50, ATA_UDMA6, },
  66         { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, ATA_UDMA6, },
  67         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, ATA_UDMA6, },
  68         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, ATA_UDMA6, },
  69         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, ATA_UDMA6, },
  70         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, 0x50, ATA_UDMA6, },
  71         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, 0x50, ATA_UDMA6, },
  72         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, 0x50, ATA_UDMA6, },
  73         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, 0x50, ATA_UDMA6, },
  74         { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, 0x50, ATA_UDMA6, },
  75         { PCI_DEVICE_ID_AMD_CS5536_IDE,          0x40, ATA_UDMA5, },
  76         { 0 }
  77 };
  78
  79 static struct amd_ide_chip *amd_config;
  80 static const struct ide_port_info *amd_chipset;
  81 static unsigned int amd_80w;
  82 static unsigned int amd_clock;
  83
  84 static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
  85 static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
  86
  87 /*
  88  * amd_set_speed() writes timing values to the chipset registers
  89  */
  90
  91 static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
  92 {
  93         unsigned char t;
  94
  95         pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
  96         t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
  97         pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
  98
  99         pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
 100                 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
 101
 102         pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
 103                 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
 104
 105         switch (amd_config->udma_mask) {
 106         case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
 107         case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
 108         case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
 109         case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
 110         default: return;
 111         }
 112
 113         pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
 114 }
 115
 116 /*
 117  * amd_set_drive() computes timing values and configures the chipset
 118  * to a desired transfer mode.  It also can be called by upper layers.
 119  */
 120
 121 static void amd_set_drive(ide_drive_t *drive, const u8 speed)
 122 {
 123         ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
 124         struct ide_timing t, p;
 125         int T, UT;
 126
 127         T = 1000000000 / amd_clock;
 128         UT = (amd_config->udma_mask == ATA_UDMA2) ? T : (T / 2);
 129
 130         ide_timing_compute(drive, speed, &t, T, UT);
 131
 132         if (peer->present) {
 133                 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
 134                 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
 135         }
 136
 137         if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
 138         if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
 139
 140         amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
 141 }
 142
 143 /*
 144  * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
 145  */
 146
 147 static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
 148 {
 149         amd_set_drive(drive, XFER_PIO_0 + pio);
 150 }
 151
 152 /*
 153  * The initialization callback. Here we determine the IDE chip type
 154  * and initialize its drive independent registers.
 155  */
 156
 157 static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const char *name)
 158 {
 159         unsigned char t;
 160         unsigned int u;
 161         int i;
 162
 163 /*
 164  * Check for bad SWDMA.
 165  */
 166
 167         if (amd_config->flags & AMD_CHECK_SWDMA) {
 168                 if (dev->revision <= 7)
 169                         amd_config->flags |= AMD_BAD_SWDMA;
 170         }
 171
 172 /*
 173  * Check 80-wire cable presence.
 174  */
 175
 176         switch (amd_config->udma_mask) {
 177
 178                 case ATA_UDMA6:
 179                 case ATA_UDMA5:
 180                         pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
 181                         pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
 182                         amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
 183                         for (i = 24; i >= 0; i -= 8)
 184                                 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
 185                                         printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
 186                                                 amd_chipset->name);
 187                                         amd_80w |= (1 << (1 - (i >> 4)));
 188                                 }
 189                         break;
 190
 191                 case ATA_UDMA4:
 192                         /* no host side cable detection */
 193                         amd_80w = 0x03;
 194                         break;
 195         }
 196
 197 /*
 198  * Take care of prefetch & postwrite.
 199  */
 200
 201         pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
 202         pci_write_config_byte(dev, AMD_IDE_CONFIG,
 203                 (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
 204
 205 /*
 206  * Take care of incorrectly wired Serenade mainboards.
 207  */
 208
 209         if ((amd_config->flags & AMD_CHECK_SERENADE) &&
 210                 dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
 211                 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
 212                         amd_config->udma_mask = ATA_UDMA5;
 213
 214 /*
 215  * Determine the system bus clock.
 216  */
 217
 218         amd_clock = system_bus_clock() * 1000;
 219
 220         switch (amd_clock) {
 221                 case 33000: amd_clock = 33333; break;
 222                 case 37000: amd_clock = 37500; break;
 223                 case 41000: amd_clock = 41666; break;
 224         }
 225
 226         if (amd_clock < 20000 || amd_clock > 50000) {
 227                 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
 228                         amd_chipset->name, amd_clock);
 229                 amd_clock = 33333;
 230         }
 231
 232 /*
 233  * Print the boot message.
 234  */
 235
 236         printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
 237                 amd_chipset->name, pci_name(dev), dev->revision,
 238                 amd_dma[fls(amd_config->udma_mask) - 1]);
 239
 240         return dev->irq;
 241 }
 242
 243 static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
 244 {
 245         if (hwif->irq == 0) /* 0 is bogus but will do for now */
 246                 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
 247
 248         hwif->set_pio_mode = &amd_set_pio_mode;
 249         hwif->set_dma_mode = &amd_set_drive;
 250
 251         if (!hwif->dma_base)
 252                 return;
 253
 254         hwif->ultra_mask = amd_config->udma_mask;
 255         if (amd_config->flags & AMD_BAD_SWDMA)
 256                 hwif->swdma_mask = 0x00;
 257
 258         if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
 259                 if ((amd_80w >> hwif->channel) & 1)
 260                         hwif->cbl = ATA_CBL_PATA80;
 261                 else
 262                         hwif->cbl = ATA_CBL_PATA40;
 263         }
 264 }
 265
 266 #define IDE_HFLAGS_AMD \
 267         (IDE_HFLAG_PIO_NO_BLACKLIST | \
 268          IDE_HFLAG_PIO_NO_DOWNGRADE | \
 269          IDE_HFLAG_POST_SET_MODE | \
 270          IDE_HFLAG_IO_32BIT | \
 271          IDE_HFLAG_UNMASK_IRQS | \
 272          IDE_HFLAG_BOOTABLE)
 273
 274 #define DECLARE_AMD_DEV(name_str)                                       \
 275         {                                                               \
 276                 .name           = name_str,                             \
 277                 .init_chipset   = init_chipset_amd74xx,                 \
 278                 .init_hwif      = init_hwif_amd74xx,                    \
 279                 .enablebits     = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
 280                 .host_flags     = IDE_HFLAGS_AMD,                       \
 281                 .pio_mask       = ATA_PIO5,                             \
 282                 .swdma_mask     = ATA_SWDMA2,                           \
 283                 .mwdma_mask     = ATA_MWDMA2,                           \
 284         }
 285
 286 #define DECLARE_NV_DEV(name_str)                                        \
 287         {                                                               \
 288                 .name           = name_str,                             \
 289                 .init_chipset   = init_chipset_amd74xx,                 \
 290                 .init_hwif      = init_hwif_amd74xx,                    \
 291                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
 292                 .host_flags     = IDE_HFLAGS_AMD,                       \
 293                 .pio_mask       = ATA_PIO5,                             \
 294                 .swdma_mask     = ATA_SWDMA2,                           \
 295                 .mwdma_mask     = ATA_MWDMA2,                           \
 296         }
 297
 298 static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
 299         /*  0 */ DECLARE_AMD_DEV("AMD7401"),
 300         /*  1 */ DECLARE_AMD_DEV("AMD7409"),
 301         /*  2 */ DECLARE_AMD_DEV("AMD7411"),
 302         /*  3 */ DECLARE_AMD_DEV("AMD7441"),
 303         /*  4 */ DECLARE_AMD_DEV("AMD8111"),
 304
 305         /*  5 */ DECLARE_NV_DEV("NFORCE"),
 306         /*  6 */ DECLARE_NV_DEV("NFORCE2"),
 307         /*  7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
 308         /*  8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
 309         /*  9 */ DECLARE_NV_DEV("NFORCE3-150"),
 310         /* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
 311         /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
 312         /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
 313         /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
 314         /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
 315         /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
 316         /* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
 317         /* 17 */ DECLARE_NV_DEV("NFORCE-MCP61"),
 318         /* 18 */ DECLARE_NV_DEV("NFORCE-MCP65"),
 319         /* 19 */ DECLARE_NV_DEV("NFORCE-MCP67"),
 320         /* 20 */ DECLARE_NV_DEV("NFORCE-MCP73"),
 321         /* 21 */ DECLARE_NV_DEV("NFORCE-MCP77"),
 322         /* 22 */ DECLARE_AMD_DEV("AMD5536"),
 323 };
 324
 325 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
 326 {
 327         amd_chipset = amd74xx_chipsets + id->driver_data;
 328         amd_config = amd_ide_chips + id->driver_data;
 329         if (dev->device != amd_config->id) {
 330                 printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
 331                        pci_name(dev), dev->device, amd_config->id);
 332                 return -ENODEV;
 333         }
 334         return ide_setup_pci_device(dev, amd_chipset);
 335 }
 336
 337 static const struct pci_device_id amd74xx_pci_tbl[] = {
 338         { PCI_VDEVICE(AMD,      PCI_DEVICE_ID_AMD_COBRA_7401),           0 },
 339         { PCI_VDEVICE(AMD,      PCI_DEVICE_ID_AMD_VIPER_7409),           1 },
 340         { PCI_VDEVICE(AMD,      PCI_DEVICE_ID_AMD_VIPER_7411),           2 },
 341         { PCI_VDEVICE(AMD,      PCI_DEVICE_ID_AMD_OPUS_7441),            3 },
 342         { PCI_VDEVICE(AMD,      PCI_DEVICE_ID_AMD_8111_IDE),             4 },
 343         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),        5 },
 344         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),       6 },
 345         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),      7 },
 346 #ifdef CONFIG_BLK_DEV_IDE_SATA
 347         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA),     8 },
 348 #endif
 349         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),       9 },
 350         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),     10 },
 351 #ifdef CONFIG_BLK_DEV_IDE_SATA
 352         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA),    11 },
 353         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2),   12 },
 354 #endif
 355         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 },
 356         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 },
 357         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 },
 358         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 },
 359         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 },
 360         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 },
 361         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 },
 362         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 },
 363         { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 },
 364         { PCI_VDEVICE(AMD,      PCI_DEVICE_ID_AMD_CS5536_IDE),          22 },
 365         { 0, },
 366 };
 367 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
 368
 369 static struct pci_driver driver = {
 370         .name           = "AMD_IDE",
 371         .id_table       = amd74xx_pci_tbl,
 372         .probe          = amd74xx_probe,
 373 };
 374
 375 static int __init amd74xx_ide_init(void)
 376 {
 377         return ide_pci_register_driver(&driver);
 378 }
 379
 380 module_init(amd74xx_ide_init);
 381
 382 MODULE_AUTHOR("Vojtech Pavlik");
 383 MODULE_DESCRIPTION("AMD PCI IDE driver");
 384 MODULE_LICENSE("GPL");