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ide: add short cables support
[deliverable/linux.git] / drivers / ide / pci / cmd64x.c
1 /*
2 * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007
3 *
4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
5 * Due to massive hardware bugs, UltraDMA is only supported
6 * on the 646U2 and not on the 646U.
7 *
8 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
10 *
11 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/hdreg.h>
20 #include <linux/ide.h>
21 #include <linux/init.h>
22
23 #include <asm/io.h>
24
25 #define DISPLAY_CMD64X_TIMINGS
26
27 #define CMD_DEBUG 0
28
29 #if CMD_DEBUG
30 #define cmdprintk(x...) printk(x)
31 #else
32 #define cmdprintk(x...)
33 #endif
34
35 /*
36 * CMD64x specific registers definition.
37 */
38 #define CFR 0x50
39 #define CFR_INTR_CH0 0x04
40 #define CNTRL 0x51
41 #define CNTRL_ENA_1ST 0x04
42 #define CNTRL_ENA_2ND 0x08
43 #define CNTRL_DIS_RA0 0x40
44 #define CNTRL_DIS_RA1 0x80
45
46 #define CMDTIM 0x52
47 #define ARTTIM0 0x53
48 #define DRWTIM0 0x54
49 #define ARTTIM1 0x55
50 #define DRWTIM1 0x56
51 #define ARTTIM23 0x57
52 #define ARTTIM23_DIS_RA2 0x04
53 #define ARTTIM23_DIS_RA3 0x08
54 #define ARTTIM23_INTR_CH1 0x10
55 #define DRWTIM2 0x58
56 #define BRST 0x59
57 #define DRWTIM3 0x5b
58
59 #define BMIDECR0 0x70
60 #define MRDMODE 0x71
61 #define MRDMODE_INTR_CH0 0x04
62 #define MRDMODE_INTR_CH1 0x08
63 #define MRDMODE_BLK_CH0 0x10
64 #define MRDMODE_BLK_CH1 0x20
65 #define BMIDESR0 0x72
66 #define UDIDETCR0 0x73
67 #define DTPR0 0x74
68 #define BMIDECR1 0x78
69 #define BMIDECSR 0x79
70 #define BMIDESR1 0x7A
71 #define UDIDETCR1 0x7B
72 #define DTPR1 0x7C
73
74 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
75 #include <linux/stat.h>
76 #include <linux/proc_fs.h>
77
78 static u8 cmd64x_proc = 0;
79
80 #define CMD_MAX_DEVS 5
81
82 static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
83 static int n_cmd_devs;
84
85 static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
86 {
87 char *p = buf;
88 u8 reg72 = 0, reg73 = 0; /* primary */
89 u8 reg7a = 0, reg7b = 0; /* secondary */
90 u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
91 u8 rev = 0;
92
93 p += sprintf(p, "\nController: %d\n", index);
94 p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
95
96 (void) pci_read_config_byte(dev, CFR, &reg50);
97 (void) pci_read_config_byte(dev, CNTRL, &reg51);
98 (void) pci_read_config_byte(dev, ARTTIM23, &reg57);
99 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
100 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
101 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
102 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
103 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
104
105 /* PCI0643/6 originally didn't have the primary channel enable bit */
106 (void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
107 if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
108 (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3))
109 reg51 |= CNTRL_ENA_1ST;
110
111 p += sprintf(p, "---------------- Primary Channel "
112 "---------------- Secondary Channel ------------\n");
113 p += sprintf(p, " %s %s\n",
114 (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
115 (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
116 p += sprintf(p, "---------------- drive0 --------- drive1 "
117 "-------- drive0 --------- drive1 ------\n");
118 p += sprintf(p, "DMA enabled: %s %s"
119 " %s %s\n",
120 (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
121 (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
122 p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
123 ( reg73 & 0x01) ? " on" : "off",
124 ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
125 ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
126 ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
127 ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
128 ( reg73 & 0x02) ? " on" : "off",
129 ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
130 ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
131 ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
132 ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
133 p += sprintf(p, " %s (%c) %s (%c)\n",
134 ( reg7b & 0x01) ? " on" : "off",
135 ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
136 ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
137 ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
138 ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
139 ( reg7b & 0x02) ? " on" : "off",
140 ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
141 ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
142 ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
143 ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
144 p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
145 (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
146 (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
147 (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
148 (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
149
150 return (char *)p;
151 }
152
153 static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
154 {
155 char *p = buffer;
156 int i;
157
158 for (i = 0; i < n_cmd_devs; i++) {
159 struct pci_dev *dev = cmd_devs[i];
160 p = print_cmd64x_get_info(p, dev, i);
161 }
162 return p-buffer; /* => must be less than 4k! */
163 }
164
165 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
166
167 static u8 quantize_timing(int timing, int quant)
168 {
169 return (timing + quant - 1) / quant;
170 }
171
172 /*
173 * This routine calculates active/recovery counts and then writes them into
174 * the chipset registers.
175 */
176 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
177 {
178 struct pci_dev *dev = HWIF(drive)->pci_dev;
179 int clock_time = 1000 / system_bus_clock();
180 u8 cycle_count, active_count, recovery_count, drwtim;
181 static const u8 recovery_values[] =
182 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
183 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
184
185 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
186 cycle_time, active_time);
187
188 cycle_count = quantize_timing( cycle_time, clock_time);
189 active_count = quantize_timing(active_time, clock_time);
190 recovery_count = cycle_count - active_count;
191
192 /*
193 * In case we've got too long recovery phase, try to lengthen
194 * the active phase
195 */
196 if (recovery_count > 16) {
197 active_count += recovery_count - 16;
198 recovery_count = 16;
199 }
200 if (active_count > 16) /* shouldn't actually happen... */
201 active_count = 16;
202
203 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
204 cycle_count, active_count, recovery_count);
205
206 /*
207 * Convert values to internal chipset representation
208 */
209 recovery_count = recovery_values[recovery_count];
210 active_count &= 0x0f;
211
212 /* Program the active/recovery counts into the DRWTIM register */
213 drwtim = (active_count << 4) | recovery_count;
214 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
215 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
216 }
217
218 /*
219 * This routine selects drive's best PIO mode and writes into the chipset
220 * registers setup/active/recovery timings.
221 */
222 static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
223 {
224 ide_hwif_t *hwif = HWIF(drive);
225 struct pci_dev *dev = hwif->pci_dev;
226 ide_pio_data_t pio;
227 u8 pio_mode, setup_count, arttim = 0;
228 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
229 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
230 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
231
232 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
233 drive->name, mode_wanted, pio_mode, pio.cycle_time,
234 pio.overridden ? " (overriding vendor mode)" : "");
235
236 program_cycle_times(drive, pio.cycle_time,
237 ide_pio_timings[pio_mode].active_time);
238
239 setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
240 1000 / system_bus_clock());
241
242 /*
243 * The primary channel has individual address setup timing registers
244 * for each drive and the hardware selects the slowest timing itself.
245 * The secondary channel has one common register and we have to select
246 * the slowest address setup timing ourselves.
247 */
248 if (hwif->channel) {
249 ide_drive_t *drives = hwif->drives;
250
251 drive->drive_data = setup_count;
252 setup_count = max(drives[0].drive_data, drives[1].drive_data);
253 }
254
255 if (setup_count > 5) /* shouldn't actually happen... */
256 setup_count = 5;
257 cmdprintk("Final address setup count: %d\n", setup_count);
258
259 /*
260 * Program the address setup clocks into the ARTTIM registers.
261 * Avoid clearing the secondary channel's interrupt bit.
262 */
263 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
264 if (hwif->channel)
265 arttim &= ~ARTTIM23_INTR_CH1;
266 arttim &= ~0xc0;
267 arttim |= setup_values[setup_count];
268 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
269 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
270
271 return pio_mode;
272 }
273
274 /*
275 * Attempts to set drive's PIO mode.
276 * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
277 * and 255: auto-select best mode (used at boot time).
278 */
279 static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio)
280 {
281 /*
282 * Filter out the prefetch control values
283 * to prevent PIO5 from being programmed
284 */
285 if (pio == 8 || pio == 9)
286 return;
287
288 pio = cmd64x_tune_pio(drive, pio);
289 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
290 }
291
292 static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
293 {
294 ide_hwif_t *hwif = HWIF(drive);
295 struct pci_dev *dev = hwif->pci_dev;
296 u8 unit = drive->dn & 0x01;
297 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
298
299 speed = ide_rate_filter(drive, speed);
300
301 if (speed >= XFER_SW_DMA_0) {
302 (void) pci_read_config_byte(dev, pciU, &regU);
303 regU &= ~(unit ? 0xCA : 0x35);
304 }
305
306 switch(speed) {
307 case XFER_UDMA_5:
308 regU |= unit ? 0x0A : 0x05;
309 break;
310 case XFER_UDMA_4:
311 regU |= unit ? 0x4A : 0x15;
312 break;
313 case XFER_UDMA_3:
314 regU |= unit ? 0x8A : 0x25;
315 break;
316 case XFER_UDMA_2:
317 regU |= unit ? 0x42 : 0x11;
318 break;
319 case XFER_UDMA_1:
320 regU |= unit ? 0x82 : 0x21;
321 break;
322 case XFER_UDMA_0:
323 regU |= unit ? 0xC2 : 0x31;
324 break;
325 case XFER_MW_DMA_2:
326 program_cycle_times(drive, 120, 70);
327 break;
328 case XFER_MW_DMA_1:
329 program_cycle_times(drive, 150, 80);
330 break;
331 case XFER_MW_DMA_0:
332 program_cycle_times(drive, 480, 215);
333 break;
334 case XFER_PIO_5:
335 case XFER_PIO_4:
336 case XFER_PIO_3:
337 case XFER_PIO_2:
338 case XFER_PIO_1:
339 case XFER_PIO_0:
340 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
341 break;
342 default:
343 return 1;
344 }
345
346 if (speed >= XFER_SW_DMA_0)
347 (void) pci_write_config_byte(dev, pciU, regU);
348
349 return ide_config_drive_speed(drive, speed);
350 }
351
352 static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
353 {
354 if (ide_tune_dma(drive))
355 return 0;
356
357 if (ide_use_fast_pio(drive))
358 cmd64x_tune_drive(drive, 255);
359
360 return -1;
361 }
362
363 static int cmd648_ide_dma_end (ide_drive_t *drive)
364 {
365 ide_hwif_t *hwif = HWIF(drive);
366 int err = __ide_dma_end(drive);
367 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
368 MRDMODE_INTR_CH0;
369 u8 mrdmode = inb(hwif->dma_master + 0x01);
370
371 /* clear the interrupt bit */
372 outb(mrdmode | irq_mask, hwif->dma_master + 0x01);
373
374 return err;
375 }
376
377 static int cmd64x_ide_dma_end (ide_drive_t *drive)
378 {
379 ide_hwif_t *hwif = HWIF(drive);
380 struct pci_dev *dev = hwif->pci_dev;
381 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
382 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
383 CFR_INTR_CH0;
384 u8 irq_stat = 0;
385 int err = __ide_dma_end(drive);
386
387 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
388 /* clear the interrupt bit */
389 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
390
391 return err;
392 }
393
394 static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
395 {
396 ide_hwif_t *hwif = HWIF(drive);
397 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
398 MRDMODE_INTR_CH0;
399 u8 dma_stat = inb(hwif->dma_status);
400 u8 mrdmode = inb(hwif->dma_master + 0x01);
401
402 #ifdef DEBUG
403 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
404 drive->name, dma_stat, mrdmode, irq_mask);
405 #endif
406 if (!(mrdmode & irq_mask))
407 return 0;
408
409 /* return 1 if INTR asserted */
410 if (dma_stat & 4)
411 return 1;
412
413 return 0;
414 }
415
416 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
417 {
418 ide_hwif_t *hwif = HWIF(drive);
419 struct pci_dev *dev = hwif->pci_dev;
420 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
421 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
422 CFR_INTR_CH0;
423 u8 dma_stat = inb(hwif->dma_status);
424 u8 irq_stat = 0;
425
426 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
427
428 #ifdef DEBUG
429 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
430 drive->name, dma_stat, irq_stat, irq_mask);
431 #endif
432 if (!(irq_stat & irq_mask))
433 return 0;
434
435 /* return 1 if INTR asserted */
436 if (dma_stat & 4)
437 return 1;
438
439 return 0;
440 }
441
442 /*
443 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
444 * event order for DMA transfers.
445 */
446
447 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
448 {
449 ide_hwif_t *hwif = HWIF(drive);
450 u8 dma_stat = 0, dma_cmd = 0;
451
452 drive->waiting_for_dma = 0;
453 /* get DMA status */
454 dma_stat = inb(hwif->dma_status);
455 /* read DMA command state */
456 dma_cmd = inb(hwif->dma_command);
457 /* stop DMA */
458 outb(dma_cmd & ~1, hwif->dma_command);
459 /* clear the INTR & ERROR bits */
460 outb(dma_stat | 6, hwif->dma_status);
461 /* and free any DMA resources */
462 ide_destroy_dmatable(drive);
463 /* verify good DMA status */
464 return (dma_stat & 7) != 4;
465 }
466
467 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
468 {
469 u8 mrdmode = 0;
470
471 if (dev->device == PCI_DEVICE_ID_CMD_646) {
472 u8 rev = 0;
473
474 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
475
476 switch (rev) {
477 case 0x07:
478 case 0x05:
479 printk("%s: UltraDMA capable", name);
480 break;
481 case 0x03:
482 default:
483 printk("%s: MultiWord DMA force limited", name);
484 break;
485 case 0x01:
486 printk("%s: MultiWord DMA limited, "
487 "IRQ workaround enabled\n", name);
488 break;
489 }
490 }
491
492 /* Set a good latency timer and cache line size value. */
493 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
494 /* FIXME: pci_set_master() to ensure a good latency timer value */
495
496 /*
497 * Enable interrupts, select MEMORY READ LINE for reads.
498 *
499 * NOTE: although not mentioned in the PCI0646U specs,
500 * bits 0-1 are write only and won't be read back as
501 * set or not -- PCI0646U2 specs clarify this point.
502 */
503 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
504 mrdmode &= ~0x30;
505 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
506
507 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
508
509 cmd_devs[n_cmd_devs++] = dev;
510
511 if (!cmd64x_proc) {
512 cmd64x_proc = 1;
513 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
514 }
515 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */
516
517 return 0;
518 }
519
520 static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
521 {
522 struct pci_dev *dev = hwif->pci_dev;
523 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
524
525 switch (dev->device) {
526 case PCI_DEVICE_ID_CMD_648:
527 case PCI_DEVICE_ID_CMD_649:
528 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
529 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
530 default:
531 return ATA_CBL_PATA40;
532 }
533 }
534
535 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
536 {
537 struct pci_dev *dev = hwif->pci_dev;
538 u8 rev = 0;
539
540 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
541
542 hwif->tuneproc = &cmd64x_tune_drive;
543 hwif->speedproc = &cmd64x_tune_chipset;
544
545 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
546
547 if (!hwif->dma_base)
548 return;
549
550 hwif->atapi_dma = 1;
551 hwif->mwdma_mask = 0x07;
552 hwif->ultra_mask = hwif->cds->udma_mask;
553
554 /*
555 * UltraDMA only supported on PCI646U and PCI646U2, which
556 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
557 * Actually, although the CMD tech support people won't
558 * tell me the details, the 0x03 revision cannot support
559 * UDMA correctly without hardware modifications, and even
560 * then it only works with Quantum disks due to some
561 * hold time assumptions in the 646U part which are fixed
562 * in the 646U2.
563 *
564 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
565 */
566 if (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 5)
567 hwif->ultra_mask = 0x00;
568
569 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
570
571 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
572 hwif->cbl = ata66_cmd64x(hwif);
573
574 switch (dev->device) {
575 case PCI_DEVICE_ID_CMD_648:
576 case PCI_DEVICE_ID_CMD_649:
577 alt_irq_bits:
578 hwif->ide_dma_end = &cmd648_ide_dma_end;
579 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
580 break;
581 case PCI_DEVICE_ID_CMD_646:
582 hwif->chipset = ide_cmd646;
583 if (rev == 0x01) {
584 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
585 break;
586 } else if (rev >= 0x03)
587 goto alt_irq_bits;
588 /* fall thru */
589 default:
590 hwif->ide_dma_end = &cmd64x_ide_dma_end;
591 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
592 break;
593 }
594
595 if (!noautodma)
596 hwif->autodma = 1;
597 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
598 }
599
600 static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
601 {
602 return ide_setup_pci_device(dev, d);
603 }
604
605 static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
606 {
607 u8 rev = 0;
608
609 /*
610 * The original PCI0646 didn't have the primary channel enable bit,
611 * it appeared starting with PCI0646U (i.e. revision ID 3).
612 */
613 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
614 if (rev < 3)
615 d->enablebits[0].reg = 0;
616
617 return ide_setup_pci_device(dev, d);
618 }
619
620 static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
621 { /* 0 */
622 .name = "CMD643",
623 .init_setup = init_setup_cmd64x,
624 .init_chipset = init_chipset_cmd64x,
625 .init_hwif = init_hwif_cmd64x,
626 .channels = 2,
627 .autodma = AUTODMA,
628 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
629 .bootable = ON_BOARD,
630 .udma_mask = 0x00, /* no udma */
631 },{ /* 1 */
632 .name = "CMD646",
633 .init_setup = init_setup_cmd646,
634 .init_chipset = init_chipset_cmd64x,
635 .init_hwif = init_hwif_cmd64x,
636 .channels = 2,
637 .autodma = AUTODMA,
638 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
639 .bootable = ON_BOARD,
640 .udma_mask = 0x07, /* udma0-2 */
641 },{ /* 2 */
642 .name = "CMD648",
643 .init_setup = init_setup_cmd64x,
644 .init_chipset = init_chipset_cmd64x,
645 .init_hwif = init_hwif_cmd64x,
646 .channels = 2,
647 .autodma = AUTODMA,
648 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
649 .bootable = ON_BOARD,
650 .udma_mask = 0x1f, /* udma0-4 */
651 },{ /* 3 */
652 .name = "CMD649",
653 .init_setup = init_setup_cmd64x,
654 .init_chipset = init_chipset_cmd64x,
655 .init_hwif = init_hwif_cmd64x,
656 .channels = 2,
657 .autodma = AUTODMA,
658 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
659 .bootable = ON_BOARD,
660 .udma_mask = 0x3f, /* udma0-5 */
661 }
662 };
663
664 /*
665 * We may have to modify enablebits for PCI0646, so we'd better pass
666 * a local copy of the ide_pci_device_t structure down the call chain...
667 */
668 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
669 {
670 ide_pci_device_t d = cmd64x_chipsets[id->driver_data];
671
672 return d.init_setup(dev, &d);
673 }
674
675 static struct pci_device_id cmd64x_pci_tbl[] = {
676 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
677 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
678 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
679 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
680 { 0, },
681 };
682 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
683
684 static struct pci_driver driver = {
685 .name = "CMD64x_IDE",
686 .id_table = cmd64x_pci_tbl,
687 .probe = cmd64x_init_one,
688 };
689
690 static int __init cmd64x_ide_init(void)
691 {
692 return ide_pci_register_driver(&driver);
693 }
694
695 module_init(cmd64x_ide_init);
696
697 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
698 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
699 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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