drivers/ide/pci/cs5530.c

   1 /*
   2  * linux/drivers/ide/pci/cs5530.c               Version 0.74    Jul 28 2007
   3  *
   4  * Copyright (C) 2000                   Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2000                   Mark Lord <mlord@pobox.com>
   6  * Copyright (C) 2007                   Bartlomiej Zolnierkiewicz
   7  *
   8  * May be copied or modified under the terms of the GNU General Public License
   9  *
  10  * Development of this chipset driver was funded
  11  * by the nice folks at National Semiconductor.
  12  *
  13  * Documentation:
  14  *      CS5530 documentation available from National Semiconductor.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/timer.h>
  22 #include <linux/mm.h>
  23 #include <linux/ioport.h>
  24 #include <linux/blkdev.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/init.h>
  29 #include <linux/ide.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 /*
  34  * Here are the standard PIO mode 0-4 timings for each "format".
  35  * Format-0 uses fast data reg timings, with slower command reg timings.
  36  * Format-1 uses fast timings for all registers, but won't work with all drives.
  37  */
  38 static unsigned int cs5530_pio_timings[2][5] = {
  39         {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
  40         {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
  41 };
  42
  43 /*
  44  * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
  45  */
  46 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
  47 #define CS5530_BASEREG(hwif)    (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
  48
  49 /**
  50  *      cs5530_set_pio_mode     -       set host controller for PIO mode
  51  *      @drive: drive
  52  *      @pio: PIO mode number
  53  *
  54  *      Handles setting of PIO mode for the chipset.
  55  *
  56  *      The init_hwif_cs5530() routine guarantees that all drives
  57  *      will have valid default PIO timings set up before we get here.
  58  */
  59
  60 static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
  61 {
  62         unsigned long basereg = CS5530_BASEREG(drive->hwif);
  63         unsigned int format = (inl(basereg + 4) >> 31) & 1;
  64
  65         outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
  66 }
  67
  68 /**
  69  *      cs5530_udma_filter      -       UDMA filter
  70  *      @drive: drive
  71  *
  72  *      cs5530_udma_filter() does UDMA mask filtering for the given drive
  73  *      taking into the consideration capabilities of the mate device.
  74  *
  75  *      The CS5530 specifies that two drives sharing a cable cannot mix
  76  *      UDMA/MDMA.  It has to be one or the other, for the pair, though
  77  *      different timings can still be chosen for each drive.  We could
  78  *      set the appropriate timing bits on the fly, but that might be
  79  *      a bit confusing.  So, for now we statically handle this requirement
  80  *      by looking at our mate drive to see what it is capable of, before
  81  *      choosing a mode for our own drive.
  82  *
  83  *      Note: This relies on the fact we never fail from UDMA to MWDMA2
  84  *      but instead drop to PIO.
  85  */
  86
  87 static u8 cs5530_udma_filter(ide_drive_t *drive)
  88 {
  89         ide_hwif_t *hwif = drive->hwif;
  90         ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
  91         struct hd_driveid *mateid = mate->id;
  92         u8 mask = hwif->ultra_mask;
  93
  94         if (mate->present == 0)
  95                 goto out;
  96
  97         if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
  98                 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
  99                         goto out;
 100                 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
 101                         mask = 0;
 102         }
 103 out:
 104         return mask;
 105 }
 106
 107 /**
 108  *      cs5530_config_dma       -       set DMA/UDMA mode
 109  *      @drive: drive to tune
 110  *
 111  *      cs5530_config_dma() handles setting of DMA/UDMA mode
 112  *      for both the chipset and drive.
 113  */
 114
 115 static int cs5530_config_dma(ide_drive_t *drive)
 116 {
 117         if (ide_tune_dma(drive))
 118                 return 0;
 119
 120         return 1;
 121 }
 122
 123 static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
 124 {
 125         unsigned long basereg;
 126         unsigned int reg, timings = 0;
 127
 128         switch (mode) {
 129                 case XFER_UDMA_0:       timings = 0x00921250; break;
 130                 case XFER_UDMA_1:       timings = 0x00911140; break;
 131                 case XFER_UDMA_2:       timings = 0x00911030; break;
 132                 case XFER_MW_DMA_0:     timings = 0x00077771; break;
 133                 case XFER_MW_DMA_1:     timings = 0x00012121; break;
 134                 case XFER_MW_DMA_2:     timings = 0x00002020; break;
 135                 default:
 136                         BUG();
 137                         break;
 138         }
 139         basereg = CS5530_BASEREG(drive->hwif);
 140         reg = inl(basereg + 4);                 /* get drive0 config register */
 141         timings |= reg & 0x80000000;            /* preserve PIO format bit */
 142         if ((drive-> dn & 1) == 0) {            /* are we configuring drive0? */
 143                 outl(timings, basereg + 4);     /* write drive0 config register */
 144         } else {
 145                 if (timings & 0x00100000)
 146                         reg |=  0x00100000;     /* enable UDMA timings for both drives */
 147                 else
 148                         reg &= ~0x00100000;     /* disable UDMA timings for both drives */
 149                 outl(reg, basereg + 4);         /* write drive0 config register */
 150                 outl(timings, basereg + 12);    /* write drive1 config register */
 151         }
 152 }
 153
 154 /**
 155  *      init_chipset_5530       -       set up 5530 bridge
 156  *      @dev: PCI device
 157  *      @name: device name
 158  *
 159  *      Initialize the cs5530 bridge for reliable IDE DMA operation.
 160  */
 161
 162 static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
 163 {
 164         struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
 165         unsigned long flags;
 166
 167         if (pci_resource_start(dev, 4) == 0)
 168                 return -EFAULT;
 169
 170         dev = NULL;
 171         while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
 172                 switch (dev->device) {
 173                         case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
 174                                 master_0 = pci_dev_get(dev);
 175                                 break;
 176                         case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
 177                                 cs5530_0 = pci_dev_get(dev);
 178                                 break;
 179                 }
 180         }
 181         if (!master_0) {
 182                 printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
 183                 goto out;
 184         }
 185         if (!cs5530_0) {
 186                 printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
 187                 goto out;
 188         }
 189
 190         spin_lock_irqsave(&ide_lock, flags);
 191                 /* all CPUs (there should only be one CPU with this chipset) */
 192
 193         /*
 194          * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
 195          * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
 196          */
 197
 198         pci_set_master(cs5530_0);
 199         pci_try_set_mwi(cs5530_0);
 200
 201         /*
 202          * Set PCI CacheLineSize to 16-bytes:
 203          * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
 204          */
 205
 206         pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
 207
 208         /*
 209          * Disable trapping of UDMA register accesses (Win98 hack):
 210          * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
 211          */
 212
 213         pci_write_config_word(cs5530_0, 0xd0, 0x5006);
 214
 215         /*
 216          * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
 217          * The other settings are what is necessary to get the register
 218          * into a sane state for IDE DMA operation.
 219          */
 220
 221         pci_write_config_byte(master_0, 0x40, 0x1e);
 222
 223         /*
 224          * Set max PCI burst size (16-bytes seems to work best):
 225          *         16bytes: set bit-1 at 0x41 (reg value of 0x16)
 226          *      all others: clear bit-1 at 0x41, and do:
 227          *        128bytes: OR 0x00 at 0x41
 228          *        256bytes: OR 0x04 at 0x41
 229          *        512bytes: OR 0x08 at 0x41
 230          *       1024bytes: OR 0x0c at 0x41
 231          */
 232
 233         pci_write_config_byte(master_0, 0x41, 0x14);
 234
 235         /*
 236          * These settings are necessary to get the chip
 237          * into a sane state for IDE DMA operation.
 238          */
 239
 240         pci_write_config_byte(master_0, 0x42, 0x00);
 241         pci_write_config_byte(master_0, 0x43, 0xc1);
 242
 243         spin_unlock_irqrestore(&ide_lock, flags);
 244
 245 out:
 246         pci_dev_put(master_0);
 247         pci_dev_put(cs5530_0);
 248         return 0;
 249 }
 250
 251 /**
 252  *      init_hwif_cs5530        -       initialise an IDE channel
 253  *      @hwif: IDE to initialize
 254  *
 255  *      This gets invoked by the IDE driver once for each channel. It
 256  *      performs channel-specific pre-initialization before drive probing.
 257  */
 258
 259 static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
 260 {
 261         unsigned long basereg;
 262         u32 d0_timings;
 263         hwif->autodma = 0;
 264
 265         if (hwif->mate)
 266                 hwif->serialized = hwif->mate->serialized = 1;
 267
 268         hwif->set_pio_mode = &cs5530_set_pio_mode;
 269         hwif->set_dma_mode = &cs5530_set_dma_mode;
 270
 271         basereg = CS5530_BASEREG(hwif);
 272         d0_timings = inl(basereg + 0);
 273         if (CS5530_BAD_PIO(d0_timings)) {
 274                 /* PIO timings not initialized? */
 275                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
 276                 if (!hwif->drives[0].autotune)
 277                         hwif->drives[0].autotune = 1;
 278                         /* needs autotuning later */
 279         }
 280         if (CS5530_BAD_PIO(inl(basereg + 8))) {
 281                 /* PIO timings not initialized? */
 282                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
 283                 if (!hwif->drives[1].autotune)
 284                         hwif->drives[1].autotune = 1;
 285                         /* needs autotuning later */
 286         }
 287
 288         if (hwif->dma_base == 0)
 289                 return;
 290
 291         hwif->atapi_dma = 1;
 292         hwif->ultra_mask = 0x07;
 293         hwif->mwdma_mask = 0x07;
 294
 295         hwif->udma_filter = cs5530_udma_filter;
 296         hwif->ide_dma_check = &cs5530_config_dma;
 297         if (!noautodma)
 298                 hwif->autodma = 1;
 299         hwif->drives[0].autodma = hwif->autodma;
 300         hwif->drives[1].autodma = hwif->autodma;
 301 }
 302
 303 static ide_pci_device_t cs5530_chipset __devinitdata = {
 304         .name           = "CS5530",
 305         .init_chipset   = init_chipset_cs5530,
 306         .init_hwif      = init_hwif_cs5530,
 307         .autodma        = AUTODMA,
 308         .bootable       = ON_BOARD,
 309         .pio_mask       = ATA_PIO4,
 310         .host_flags     = IDE_HFLAG_POST_SET_MODE,
 311 };
 312
 313 static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 314 {
 315         return ide_setup_pci_device(dev, &cs5530_chipset);
 316 }
 317
 318 static struct pci_device_id cs5530_pci_tbl[] = {
 319         { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 320         { 0, },
 321 };
 322 MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
 323
 324 static struct pci_driver driver = {
 325         .name           = "CS5530 IDE",
 326         .id_table       = cs5530_pci_tbl,
 327         .probe          = cs5530_init_one,
 328 };
 329
 330 static int __init cs5530_ide_init(void)
 331 {
 332         return ide_pci_register_driver(&driver);
 333 }
 334
 335 module_init(cs5530_ide_init);
 336
 337 MODULE_AUTHOR("Mark Lord");
 338 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
 339 MODULE_LICENSE("GPL");