drivers/ide/pci/cs5530.c

   1 /*
   2  * linux/drivers/ide/pci/cs5530.c               Version 0.77    Sep 24 2007
   3  *
   4  * Copyright (C) 2000                   Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2000                   Mark Lord <mlord@pobox.com>
   6  * Copyright (C) 2007                   Bartlomiej Zolnierkiewicz
   7  *
   8  * May be copied or modified under the terms of the GNU General Public License
   9  *
  10  * Development of this chipset driver was funded
  11  * by the nice folks at National Semiconductor.
  12  *
  13  * Documentation:
  14  *      CS5530 documentation available from National Semiconductor.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/timer.h>
  22 #include <linux/mm.h>
  23 #include <linux/ioport.h>
  24 #include <linux/blkdev.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/init.h>
  29 #include <linux/ide.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 /*
  34  * Here are the standard PIO mode 0-4 timings for each "format".
  35  * Format-0 uses fast data reg timings, with slower command reg timings.
  36  * Format-1 uses fast timings for all registers, but won't work with all drives.
  37  */
  38 static unsigned int cs5530_pio_timings[2][5] = {
  39         {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
  40         {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
  41 };
  42
  43 /*
  44  * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
  45  */
  46 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
  47 #define CS5530_BASEREG(hwif)    (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
  48
  49 /**
  50  *      cs5530_set_pio_mode     -       set host controller for PIO mode
  51  *      @drive: drive
  52  *      @pio: PIO mode number
  53  *
  54  *      Handles setting of PIO mode for the chipset.
  55  *
  56  *      The init_hwif_cs5530() routine guarantees that all drives
  57  *      will have valid default PIO timings set up before we get here.
  58  */
  59
  60 static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
  61 {
  62         unsigned long basereg = CS5530_BASEREG(drive->hwif);
  63         unsigned int format = (inl(basereg + 4) >> 31) & 1;
  64
  65         outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
  66 }
  67
  68 /**
  69  *      cs5530_udma_filter      -       UDMA filter
  70  *      @drive: drive
  71  *
  72  *      cs5530_udma_filter() does UDMA mask filtering for the given drive
  73  *      taking into the consideration capabilities of the mate device.
  74  *
  75  *      The CS5530 specifies that two drives sharing a cable cannot mix
  76  *      UDMA/MDMA.  It has to be one or the other, for the pair, though
  77  *      different timings can still be chosen for each drive.  We could
  78  *      set the appropriate timing bits on the fly, but that might be
  79  *      a bit confusing.  So, for now we statically handle this requirement
  80  *      by looking at our mate drive to see what it is capable of, before
  81  *      choosing a mode for our own drive.
  82  *
  83  *      Note: This relies on the fact we never fail from UDMA to MWDMA2
  84  *      but instead drop to PIO.
  85  */
  86
  87 static u8 cs5530_udma_filter(ide_drive_t *drive)
  88 {
  89         ide_hwif_t *hwif = drive->hwif;
  90         ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
  91         struct hd_driveid *mateid = mate->id;
  92         u8 mask = hwif->ultra_mask;
  93
  94         if (mate->present == 0)
  95                 goto out;
  96
  97         if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
  98                 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
  99                         goto out;
 100                 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
 101                         mask = 0;
 102         }
 103 out:
 104         return mask;
 105 }
 106
 107 static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
 108 {
 109         unsigned long basereg;
 110         unsigned int reg, timings = 0;
 111
 112         switch (mode) {
 113                 case XFER_UDMA_0:       timings = 0x00921250; break;
 114                 case XFER_UDMA_1:       timings = 0x00911140; break;
 115                 case XFER_UDMA_2:       timings = 0x00911030; break;
 116                 case XFER_MW_DMA_0:     timings = 0x00077771; break;
 117                 case XFER_MW_DMA_1:     timings = 0x00012121; break;
 118                 case XFER_MW_DMA_2:     timings = 0x00002020; break;
 119                 default:
 120                         return;
 121         }
 122         basereg = CS5530_BASEREG(drive->hwif);
 123         reg = inl(basereg + 4);                 /* get drive0 config register */
 124         timings |= reg & 0x80000000;            /* preserve PIO format bit */
 125         if ((drive-> dn & 1) == 0) {            /* are we configuring drive0? */
 126                 outl(timings, basereg + 4);     /* write drive0 config register */
 127         } else {
 128                 if (timings & 0x00100000)
 129                         reg |=  0x00100000;     /* enable UDMA timings for both drives */
 130                 else
 131                         reg &= ~0x00100000;     /* disable UDMA timings for both drives */
 132                 outl(reg, basereg + 4);         /* write drive0 config register */
 133                 outl(timings, basereg + 12);    /* write drive1 config register */
 134         }
 135 }
 136
 137 /**
 138  *      init_chipset_5530       -       set up 5530 bridge
 139  *      @dev: PCI device
 140  *      @name: device name
 141  *
 142  *      Initialize the cs5530 bridge for reliable IDE DMA operation.
 143  */
 144
 145 static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
 146 {
 147         struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
 148
 149         if (pci_resource_start(dev, 4) == 0)
 150                 return -EFAULT;
 151
 152         dev = NULL;
 153         while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
 154                 switch (dev->device) {
 155                         case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
 156                                 master_0 = pci_dev_get(dev);
 157                                 break;
 158                         case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
 159                                 cs5530_0 = pci_dev_get(dev);
 160                                 break;
 161                 }
 162         }
 163         if (!master_0) {
 164                 printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
 165                 goto out;
 166         }
 167         if (!cs5530_0) {
 168                 printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
 169                 goto out;
 170         }
 171
 172         /*
 173          * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
 174          * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
 175          */
 176
 177         pci_set_master(cs5530_0);
 178         pci_try_set_mwi(cs5530_0);
 179
 180         /*
 181          * Set PCI CacheLineSize to 16-bytes:
 182          * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
 183          */
 184
 185         pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
 186
 187         /*
 188          * Disable trapping of UDMA register accesses (Win98 hack):
 189          * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
 190          */
 191
 192         pci_write_config_word(cs5530_0, 0xd0, 0x5006);
 193
 194         /*
 195          * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
 196          * The other settings are what is necessary to get the register
 197          * into a sane state for IDE DMA operation.
 198          */
 199
 200         pci_write_config_byte(master_0, 0x40, 0x1e);
 201
 202         /*
 203          * Set max PCI burst size (16-bytes seems to work best):
 204          *         16bytes: set bit-1 at 0x41 (reg value of 0x16)
 205          *      all others: clear bit-1 at 0x41, and do:
 206          *        128bytes: OR 0x00 at 0x41
 207          *        256bytes: OR 0x04 at 0x41
 208          *        512bytes: OR 0x08 at 0x41
 209          *       1024bytes: OR 0x0c at 0x41
 210          */
 211
 212         pci_write_config_byte(master_0, 0x41, 0x14);
 213
 214         /*
 215          * These settings are necessary to get the chip
 216          * into a sane state for IDE DMA operation.
 217          */
 218
 219         pci_write_config_byte(master_0, 0x42, 0x00);
 220         pci_write_config_byte(master_0, 0x43, 0xc1);
 221
 222 out:
 223         pci_dev_put(master_0);
 224         pci_dev_put(cs5530_0);
 225         return 0;
 226 }
 227
 228 /**
 229  *      init_hwif_cs5530        -       initialise an IDE channel
 230  *      @hwif: IDE to initialize
 231  *
 232  *      This gets invoked by the IDE driver once for each channel. It
 233  *      performs channel-specific pre-initialization before drive probing.
 234  */
 235
 236 static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
 237 {
 238         unsigned long basereg;
 239         u32 d0_timings;
 240
 241         hwif->set_pio_mode = &cs5530_set_pio_mode;
 242         hwif->set_dma_mode = &cs5530_set_dma_mode;
 243
 244         basereg = CS5530_BASEREG(hwif);
 245         d0_timings = inl(basereg + 0);
 246         if (CS5530_BAD_PIO(d0_timings))
 247                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
 248         if (CS5530_BAD_PIO(inl(basereg + 8)))
 249                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
 250
 251         if (hwif->dma_base == 0)
 252                 return;
 253
 254         hwif->udma_filter = cs5530_udma_filter;
 255 }
 256
 257 static const struct ide_port_info cs5530_chipset __devinitdata = {
 258         .name           = "CS5530",
 259         .init_chipset   = init_chipset_cs5530,
 260         .init_hwif      = init_hwif_cs5530,
 261         .host_flags     = IDE_HFLAG_SERIALIZE |
 262                           IDE_HFLAG_POST_SET_MODE |
 263                           IDE_HFLAG_BOOTABLE,
 264         .pio_mask       = ATA_PIO4,
 265         .mwdma_mask     = ATA_MWDMA2,
 266         .udma_mask      = ATA_UDMA2,
 267 };
 268
 269 static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 270 {
 271         return ide_setup_pci_device(dev, &cs5530_chipset);
 272 }
 273
 274 static const struct pci_device_id cs5530_pci_tbl[] = {
 275         { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
 276         { 0, },
 277 };
 278 MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
 279
 280 static struct pci_driver driver = {
 281         .name           = "CS5530 IDE",
 282         .id_table       = cs5530_pci_tbl,
 283         .probe          = cs5530_init_one,
 284 };
 285
 286 static int __init cs5530_ide_init(void)
 287 {
 288         return ide_pci_register_driver(&driver);
 289 }
 290
 291 module_init(cs5530_ide_init);
 292
 293 MODULE_AUTHOR("Mark Lord");
 294 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
 295 MODULE_LICENSE("GPL");