2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
20 * Note that final HPT370 support was done by force extraction of GPL.
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * Alan Cox <alan@redhat.com>
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
120 #include <linux/types.h>
121 #include <linux/module.h>
122 #include <linux/kernel.h>
123 #include <linux/delay.h>
124 #include <linux/blkdev.h>
125 #include <linux/hdreg.h>
126 #include <linux/interrupt.h>
127 #include <linux/pci.h>
128 #include <linux/init.h>
129 #include <linux/ide.h>
131 #include <asm/uaccess.h>
134 /* various tuning parameters */
135 #define HPT_RESET_STATE_ENGINE
136 #undef HPT_DELAY_INTERRUPT
137 #define HPT_SERIALIZE_IO 0
139 static const char *quirk_drives
[] = {
140 "QUANTUM FIREBALLlct08 08",
141 "QUANTUM FIREBALLP KA6.4",
142 "QUANTUM FIREBALLP LM20.4",
143 "QUANTUM FIREBALLP LM20.5",
147 static const char *bad_ata100_5
[] = {
166 static const char *bad_ata66_4
[] = {
182 "MAXTOR STM3320620A",
186 static const char *bad_ata66_3
[] = {
191 static const char *bad_ata33
[] = {
192 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
193 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
194 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
196 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
197 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
198 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
202 static u8 xfer_speeds
[] = {
222 /* Key for bus clock timings
225 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
227 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
229 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
231 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
233 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
234 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
235 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
237 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
238 * task file register access.
241 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
246 static u32 forty_base_hpt36x
[] = {
247 /* XFER_UDMA_6 */ 0x900fd943,
248 /* XFER_UDMA_5 */ 0x900fd943,
249 /* XFER_UDMA_4 */ 0x900fd943,
250 /* XFER_UDMA_3 */ 0x900ad943,
251 /* XFER_UDMA_2 */ 0x900bd943,
252 /* XFER_UDMA_1 */ 0x9008d943,
253 /* XFER_UDMA_0 */ 0x9008d943,
255 /* XFER_MW_DMA_2 */ 0xa008d943,
256 /* XFER_MW_DMA_1 */ 0xa010d955,
257 /* XFER_MW_DMA_0 */ 0xa010d9fc,
259 /* XFER_PIO_4 */ 0xc008d963,
260 /* XFER_PIO_3 */ 0xc010d974,
261 /* XFER_PIO_2 */ 0xc010d997,
262 /* XFER_PIO_1 */ 0xc010d9c7,
263 /* XFER_PIO_0 */ 0xc018d9d9
266 static u32 thirty_three_base_hpt36x
[] = {
267 /* XFER_UDMA_6 */ 0x90c9a731,
268 /* XFER_UDMA_5 */ 0x90c9a731,
269 /* XFER_UDMA_4 */ 0x90c9a731,
270 /* XFER_UDMA_3 */ 0x90cfa731,
271 /* XFER_UDMA_2 */ 0x90caa731,
272 /* XFER_UDMA_1 */ 0x90cba731,
273 /* XFER_UDMA_0 */ 0x90c8a731,
275 /* XFER_MW_DMA_2 */ 0xa0c8a731,
276 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
277 /* XFER_MW_DMA_0 */ 0xa0c8a797,
279 /* XFER_PIO_4 */ 0xc0c8a731,
280 /* XFER_PIO_3 */ 0xc0c8a742,
281 /* XFER_PIO_2 */ 0xc0d0a753,
282 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
283 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
286 static u32 twenty_five_base_hpt36x
[] = {
287 /* XFER_UDMA_6 */ 0x90c98521,
288 /* XFER_UDMA_5 */ 0x90c98521,
289 /* XFER_UDMA_4 */ 0x90c98521,
290 /* XFER_UDMA_3 */ 0x90cf8521,
291 /* XFER_UDMA_2 */ 0x90cf8521,
292 /* XFER_UDMA_1 */ 0x90cb8521,
293 /* XFER_UDMA_0 */ 0x90cb8521,
295 /* XFER_MW_DMA_2 */ 0xa0ca8521,
296 /* XFER_MW_DMA_1 */ 0xa0ca8532,
297 /* XFER_MW_DMA_0 */ 0xa0ca8575,
299 /* XFER_PIO_4 */ 0xc0ca8521,
300 /* XFER_PIO_3 */ 0xc0ca8532,
301 /* XFER_PIO_2 */ 0xc0ca8542,
302 /* XFER_PIO_1 */ 0xc0d08572,
303 /* XFER_PIO_0 */ 0xc0d08585
307 /* These are the timing tables from the HighPoint open source drivers... */
308 static u32 thirty_three_base_hpt37x
[] = {
309 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
310 /* XFER_UDMA_5 */ 0x12446231,
311 /* XFER_UDMA_4 */ 0x12446231,
312 /* XFER_UDMA_3 */ 0x126c6231,
313 /* XFER_UDMA_2 */ 0x12486231,
314 /* XFER_UDMA_1 */ 0x124c6233,
315 /* XFER_UDMA_0 */ 0x12506297,
317 /* XFER_MW_DMA_2 */ 0x22406c31,
318 /* XFER_MW_DMA_1 */ 0x22406c33,
319 /* XFER_MW_DMA_0 */ 0x22406c97,
321 /* XFER_PIO_4 */ 0x06414e31,
322 /* XFER_PIO_3 */ 0x06414e42,
323 /* XFER_PIO_2 */ 0x06414e53,
324 /* XFER_PIO_1 */ 0x06814e93,
325 /* XFER_PIO_0 */ 0x06814ea7
328 static u32 fifty_base_hpt37x
[] = {
329 /* XFER_UDMA_6 */ 0x12848242,
330 /* XFER_UDMA_5 */ 0x12848242,
331 /* XFER_UDMA_4 */ 0x12ac8242,
332 /* XFER_UDMA_3 */ 0x128c8242,
333 /* XFER_UDMA_2 */ 0x120c8242,
334 /* XFER_UDMA_1 */ 0x12148254,
335 /* XFER_UDMA_0 */ 0x121882ea,
337 /* XFER_MW_DMA_2 */ 0x22808242,
338 /* XFER_MW_DMA_1 */ 0x22808254,
339 /* XFER_MW_DMA_0 */ 0x228082ea,
341 /* XFER_PIO_4 */ 0x0a81f442,
342 /* XFER_PIO_3 */ 0x0a81f443,
343 /* XFER_PIO_2 */ 0x0a81f454,
344 /* XFER_PIO_1 */ 0x0ac1f465,
345 /* XFER_PIO_0 */ 0x0ac1f48a
348 static u32 sixty_six_base_hpt37x
[] = {
349 /* XFER_UDMA_6 */ 0x1c869c62,
350 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
351 /* XFER_UDMA_4 */ 0x1c8a9c62,
352 /* XFER_UDMA_3 */ 0x1c8e9c62,
353 /* XFER_UDMA_2 */ 0x1c929c62,
354 /* XFER_UDMA_1 */ 0x1c9a9c62,
355 /* XFER_UDMA_0 */ 0x1c829c62,
357 /* XFER_MW_DMA_2 */ 0x2c829c62,
358 /* XFER_MW_DMA_1 */ 0x2c829c66,
359 /* XFER_MW_DMA_0 */ 0x2c829d2e,
361 /* XFER_PIO_4 */ 0x0c829c62,
362 /* XFER_PIO_3 */ 0x0c829c84,
363 /* XFER_PIO_2 */ 0x0c829ca6,
364 /* XFER_PIO_1 */ 0x0d029d26,
365 /* XFER_PIO_0 */ 0x0d029d5e
369 * The following are the new timing tables with PIO mode data/taskfile transfer
370 * overclocking fixed...
373 /* This table is taken from the HPT370 data manual rev. 1.02 */
374 static u32 thirty_three_base_hpt37x
[] = {
375 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
376 /* XFER_UDMA_5 */ 0x16455031,
377 /* XFER_UDMA_4 */ 0x16455031,
378 /* XFER_UDMA_3 */ 0x166d5031,
379 /* XFER_UDMA_2 */ 0x16495031,
380 /* XFER_UDMA_1 */ 0x164d5033,
381 /* XFER_UDMA_0 */ 0x16515097,
383 /* XFER_MW_DMA_2 */ 0x26515031,
384 /* XFER_MW_DMA_1 */ 0x26515033,
385 /* XFER_MW_DMA_0 */ 0x26515097,
387 /* XFER_PIO_4 */ 0x06515021,
388 /* XFER_PIO_3 */ 0x06515022,
389 /* XFER_PIO_2 */ 0x06515033,
390 /* XFER_PIO_1 */ 0x06915065,
391 /* XFER_PIO_0 */ 0x06d1508a
394 static u32 fifty_base_hpt37x
[] = {
395 /* XFER_UDMA_6 */ 0x1a861842,
396 /* XFER_UDMA_5 */ 0x1a861842,
397 /* XFER_UDMA_4 */ 0x1aae1842,
398 /* XFER_UDMA_3 */ 0x1a8e1842,
399 /* XFER_UDMA_2 */ 0x1a0e1842,
400 /* XFER_UDMA_1 */ 0x1a161854,
401 /* XFER_UDMA_0 */ 0x1a1a18ea,
403 /* XFER_MW_DMA_2 */ 0x2a821842,
404 /* XFER_MW_DMA_1 */ 0x2a821854,
405 /* XFER_MW_DMA_0 */ 0x2a8218ea,
407 /* XFER_PIO_4 */ 0x0a821842,
408 /* XFER_PIO_3 */ 0x0a821843,
409 /* XFER_PIO_2 */ 0x0a821855,
410 /* XFER_PIO_1 */ 0x0ac218a8,
411 /* XFER_PIO_0 */ 0x0b02190c
414 static u32 sixty_six_base_hpt37x
[] = {
415 /* XFER_UDMA_6 */ 0x1c86fe62,
416 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
417 /* XFER_UDMA_4 */ 0x1c8afe62,
418 /* XFER_UDMA_3 */ 0x1c8efe62,
419 /* XFER_UDMA_2 */ 0x1c92fe62,
420 /* XFER_UDMA_1 */ 0x1c9afe62,
421 /* XFER_UDMA_0 */ 0x1c82fe62,
423 /* XFER_MW_DMA_2 */ 0x2c82fe62,
424 /* XFER_MW_DMA_1 */ 0x2c82fe66,
425 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
427 /* XFER_PIO_4 */ 0x0c82fe62,
428 /* XFER_PIO_3 */ 0x0c82fe84,
429 /* XFER_PIO_2 */ 0x0c82fea6,
430 /* XFER_PIO_1 */ 0x0d02ff26,
431 /* XFER_PIO_0 */ 0x0d42ff7f
435 #define HPT366_DEBUG_DRIVE_INFO 0
436 #define HPT371_ALLOW_ATA133_6 1
437 #define HPT302_ALLOW_ATA133_6 1
438 #define HPT372_ALLOW_ATA133_6 1
439 #define HPT370_ALLOW_ATA100_5 0
440 #define HPT366_ALLOW_ATA66_4 1
441 #define HPT366_ALLOW_ATA66_3 1
442 #define HPT366_MAX_DEVS 8
444 /* Supported ATA clock frequencies */
458 u32
*clock_table
[NUM_ATA_CLOCKS
];
462 * Hold all the HighPoint chip information in one place.
466 char *chip_name
; /* Chip name */
467 u8 chip_type
; /* Chip type */
468 u8 udma_mask
; /* Allowed UltraDMA modes mask. */
469 u8 dpll_clk
; /* DPLL clock in MHz */
470 u8 pci_clk
; /* PCI clock in MHz */
471 struct hpt_timings
*timings
; /* Chipset timing data */
472 u8 clock
; /* ATA clock selected */
475 /* Supported HighPoint chips */
490 static struct hpt_timings hpt36x_timings
= {
491 .pio_mask
= 0xc1f8ffff,
492 .dma_mask
= 0x303800ff,
493 .ultra_mask
= 0x30070000,
495 [ATA_CLOCK_25MHZ
] = twenty_five_base_hpt36x
,
496 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt36x
,
497 [ATA_CLOCK_40MHZ
] = forty_base_hpt36x
,
498 [ATA_CLOCK_50MHZ
] = NULL
,
499 [ATA_CLOCK_66MHZ
] = NULL
503 static struct hpt_timings hpt37x_timings
= {
504 .pio_mask
= 0xcfc3ffff,
505 .dma_mask
= 0x31c001ff,
506 .ultra_mask
= 0x303c0000,
508 [ATA_CLOCK_25MHZ
] = NULL
,
509 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt37x
,
510 [ATA_CLOCK_40MHZ
] = NULL
,
511 [ATA_CLOCK_50MHZ
] = fifty_base_hpt37x
,
512 [ATA_CLOCK_66MHZ
] = sixty_six_base_hpt37x
516 static const struct hpt_info hpt36x __devinitdata
= {
517 .chip_name
= "HPT36x",
519 .udma_mask
= HPT366_ALLOW_ATA66_3
? (HPT366_ALLOW_ATA66_4
? ATA_UDMA4
: ATA_UDMA3
) : ATA_UDMA2
,
520 .dpll_clk
= 0, /* no DPLL */
521 .timings
= &hpt36x_timings
524 static const struct hpt_info hpt370 __devinitdata
= {
525 .chip_name
= "HPT370",
527 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
529 .timings
= &hpt37x_timings
532 static const struct hpt_info hpt370a __devinitdata
= {
533 .chip_name
= "HPT370A",
534 .chip_type
= HPT370A
,
535 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
537 .timings
= &hpt37x_timings
540 static const struct hpt_info hpt374 __devinitdata
= {
541 .chip_name
= "HPT374",
543 .udma_mask
= ATA_UDMA5
,
545 .timings
= &hpt37x_timings
548 static const struct hpt_info hpt372 __devinitdata
= {
549 .chip_name
= "HPT372",
551 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
553 .timings
= &hpt37x_timings
556 static const struct hpt_info hpt372a __devinitdata
= {
557 .chip_name
= "HPT372A",
558 .chip_type
= HPT372A
,
559 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
561 .timings
= &hpt37x_timings
564 static const struct hpt_info hpt302 __devinitdata
= {
565 .chip_name
= "HPT302",
567 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
569 .timings
= &hpt37x_timings
572 static const struct hpt_info hpt371 __devinitdata
= {
573 .chip_name
= "HPT371",
575 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
577 .timings
= &hpt37x_timings
580 static const struct hpt_info hpt372n __devinitdata
= {
581 .chip_name
= "HPT372N",
582 .chip_type
= HPT372N
,
583 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
585 .timings
= &hpt37x_timings
588 static const struct hpt_info hpt302n __devinitdata
= {
589 .chip_name
= "HPT302N",
590 .chip_type
= HPT302N
,
591 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
593 .timings
= &hpt37x_timings
596 static const struct hpt_info hpt371n __devinitdata
= {
597 .chip_name
= "HPT371N",
598 .chip_type
= HPT371N
,
599 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
601 .timings
= &hpt37x_timings
604 static int check_in_drive_list(ide_drive_t
*drive
, const char **list
)
606 struct hd_driveid
*id
= drive
->id
;
609 if (!strcmp(*list
++,id
->model
))
615 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
616 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
619 static u8
hpt3xx_udma_filter(ide_drive_t
*drive
)
621 ide_hwif_t
*hwif
= HWIF(drive
);
622 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
623 struct hpt_info
*info
= pci_get_drvdata(dev
);
624 u8 mask
= hwif
->ultra_mask
;
626 switch (info
->chip_type
) {
628 if (!HPT366_ALLOW_ATA66_4
||
629 check_in_drive_list(drive
, bad_ata66_4
))
632 if (!HPT366_ALLOW_ATA66_3
||
633 check_in_drive_list(drive
, bad_ata66_3
))
637 if (!HPT370_ALLOW_ATA100_5
||
638 check_in_drive_list(drive
, bad_ata100_5
))
642 if (!HPT370_ALLOW_ATA100_5
||
643 check_in_drive_list(drive
, bad_ata100_5
))
649 if (ide_dev_is_sata(drive
->id
))
656 return check_in_drive_list(drive
, bad_ata33
) ? 0x00 : mask
;
659 static u8
hpt3xx_mdma_filter(ide_drive_t
*drive
)
661 ide_hwif_t
*hwif
= HWIF(drive
);
662 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
663 struct hpt_info
*info
= pci_get_drvdata(dev
);
665 switch (info
->chip_type
) {
670 if (ide_dev_is_sata(drive
->id
))
678 static u32
get_speed_setting(u8 speed
, struct hpt_info
*info
)
683 * Lookup the transfer mode table to get the index into
686 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
688 for (i
= 0; i
< ARRAY_SIZE(xfer_speeds
) - 1; i
++)
689 if (xfer_speeds
[i
] == speed
)
692 return info
->timings
->clock_table
[info
->clock
][i
];
695 static void hpt3xx_set_mode(ide_drive_t
*drive
, const u8 speed
)
697 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
698 struct hpt_info
*info
= pci_get_drvdata(dev
);
699 struct hpt_timings
*t
= info
->timings
;
700 u8 itr_addr
= 0x40 + (drive
->dn
* 4);
702 u32 new_itr
= get_speed_setting(speed
, info
);
703 u32 itr_mask
= speed
< XFER_MW_DMA_0
? t
->pio_mask
:
704 (speed
< XFER_UDMA_0
? t
->dma_mask
:
707 pci_read_config_dword(dev
, itr_addr
, &old_itr
);
708 new_itr
= (old_itr
& ~itr_mask
) | (new_itr
& itr_mask
);
710 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
711 * to avoid problems handling I/O errors later
713 new_itr
&= ~0xc0000000;
715 pci_write_config_dword(dev
, itr_addr
, new_itr
);
718 static void hpt3xx_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
720 hpt3xx_set_mode(drive
, XFER_PIO_0
+ pio
);
723 static void hpt3xx_quirkproc(ide_drive_t
*drive
)
725 struct hd_driveid
*id
= drive
->id
;
726 const char **list
= quirk_drives
;
729 if (strstr(id
->model
, *list
++)) {
730 drive
->quirk_list
= 1;
734 drive
->quirk_list
= 0;
737 static void hpt3xx_maskproc(ide_drive_t
*drive
, int mask
)
739 ide_hwif_t
*hwif
= HWIF(drive
);
740 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
741 struct hpt_info
*info
= pci_get_drvdata(dev
);
743 if (drive
->quirk_list
) {
744 if (info
->chip_type
>= HPT370
) {
747 pci_read_config_byte(dev
, 0x5a, &scr1
);
748 if (((scr1
& 0x10) >> 4) != mask
) {
753 pci_write_config_byte(dev
, 0x5a, scr1
);
757 disable_irq(hwif
->irq
);
759 enable_irq (hwif
->irq
);
762 outb(mask
? (drive
->ctl
| 2) : (drive
->ctl
& ~2),
763 hwif
->io_ports
[IDE_CONTROL_OFFSET
]);
767 * This is specific to the HPT366 UDMA chipset
768 * by HighPoint|Triones Technologies, Inc.
770 static void hpt366_dma_lost_irq(ide_drive_t
*drive
)
772 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
773 u8 mcr1
= 0, mcr3
= 0, scr1
= 0;
775 pci_read_config_byte(dev
, 0x50, &mcr1
);
776 pci_read_config_byte(dev
, 0x52, &mcr3
);
777 pci_read_config_byte(dev
, 0x5a, &scr1
);
778 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
779 drive
->name
, __FUNCTION__
, mcr1
, mcr3
, scr1
);
781 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
782 ide_dma_lost_irq(drive
);
785 static void hpt370_clear_engine(ide_drive_t
*drive
)
787 ide_hwif_t
*hwif
= HWIF(drive
);
788 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
790 pci_write_config_byte(dev
, hwif
->select_data
, 0x37);
794 static void hpt370_irq_timeout(ide_drive_t
*drive
)
796 ide_hwif_t
*hwif
= HWIF(drive
);
797 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
801 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
802 printk(KERN_DEBUG
"%s: %d bytes in FIFO\n", drive
->name
, bfifo
& 0x1ff);
804 /* get DMA command mode */
805 dma_cmd
= inb(hwif
->dma_command
);
807 outb(dma_cmd
& ~0x1, hwif
->dma_command
);
808 hpt370_clear_engine(drive
);
811 static void hpt370_ide_dma_start(ide_drive_t
*drive
)
813 #ifdef HPT_RESET_STATE_ENGINE
814 hpt370_clear_engine(drive
);
816 ide_dma_start(drive
);
819 static int hpt370_ide_dma_end(ide_drive_t
*drive
)
821 ide_hwif_t
*hwif
= HWIF(drive
);
822 u8 dma_stat
= inb(hwif
->dma_status
);
824 if (dma_stat
& 0x01) {
827 dma_stat
= inb(hwif
->dma_status
);
829 hpt370_irq_timeout(drive
);
831 return __ide_dma_end(drive
);
834 static void hpt370_dma_timeout(ide_drive_t
*drive
)
836 hpt370_irq_timeout(drive
);
837 ide_dma_timeout(drive
);
840 /* returns 1 if DMA IRQ issued, 0 otherwise */
841 static int hpt374_ide_dma_test_irq(ide_drive_t
*drive
)
843 ide_hwif_t
*hwif
= HWIF(drive
);
844 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
848 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
850 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
854 dma_stat
= inb(hwif
->dma_status
);
855 /* return 1 if INTR asserted */
859 if (!drive
->waiting_for_dma
)
860 printk(KERN_WARNING
"%s: (%s) called while not waiting\n",
861 drive
->name
, __FUNCTION__
);
865 static int hpt374_ide_dma_end(ide_drive_t
*drive
)
867 ide_hwif_t
*hwif
= HWIF(drive
);
868 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
869 u8 mcr
= 0, mcr_addr
= hwif
->select_data
;
870 u8 bwsr
= 0, mask
= hwif
->channel
? 0x02 : 0x01;
872 pci_read_config_byte(dev
, 0x6a, &bwsr
);
873 pci_read_config_byte(dev
, mcr_addr
, &mcr
);
875 pci_write_config_byte(dev
, mcr_addr
, mcr
| 0x30);
876 return __ide_dma_end(drive
);
880 * hpt3xxn_set_clock - perform clock switching dance
881 * @hwif: hwif to switch
882 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
884 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
887 static void hpt3xxn_set_clock(ide_hwif_t
*hwif
, u8 mode
)
889 unsigned long base
= hwif
->extra_base
;
890 u8 scr2
= inb(base
+ 0x6b);
892 if ((scr2
& 0x7f) == mode
)
895 /* Tristate the bus */
896 outb(0x80, base
+ 0x63);
897 outb(0x80, base
+ 0x67);
899 /* Switch clock and reset channels */
900 outb(mode
, base
+ 0x6b);
901 outb(0xc0, base
+ 0x69);
904 * Reset the state machines.
905 * NOTE: avoid accidentally enabling the disabled channels.
907 outb(inb(base
+ 0x60) | 0x32, base
+ 0x60);
908 outb(inb(base
+ 0x64) | 0x32, base
+ 0x64);
911 outb(0x00, base
+ 0x69);
913 /* Reconnect channels to bus */
914 outb(0x00, base
+ 0x63);
915 outb(0x00, base
+ 0x67);
919 * hpt3xxn_rw_disk - prepare for I/O
920 * @drive: drive for command
921 * @rq: block request structure
923 * This is called when a disk I/O is issued to HPT3xxN.
924 * We need it because of the clock switching.
927 static void hpt3xxn_rw_disk(ide_drive_t
*drive
, struct request
*rq
)
929 hpt3xxn_set_clock(HWIF(drive
), rq_data_dir(rq
) ? 0x23 : 0x21);
933 * hpt37x_calibrate_dpll - calibrate the DPLL
936 * Perform a calibration cycle on the DPLL.
937 * Returns 1 if this succeeds
939 static int __devinit
hpt37x_calibrate_dpll(struct pci_dev
*dev
, u16 f_low
, u16 f_high
)
941 u32 dpll
= (f_high
<< 16) | f_low
| 0x100;
945 pci_write_config_dword(dev
, 0x5c, dpll
);
947 /* Wait for oscillator ready */
948 for(i
= 0; i
< 0x5000; ++i
) {
950 pci_read_config_byte(dev
, 0x5b, &scr2
);
954 /* See if it stays ready (we'll just bail out if it's not yet) */
955 for(i
= 0; i
< 0x1000; ++i
) {
956 pci_read_config_byte(dev
, 0x5b, &scr2
);
957 /* DPLL destabilized? */
961 /* Turn off tuning, we have the DPLL set */
962 pci_read_config_dword (dev
, 0x5c, &dpll
);
963 pci_write_config_dword(dev
, 0x5c, (dpll
& ~0x100));
967 static unsigned int __devinit
init_chipset_hpt366(struct pci_dev
*dev
, const char *name
)
969 struct hpt_info
*info
= kmalloc(sizeof(struct hpt_info
), GFP_KERNEL
);
970 unsigned long io_base
= pci_resource_start(dev
, 4);
971 u8 pci_clk
, dpll_clk
= 0; /* PCI and DPLL clock in MHz */
973 enum ata_clock clock
;
976 printk(KERN_ERR
"%s: out of memory!\n", name
);
981 * Copy everything from a static "template" structure
982 * to just allocated per-chip hpt_info structure.
984 memcpy(info
, pci_get_drvdata(dev
), sizeof(struct hpt_info
));
985 chip_type
= info
->chip_type
;
987 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (L1_CACHE_BYTES
/ 4));
988 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x78);
989 pci_write_config_byte(dev
, PCI_MIN_GNT
, 0x08);
990 pci_write_config_byte(dev
, PCI_MAX_LAT
, 0x08);
993 * First, try to estimate the PCI clock frequency...
995 if (chip_type
>= HPT370
) {
1000 /* Interrupt force enable. */
1001 pci_read_config_byte(dev
, 0x5a, &scr1
);
1003 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
1006 * HighPoint does this for HPT372A.
1007 * NOTE: This register is only writeable via I/O space.
1009 if (chip_type
== HPT372A
)
1010 outb(0x0e, io_base
+ 0x9c);
1013 * Default to PCI clock. Make sure MA15/16 are set to output
1014 * to prevent drives having problems with 40-pin cables.
1016 pci_write_config_byte(dev
, 0x5b, 0x23);
1019 * We'll have to read f_CNT value in order to determine
1020 * the PCI clock frequency according to the following ratio:
1022 * f_CNT = Fpci * 192 / Fdpll
1024 * First try reading the register in which the HighPoint BIOS
1025 * saves f_CNT value before reprogramming the DPLL from its
1026 * default setting (which differs for the various chips).
1028 * NOTE: This register is only accessible via I/O space;
1029 * HPT374 BIOS only saves it for the function 0, so we have to
1030 * always read it from there -- no need to check the result of
1031 * pci_get_slot() for the function 0 as the whole device has
1032 * been already "pinned" (via function 1) in init_setup_hpt374()
1034 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1035 struct pci_dev
*dev1
= pci_get_slot(dev
->bus
,
1037 unsigned long io_base
= pci_resource_start(dev1
, 4);
1039 temp
= inl(io_base
+ 0x90);
1042 temp
= inl(io_base
+ 0x90);
1045 * In case the signature check fails, we'll have to
1046 * resort to reading the f_CNT register itself in hopes
1047 * that nobody has touched the DPLL yet...
1049 if ((temp
& 0xFFFFF000) != 0xABCDE000) {
1052 printk(KERN_WARNING
"%s: no clock data saved by BIOS\n",
1055 /* Calculate the average value of f_CNT. */
1056 for (temp
= i
= 0; i
< 128; i
++) {
1057 pci_read_config_word(dev
, 0x78, &f_cnt
);
1058 temp
+= f_cnt
& 0x1ff;
1063 f_cnt
= temp
& 0x1ff;
1065 dpll_clk
= info
->dpll_clk
;
1066 pci_clk
= (f_cnt
* dpll_clk
) / 192;
1068 /* Clamp PCI clock to bands. */
1071 else if(pci_clk
< 45)
1073 else if(pci_clk
< 55)
1078 printk(KERN_INFO
"%s: DPLL base: %d MHz, f_CNT: %d, "
1079 "assuming %d MHz PCI\n", name
, dpll_clk
, f_cnt
, pci_clk
);
1083 pci_read_config_dword(dev
, 0x40, &itr1
);
1085 /* Detect PCI clock by looking at cmd_high_time. */
1086 switch((itr1
>> 8) & 0x07) {
1100 /* Let's assume we'll use PCI clock for the ATA clock... */
1103 clock
= ATA_CLOCK_25MHZ
;
1107 clock
= ATA_CLOCK_33MHZ
;
1110 clock
= ATA_CLOCK_40MHZ
;
1113 clock
= ATA_CLOCK_50MHZ
;
1116 clock
= ATA_CLOCK_66MHZ
;
1121 * Only try the DPLL if we don't have a table for the PCI clock that
1122 * we are running at for HPT370/A, always use it for anything newer...
1124 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1125 * We also don't like using the DPLL because this causes glitches
1126 * on PRST-/SRST- when the state engine gets reset...
1128 if (chip_type
>= HPT374
|| info
->timings
->clock_table
[clock
] == NULL
) {
1129 u16 f_low
, delta
= pci_clk
< 50 ? 2 : 4;
1133 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1134 * supported/enabled, use 50 MHz DPLL clock otherwise...
1136 if (info
->udma_mask
== ATA_UDMA6
) {
1138 clock
= ATA_CLOCK_66MHZ
;
1139 } else if (dpll_clk
) { /* HPT36x chips don't have DPLL */
1141 clock
= ATA_CLOCK_50MHZ
;
1144 if (info
->timings
->clock_table
[clock
] == NULL
) {
1145 printk(KERN_ERR
"%s: unknown bus timing!\n", name
);
1150 /* Select the DPLL clock. */
1151 pci_write_config_byte(dev
, 0x5b, 0x21);
1154 * Adjust the DPLL based upon PCI clock, enable it,
1155 * and wait for stabilization...
1157 f_low
= (pci_clk
* 48) / dpll_clk
;
1159 for (adjust
= 0; adjust
< 8; adjust
++) {
1160 if(hpt37x_calibrate_dpll(dev
, f_low
, f_low
+ delta
))
1164 * See if it'll settle at a fractionally different clock
1167 f_low
-= adjust
>> 1;
1169 f_low
+= adjust
>> 1;
1172 printk(KERN_ERR
"%s: DPLL did not stabilize!\n", name
);
1177 printk("%s: using %d MHz DPLL clock\n", name
, dpll_clk
);
1179 /* Mark the fact that we're not using the DPLL. */
1182 printk("%s: using %d MHz PCI clock\n", name
, pci_clk
);
1185 /* Store the clock frequencies. */
1186 info
->dpll_clk
= dpll_clk
;
1187 info
->pci_clk
= pci_clk
;
1188 info
->clock
= clock
;
1190 /* Point to this chip's own instance of the hpt_info structure. */
1191 pci_set_drvdata(dev
, info
);
1193 if (chip_type
>= HPT370
) {
1197 * Reset the state engines.
1198 * NOTE: Avoid accidentally enabling the disabled channels.
1200 pci_read_config_byte (dev
, 0x50, &mcr1
);
1201 pci_read_config_byte (dev
, 0x54, &mcr4
);
1202 pci_write_config_byte(dev
, 0x50, (mcr1
| 0x32));
1203 pci_write_config_byte(dev
, 0x54, (mcr4
| 0x32));
1208 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1209 * the MISC. register to stretch the UltraDMA Tss timing.
1210 * NOTE: This register is only writeable via I/O space.
1212 if (chip_type
== HPT371N
&& clock
== ATA_CLOCK_66MHZ
)
1214 outb(inb(io_base
+ 0x9c) | 0x04, io_base
+ 0x9c);
1219 static u8 __devinit
hpt3xx_cable_detect(ide_hwif_t
*hwif
)
1221 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1222 struct hpt_info
*info
= pci_get_drvdata(dev
);
1223 u8 chip_type
= info
->chip_type
;
1224 u8 scr1
= 0, ata66
= hwif
->channel
? 0x01 : 0x02;
1227 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1228 * address lines to access an external EEPROM. To read valid
1229 * cable detect state the pins must be enabled as inputs.
1231 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1233 * HPT374 PCI function 1
1234 * - set bit 15 of reg 0x52 to enable TCBLID as input
1235 * - set bit 15 of reg 0x56 to enable FCBLID as input
1237 u8 mcr_addr
= hwif
->select_data
+ 2;
1240 pci_read_config_word(dev
, mcr_addr
, &mcr
);
1241 pci_write_config_word(dev
, mcr_addr
, (mcr
| 0x8000));
1242 /* now read cable id register */
1243 pci_read_config_byte(dev
, 0x5a, &scr1
);
1244 pci_write_config_word(dev
, mcr_addr
, mcr
);
1245 } else if (chip_type
>= HPT370
) {
1247 * HPT370/372 and 374 pcifn 0
1248 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1252 pci_read_config_byte(dev
, 0x5b, &scr2
);
1253 pci_write_config_byte(dev
, 0x5b, (scr2
& ~1));
1254 /* now read cable id register */
1255 pci_read_config_byte(dev
, 0x5a, &scr1
);
1256 pci_write_config_byte(dev
, 0x5b, scr2
);
1258 pci_read_config_byte(dev
, 0x5a, &scr1
);
1260 return (scr1
& ata66
) ? ATA_CBL_PATA40
: ATA_CBL_PATA80
;
1263 static void __devinit
init_hwif_hpt366(ide_hwif_t
*hwif
)
1265 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1266 struct hpt_info
*info
= pci_get_drvdata(dev
);
1267 int serialize
= HPT_SERIALIZE_IO
;
1268 u8 chip_type
= info
->chip_type
;
1269 u8 new_mcr
, old_mcr
= 0;
1271 /* Cache the channel's MISC. control registers' offset */
1272 hwif
->select_data
= hwif
->channel
? 0x54 : 0x50;
1275 * HPT3xxN chips have some complications:
1277 * - on 33 MHz PCI we must clock switch
1278 * - on 66 MHz PCI we must NOT use the PCI clock
1280 if (chip_type
>= HPT372N
&& info
->dpll_clk
&& info
->pci_clk
< 66) {
1282 * Clock is shared between the channels,
1283 * so we'll have to serialize them... :-(
1286 hwif
->rw_disk
= &hpt3xxn_rw_disk
;
1289 /* Serialize access to this device if needed */
1290 if (serialize
&& hwif
->mate
)
1291 hwif
->serialized
= hwif
->mate
->serialized
= 1;
1294 * Disable the "fast interrupt" prediction. Don't hold off
1295 * on interrupts. (== 0x01 despite what the docs say)
1297 pci_read_config_byte(dev
, hwif
->select_data
+ 1, &old_mcr
);
1299 if (info
->chip_type
>= HPT374
)
1300 new_mcr
= old_mcr
& ~0x07;
1301 else if (info
->chip_type
>= HPT370
) {
1305 #ifdef HPT_DELAY_INTERRUPT
1310 } else /* HPT366 and HPT368 */
1311 new_mcr
= old_mcr
& ~0x80;
1313 if (new_mcr
!= old_mcr
)
1314 pci_write_config_byte(dev
, hwif
->select_data
+ 1, new_mcr
);
1316 if (hwif
->dma_base
== 0)
1319 if (chip_type
>= HPT374
) {
1320 hwif
->ide_dma_test_irq
= &hpt374_ide_dma_test_irq
;
1321 hwif
->ide_dma_end
= &hpt374_ide_dma_end
;
1322 } else if (chip_type
>= HPT370
) {
1323 hwif
->dma_start
= &hpt370_ide_dma_start
;
1324 hwif
->ide_dma_end
= &hpt370_ide_dma_end
;
1325 hwif
->dma_timeout
= &hpt370_dma_timeout
;
1327 hwif
->dma_lost_irq
= &hpt366_dma_lost_irq
;
1330 static void __devinit
init_dma_hpt366(ide_hwif_t
*hwif
, unsigned long dmabase
)
1332 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1333 u8 masterdma
= 0, slavedma
= 0;
1334 u8 dma_new
= 0, dma_old
= 0;
1335 unsigned long flags
;
1337 dma_old
= inb(dmabase
+ 2);
1339 local_irq_save(flags
);
1342 pci_read_config_byte(dev
, hwif
->channel
? 0x4b : 0x43, &masterdma
);
1343 pci_read_config_byte(dev
, hwif
->channel
? 0x4f : 0x47, &slavedma
);
1345 if (masterdma
& 0x30) dma_new
|= 0x20;
1346 if ( slavedma
& 0x30) dma_new
|= 0x40;
1347 if (dma_new
!= dma_old
)
1348 outb(dma_new
, dmabase
+ 2);
1350 local_irq_restore(flags
);
1352 ide_setup_dma(hwif
, dmabase
);
1355 static void __devinit
hpt374_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1357 if (dev2
->irq
!= dev
->irq
) {
1358 /* FIXME: we need a core pci_set_interrupt() */
1359 dev2
->irq
= dev
->irq
;
1360 printk(KERN_INFO
"HPT374: PCI config space interrupt fixed\n");
1364 static void __devinit
hpt371_init(struct pci_dev
*dev
)
1369 * HPT371 chips physically have only one channel, the secondary one,
1370 * but the primary channel registers do exist! Go figure...
1371 * So, we manually disable the non-existing channel here
1372 * (if the BIOS hasn't done this already).
1374 pci_read_config_byte(dev
, 0x50, &mcr1
);
1376 pci_write_config_byte(dev
, 0x50, mcr1
& ~0x04);
1379 static int __devinit
hpt36x_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1381 u8 mcr1
= 0, pin1
= 0, pin2
= 0;
1384 * Now we'll have to force both channels enabled if
1385 * at least one of them has been enabled by BIOS...
1387 pci_read_config_byte(dev
, 0x50, &mcr1
);
1389 pci_write_config_byte(dev
, 0x50, mcr1
| 0x30);
1391 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin1
);
1392 pci_read_config_byte(dev2
, PCI_INTERRUPT_PIN
, &pin2
);
1394 if (pin1
!= pin2
&& dev
->irq
== dev2
->irq
) {
1395 printk(KERN_INFO
"HPT36x: onboard version of chipset, "
1396 "pin1=%d pin2=%d\n", pin1
, pin2
);
1403 #define IDE_HFLAGS_HPT3XX \
1404 (IDE_HFLAG_NO_ATAPI_DMA | \
1405 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
1406 IDE_HFLAG_OFF_BOARD)
1408 static const struct ide_port_ops hpt3xx_port_ops
= {
1409 .set_pio_mode
= hpt3xx_set_pio_mode
,
1410 .set_dma_mode
= hpt3xx_set_mode
,
1411 .quirkproc
= hpt3xx_quirkproc
,
1412 .maskproc
= hpt3xx_maskproc
,
1413 .mdma_filter
= hpt3xx_mdma_filter
,
1414 .udma_filter
= hpt3xx_udma_filter
,
1415 .cable_detect
= hpt3xx_cable_detect
,
1418 static const struct ide_port_info hpt366_chipsets
[] __devinitdata
= {
1421 .init_chipset
= init_chipset_hpt366
,
1422 .init_hwif
= init_hwif_hpt366
,
1423 .init_dma
= init_dma_hpt366
,
1425 * HPT36x chips have one channel per function and have
1426 * both channel enable bits located differently and visible
1427 * to both functions -- really stupid design decision... :-(
1428 * Bit 4 is for the primary channel, bit 5 for the secondary.
1430 .enablebits
= {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1432 .port_ops
= &hpt3xx_port_ops
,
1433 .host_flags
= IDE_HFLAGS_HPT3XX
| IDE_HFLAG_SINGLE
,
1434 .pio_mask
= ATA_PIO4
,
1435 .mwdma_mask
= ATA_MWDMA2
,
1438 .init_chipset
= init_chipset_hpt366
,
1439 .init_hwif
= init_hwif_hpt366
,
1440 .init_dma
= init_dma_hpt366
,
1441 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1443 .port_ops
= &hpt3xx_port_ops
,
1444 .host_flags
= IDE_HFLAGS_HPT3XX
,
1445 .pio_mask
= ATA_PIO4
,
1446 .mwdma_mask
= ATA_MWDMA2
,
1449 .init_chipset
= init_chipset_hpt366
,
1450 .init_hwif
= init_hwif_hpt366
,
1451 .init_dma
= init_dma_hpt366
,
1452 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1454 .port_ops
= &hpt3xx_port_ops
,
1455 .host_flags
= IDE_HFLAGS_HPT3XX
,
1456 .pio_mask
= ATA_PIO4
,
1457 .mwdma_mask
= ATA_MWDMA2
,
1460 .init_chipset
= init_chipset_hpt366
,
1461 .init_hwif
= init_hwif_hpt366
,
1462 .init_dma
= init_dma_hpt366
,
1463 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1465 .port_ops
= &hpt3xx_port_ops
,
1466 .host_flags
= IDE_HFLAGS_HPT3XX
,
1467 .pio_mask
= ATA_PIO4
,
1468 .mwdma_mask
= ATA_MWDMA2
,
1471 .init_chipset
= init_chipset_hpt366
,
1472 .init_hwif
= init_hwif_hpt366
,
1473 .init_dma
= init_dma_hpt366
,
1474 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1475 .udma_mask
= ATA_UDMA5
,
1477 .port_ops
= &hpt3xx_port_ops
,
1478 .host_flags
= IDE_HFLAGS_HPT3XX
,
1479 .pio_mask
= ATA_PIO4
,
1480 .mwdma_mask
= ATA_MWDMA2
,
1483 .init_chipset
= init_chipset_hpt366
,
1484 .init_hwif
= init_hwif_hpt366
,
1485 .init_dma
= init_dma_hpt366
,
1486 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1488 .port_ops
= &hpt3xx_port_ops
,
1489 .host_flags
= IDE_HFLAGS_HPT3XX
,
1490 .pio_mask
= ATA_PIO4
,
1491 .mwdma_mask
= ATA_MWDMA2
,
1496 * hpt366_init_one - called when an HPT366 is found
1497 * @dev: the hpt366 device
1498 * @id: the matching pci id
1500 * Called when the PCI registration layer (or the IDE initialization)
1501 * finds a device matching our IDE device tables.
1503 static int __devinit
hpt366_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1505 const struct hpt_info
*info
= NULL
;
1506 struct pci_dev
*dev2
= NULL
;
1507 struct ide_port_info d
;
1508 u8 idx
= id
->driver_data
;
1509 u8 rev
= dev
->revision
;
1511 if ((idx
== 0 || idx
== 4) && (PCI_FUNC(dev
->devfn
) & 1))
1519 switch (min_t(u8
, rev
, 6)) {
1520 case 3: info
= &hpt370
; break;
1521 case 4: info
= &hpt370a
; break;
1522 case 5: info
= &hpt372
; break;
1523 case 6: info
= &hpt372n
; break;
1529 info
= (rev
> 1) ? &hpt372n
: &hpt372a
;
1532 info
= (rev
> 1) ? &hpt302n
: &hpt302
;
1536 info
= (rev
> 1) ? &hpt371n
: &hpt371
;
1546 d
= hpt366_chipsets
[idx
];
1548 d
.name
= info
->chip_name
;
1549 d
.udma_mask
= info
->udma_mask
;
1551 pci_set_drvdata(dev
, (void *)info
);
1553 if (info
== &hpt36x
|| info
== &hpt374
)
1554 dev2
= pci_get_slot(dev
->bus
, dev
->devfn
+ 1);
1559 pci_set_drvdata(dev2
, (void *)info
);
1561 if (info
== &hpt374
)
1562 hpt374_init(dev
, dev2
);
1564 if (hpt36x_init(dev
, dev2
))
1565 d
.host_flags
&= ~IDE_HFLAG_NON_BOOTABLE
;
1568 ret
= ide_setup_pci_devices(dev
, dev2
, &d
);
1574 return ide_setup_pci_device(dev
, &d
);
1577 static const struct pci_device_id hpt366_pci_tbl
[] __devinitconst
= {
1578 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT366
), 0 },
1579 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372
), 1 },
1580 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT302
), 2 },
1581 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT371
), 3 },
1582 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT374
), 4 },
1583 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372N
), 5 },
1586 MODULE_DEVICE_TABLE(pci
, hpt366_pci_tbl
);
1588 static struct pci_driver driver
= {
1589 .name
= "HPT366_IDE",
1590 .id_table
= hpt366_pci_tbl
,
1591 .probe
= hpt366_init_one
,
1594 static int __init
hpt366_ide_init(void)
1596 return ide_pci_register_driver(&driver
);
1599 module_init(hpt366_ide_init
);
1601 MODULE_AUTHOR("Andre Hedrick");
1602 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1603 MODULE_LICENSE("GPL");