2 * Copyright (C) 2004 Red Hat <alan@redhat.com>
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 * May be copied or modified under the terms of the GNU General Public License
6 * Based in part on the ITE vendor provided SCSI driver.
8 * Documentation available from
9 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
10 * Some other documents are NDA.
12 * The ITE8212 isn't exactly a standard IDE controller. It has two
13 * modes. In pass through mode then it is an IDE controller. In its smart
14 * mode its actually quite a capable hardware raid controller disguised
15 * as an IDE controller. Smart mode only understands DMA read/write and
16 * identify, none of the fancier commands apply. The IT8211 is identical
17 * in other respects but lacks the raid mode.
20 * o Rev 0x10 also requires master/slave hold the same DMA timings and
21 * cannot do ATAPI MWDMA.
22 * o The identify data for raid volumes lacks CHS info (technically ok)
23 * but also fails to set the LBA28 and other bits. We fix these in
24 * the IDE probe quirk code.
25 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * raid then the controller firmware dies
27 * o Smart mode without RAID doesn't clear all the necessary identify
28 * bits to reduce the command set to the one used
30 * This has a few impacts on the driver
31 * - In pass through mode we do all the work you would expect
32 * - In smart mode the clocking set up is done by the controller generally
33 * but we must watch the other limits and filter.
34 * - There are a few extra vendor commands that actually talk to the
35 * controller but only work PIO with no IRQ.
37 * Vendor areas of the identify block in smart mode are used for the
38 * timing and policy set up. Each HDD in raid mode also has a serial
39 * block on the disk. The hardware extra commands are get/set chip status,
40 * rebuild, get rebuild status.
42 * In Linux the driver supports pass through mode as if the device was
43 * just another IDE controller. If the smart mode is running then
44 * volumes are managed by the controller firmware and each IDE "disk"
45 * is a raid volume. Even more cute - the controller can do automated
46 * hotplug and rebuild.
48 * The pass through controller itself is a little demented. It has a
49 * flaw that it has a single set of PIO/MWDMA timings per channel so
50 * non UDMA devices restrict each others performance. It also has a
51 * single clock source per channel so mixed UDMA100/133 performance
52 * isn't perfect and we have to pick a clock. Thankfully none of this
53 * matters in smart mode. ATAPI DMA is not currently supported.
55 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
58 * - ATAPI UDMA is ok but not MWDMA it seems
59 * - RAID configuration ioctls
60 * - Move to libata once it grows up
63 #include <linux/types.h>
64 #include <linux/module.h>
65 #include <linux/pci.h>
66 #include <linux/ide.h>
67 #include <linux/init.h>
69 #define DRV_NAME "it821x"
73 unsigned int smart
:1, /* Are we in smart raid mode */
74 timing10
:1; /* Rev 0x10 */
75 u8 clock_mode
; /* 0, ATA_50 or ATA_66 */
76 u8 want
[2][2]; /* Mode/Pri log for master slave */
77 /* We need these for switching the clock when DMA goes on/off
78 The high byte is the 66Mhz timing */
79 u16 pio
[2]; /* Cached PIO values */
80 u16 mwdma
[2]; /* Cached MWDMA values */
81 u16 udma
[2]; /* Cached UDMA values (per drive) */
92 * We allow users to force the card into non raid mode without
93 * flashing the alternative BIOS. This is also necessary right now
94 * for embedded platforms that cannot run a PC BIOS but are using this
98 static int it8212_noraid
;
101 * it821x_program - program the PIO/MWDMA registers
102 * @drive: drive to tune
103 * @timing: timing info
105 * Program the PIO/MWDMA timing for this channel according to the
109 static void it821x_program(ide_drive_t
*drive
, u16 timing
)
111 ide_hwif_t
*hwif
= drive
->hwif
;
112 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
113 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
114 int channel
= hwif
->channel
;
117 /* Program PIO/MWDMA timing bits */
118 if(itdev
->clock_mode
== ATA_66
)
121 conf
= timing
& 0xFF;
123 pci_write_config_byte(dev
, 0x54 + 4 * channel
, conf
);
127 * it821x_program_udma - program the UDMA registers
128 * @drive: drive to tune
129 * @timing: timing info
131 * Program the UDMA timing for this drive according to the
135 static void it821x_program_udma(ide_drive_t
*drive
, u16 timing
)
137 ide_hwif_t
*hwif
= drive
->hwif
;
138 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
139 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
140 int channel
= hwif
->channel
;
141 int unit
= drive
->select
.b
.unit
;
144 /* Program UDMA timing bits */
145 if(itdev
->clock_mode
== ATA_66
)
148 conf
= timing
& 0xFF;
150 if (itdev
->timing10
== 0)
151 pci_write_config_byte(dev
, 0x56 + 4 * channel
+ unit
, conf
);
153 pci_write_config_byte(dev
, 0x56 + 4 * channel
, conf
);
154 pci_write_config_byte(dev
, 0x56 + 4 * channel
+ 1, conf
);
159 * it821x_clock_strategy
160 * @drive: drive to set up
162 * Select between the 50 and 66Mhz base clocks to get the best
163 * results for this interface.
166 static void it821x_clock_strategy(ide_drive_t
*drive
)
168 ide_hwif_t
*hwif
= drive
->hwif
;
169 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
170 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
172 u8 unit
= drive
->select
.b
.unit
;
173 ide_drive_t
*pair
= &hwif
->drives
[1-unit
];
179 if(itdev
->want
[0][0] > itdev
->want
[1][0]) {
180 clock
= itdev
->want
[0][1];
181 altclock
= itdev
->want
[1][1];
183 clock
= itdev
->want
[1][1];
184 altclock
= itdev
->want
[0][1];
188 * if both clocks can be used for the mode with the higher priority
189 * use the clock needed by the mode with the lower priority
191 if (clock
== ATA_ANY
)
194 /* Nobody cares - keep the same clock */
198 if(clock
== itdev
->clock_mode
)
201 /* Load this into the controller ? */
203 itdev
->clock_mode
= ATA_66
;
205 itdev
->clock_mode
= ATA_50
;
209 pci_read_config_byte(dev
, 0x50, &v
);
210 v
&= ~(1 << (1 + hwif
->channel
));
211 v
|= sel
<< (1 + hwif
->channel
);
212 pci_write_config_byte(dev
, 0x50, v
);
215 * Reprogram the UDMA/PIO of the pair drive for the switch
216 * MWDMA will be dealt with by the dma switcher
218 if(pair
&& itdev
->udma
[1-unit
] != UDMA_OFF
) {
219 it821x_program_udma(pair
, itdev
->udma
[1-unit
]);
220 it821x_program(pair
, itdev
->pio
[1-unit
]);
223 * Reprogram the UDMA/PIO of our drive for the switch.
224 * MWDMA will be dealt with by the dma switcher
226 if(itdev
->udma
[unit
] != UDMA_OFF
) {
227 it821x_program_udma(drive
, itdev
->udma
[unit
]);
228 it821x_program(drive
, itdev
->pio
[unit
]);
233 * it821x_set_pio_mode - set host controller for PIO mode
235 * @pio: PIO mode number
237 * Tune the host to the desired PIO mode taking into the consideration
238 * the maximum PIO mode supported by the other device on the cable.
241 static void it821x_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
243 ide_hwif_t
*hwif
= drive
->hwif
;
244 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
245 int unit
= drive
->select
.b
.unit
;
246 ide_drive_t
*pair
= &hwif
->drives
[1 - unit
];
249 /* Spec says 89 ref driver uses 88 */
250 static u16 pio_timings
[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
251 static u8 pio_want
[] = { ATA_66
, ATA_66
, ATA_66
, ATA_66
, ATA_ANY
};
254 * Compute the best PIO mode we can for a given device. We must
255 * pick a speed that does not cause problems with the other device
259 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
260 /* trim PIO to the slowest of the master/slave */
261 if (pair_pio
< set_pio
)
265 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
266 itdev
->want
[unit
][1] = pio_want
[set_pio
];
267 itdev
->want
[unit
][0] = 1; /* PIO is lowest priority */
268 itdev
->pio
[unit
] = pio_timings
[set_pio
];
269 it821x_clock_strategy(drive
);
270 it821x_program(drive
, itdev
->pio
[unit
]);
274 * it821x_tune_mwdma - tune a channel for MWDMA
275 * @drive: drive to set up
276 * @mode_wanted: the target operating mode
278 * Load the timing settings for this device mode into the
279 * controller when doing MWDMA in pass through mode. The caller
280 * must manage the whole lack of per device MWDMA/PIO timings and
281 * the shared MWDMA/PIO timing register.
284 static void it821x_tune_mwdma (ide_drive_t
*drive
, byte mode_wanted
)
286 ide_hwif_t
*hwif
= drive
->hwif
;
287 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
288 struct it821x_dev
*itdev
= (void *)ide_get_hwifdata(hwif
);
289 int unit
= drive
->select
.b
.unit
;
290 int channel
= hwif
->channel
;
293 static u16 dma
[] = { 0x8866, 0x3222, 0x3121 };
294 static u8 mwdma_want
[] = { ATA_ANY
, ATA_66
, ATA_ANY
};
296 itdev
->want
[unit
][1] = mwdma_want
[mode_wanted
];
297 itdev
->want
[unit
][0] = 2; /* MWDMA is low priority */
298 itdev
->mwdma
[unit
] = dma
[mode_wanted
];
299 itdev
->udma
[unit
] = UDMA_OFF
;
301 /* UDMA bits off - Revision 0x10 do them in pairs */
302 pci_read_config_byte(dev
, 0x50, &conf
);
304 conf
|= channel
? 0x60: 0x18;
306 conf
|= 1 << (3 + 2 * channel
+ unit
);
307 pci_write_config_byte(dev
, 0x50, conf
);
309 it821x_clock_strategy(drive
);
310 /* FIXME: do we need to program this ? */
311 /* it821x_program(drive, itdev->mwdma[unit]); */
315 * it821x_tune_udma - tune a channel for UDMA
316 * @drive: drive to set up
317 * @mode_wanted: the target operating mode
319 * Load the timing settings for this device mode into the
320 * controller when doing UDMA modes in pass through.
323 static void it821x_tune_udma (ide_drive_t
*drive
, byte mode_wanted
)
325 ide_hwif_t
*hwif
= drive
->hwif
;
326 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
327 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
328 int unit
= drive
->select
.b
.unit
;
329 int channel
= hwif
->channel
;
332 static u16 udma
[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
333 static u8 udma_want
[] = { ATA_ANY
, ATA_50
, ATA_ANY
, ATA_66
, ATA_66
, ATA_50
, ATA_66
};
335 itdev
->want
[unit
][1] = udma_want
[mode_wanted
];
336 itdev
->want
[unit
][0] = 3; /* UDMA is high priority */
337 itdev
->mwdma
[unit
] = MWDMA_OFF
;
338 itdev
->udma
[unit
] = udma
[mode_wanted
];
340 itdev
->udma
[unit
] |= 0x8080; /* UDMA 5/6 select on */
342 /* UDMA on. Again revision 0x10 must do the pair */
343 pci_read_config_byte(dev
, 0x50, &conf
);
345 conf
&= channel
? 0x9F: 0xE7;
347 conf
&= ~ (1 << (3 + 2 * channel
+ unit
));
348 pci_write_config_byte(dev
, 0x50, conf
);
350 it821x_clock_strategy(drive
);
351 it821x_program_udma(drive
, itdev
->udma
[unit
]);
356 * it821x_dma_read - DMA hook
357 * @drive: drive for DMA
359 * The IT821x has a single timing register for MWDMA and for PIO
360 * operations. As we flip back and forth we have to reload the
361 * clock. In addition the rev 0x10 device only works if the same
362 * timing value is loaded into the master and slave UDMA clock
363 * so we must also reload that.
365 * FIXME: we could figure out in advance if we need to do reloads
368 static void it821x_dma_start(ide_drive_t
*drive
)
370 ide_hwif_t
*hwif
= drive
->hwif
;
371 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
372 int unit
= drive
->select
.b
.unit
;
373 if(itdev
->mwdma
[unit
] != MWDMA_OFF
)
374 it821x_program(drive
, itdev
->mwdma
[unit
]);
375 else if(itdev
->udma
[unit
] != UDMA_OFF
&& itdev
->timing10
)
376 it821x_program_udma(drive
, itdev
->udma
[unit
]);
377 ide_dma_start(drive
);
381 * it821x_dma_write - DMA hook
382 * @drive: drive for DMA stop
384 * The IT821x has a single timing register for MWDMA and for PIO
385 * operations. As we flip back and forth we have to reload the
389 static int it821x_dma_end(ide_drive_t
*drive
)
391 ide_hwif_t
*hwif
= drive
->hwif
;
392 int unit
= drive
->select
.b
.unit
;
393 struct it821x_dev
*itdev
= ide_get_hwifdata(hwif
);
394 int ret
= __ide_dma_end(drive
);
395 if(itdev
->mwdma
[unit
] != MWDMA_OFF
)
396 it821x_program(drive
, itdev
->pio
[unit
]);
401 * it821x_set_dma_mode - set host controller for DMA mode
405 * Tune the ITE chipset for the desired DMA mode.
408 static void it821x_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
411 * MWDMA tuning is really hard because our MWDMA and PIO
412 * timings are kept in the same place. We can switch in the
413 * host dma on/off callbacks.
415 if (speed
>= XFER_UDMA_0
&& speed
<= XFER_UDMA_6
)
416 it821x_tune_udma(drive
, speed
- XFER_UDMA_0
);
417 else if (speed
>= XFER_MW_DMA_0
&& speed
<= XFER_MW_DMA_2
)
418 it821x_tune_mwdma(drive
, speed
- XFER_MW_DMA_0
);
422 * it821x_cable_detect - cable detection
423 * @hwif: interface to check
425 * Check for the presence of an ATA66 capable cable on the
426 * interface. Problematic as it seems some cards don't have
427 * the needed logic onboard.
430 static u8
it821x_cable_detect(ide_hwif_t
*hwif
)
432 /* The reference driver also only does disk side */
433 return ATA_CBL_PATA80
;
437 * it821x_quirkproc - post init callback
440 * This callback is run after the drive has been probed but
441 * before anything gets attached. It allows drivers to do any
442 * final tuning that is needed, or fixups to work around bugs.
445 static void it821x_quirkproc(ide_drive_t
*drive
)
447 struct it821x_dev
*itdev
= ide_get_hwifdata(drive
->hwif
);
452 * If we are in pass through mode then not much
453 * needs to be done, but we do bother to clear the
454 * IRQ mask as we may well be in PIO (eg rev 0x10)
455 * for now and we know unmasking is safe on this chipset.
457 drive
->dev_flags
|= IDE_DFLAG_UNMASK
;
460 * Perform fixups on smart mode. We need to "lose" some
461 * capabilities the firmware lacks but does not filter, and
462 * also patch up some capability bits that it forgets to set
466 /* Check for RAID v native */
467 if (strstr((char *)&id
[ATA_ID_PROD
],
468 "Integrated Technology Express")) {
469 /* In raid mode the ident block is slightly buggy
470 We need to set the bits so that the IDE layer knows
471 LBA28. LBA48 and DMA ar valid */
472 id
[ATA_ID_CAPABILITY
] |= (3 << 8); /* LBA28, DMA */
473 id
[ATA_ID_COMMAND_SET_2
] |= 0x0400; /* LBA48 valid */
474 id
[ATA_ID_CFS_ENABLE_2
] |= 0x0400; /* LBA48 on */
475 /* Reporting logic */
476 printk(KERN_INFO
"%s: IT8212 %sRAID %d volume",
477 drive
->name
, id
[147] ? "Bootable " : "",
479 if (id
[ATA_ID_CSFO
] != 1)
480 printk(KERN_CONT
"(%dK stripe)", id
[146]);
481 printk(KERN_CONT
".\n");
483 /* Non RAID volume. Fixups to stop the core code
484 doing unsupported things */
485 id
[ATA_ID_FIELD_VALID
] &= 3;
486 id
[ATA_ID_QUEUE_DEPTH
] = 0;
487 id
[ATA_ID_COMMAND_SET_1
] = 0;
488 id
[ATA_ID_COMMAND_SET_2
] &= 0xC400;
489 id
[ATA_ID_CFSSE
] &= 0xC000;
490 id
[ATA_ID_CFS_ENABLE_1
] = 0;
491 id
[ATA_ID_CFS_ENABLE_2
] &= 0xC400;
492 id
[ATA_ID_CSF_DEFAULT
] &= 0xC000;
496 id
[ATA_ID_CFA_POWER
] = 0;
497 printk(KERN_INFO
"%s: Performing identify fixups.\n",
502 * Set MWDMA0 mode as enabled/support - just to tell
503 * IDE core that DMA is supported (it821x hardware
504 * takes care of DMA mode programming).
506 if (ata_id_has_dma(id
)) {
507 id
[ATA_ID_MWDMA_MODES
] |= 0x0101;
508 drive
->current_speed
= XFER_MW_DMA_0
;
514 static struct ide_dma_ops it821x_pass_through_dma_ops
= {
515 .dma_host_set
= ide_dma_host_set
,
516 .dma_setup
= ide_dma_setup
,
517 .dma_exec_cmd
= ide_dma_exec_cmd
,
518 .dma_start
= it821x_dma_start
,
519 .dma_end
= it821x_dma_end
,
520 .dma_test_irq
= ide_dma_test_irq
,
521 .dma_timeout
= ide_dma_timeout
,
522 .dma_lost_irq
= ide_dma_lost_irq
,
526 * init_hwif_it821x - set up hwif structs
527 * @hwif: interface to set up
529 * We do the basic set up of the interface structure. The IT8212
530 * requires several custom handlers so we override the default
531 * ide DMA handlers appropriately
534 static void __devinit
init_hwif_it821x(ide_hwif_t
*hwif
)
536 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
537 struct ide_host
*host
= pci_get_drvdata(dev
);
538 struct it821x_dev
*itdevs
= host
->host_priv
;
539 struct it821x_dev
*idev
= itdevs
+ hwif
->channel
;
542 ide_set_hwifdata(hwif
, idev
);
544 pci_read_config_byte(dev
, 0x50, &conf
);
547 hwif
->host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
548 /* Long I/O's although allowed in LBA48 space cause the
549 onboard firmware to enter the twighlight zone */
553 /* Pull the current clocks from 0x50 also */
554 if (conf
& (1 << (1 + hwif
->channel
)))
555 idev
->clock_mode
= ATA_50
;
557 idev
->clock_mode
= ATA_66
;
559 idev
->want
[0][1] = ATA_ANY
;
560 idev
->want
[1][1] = ATA_ANY
;
563 * Not in the docs but according to the reference driver
567 pci_read_config_byte(dev
, 0x08, &conf
);
570 hwif
->host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
571 if (idev
->smart
== 0)
572 printk(KERN_WARNING DRV_NAME
" %s: revision 0x10, "
573 "workarounds activated\n", pci_name(dev
));
576 if (idev
->smart
== 0) {
577 /* MWDMA/PIO clock switching for pass through mode */
578 hwif
->dma_ops
= &it821x_pass_through_dma_ops
;
580 hwif
->host_flags
|= IDE_HFLAG_NO_SET_MODE
;
582 if (hwif
->dma_base
== 0)
585 hwif
->ultra_mask
= ATA_UDMA6
;
586 hwif
->mwdma_mask
= ATA_MWDMA2
;
589 static void it8212_disable_raid(struct pci_dev
*dev
)
591 /* Reset local CPU, and set BIOS not ready */
592 pci_write_config_byte(dev
, 0x5E, 0x01);
594 /* Set to bypass mode, and reset PCI bus */
595 pci_write_config_byte(dev
, 0x50, 0x00);
596 pci_write_config_word(dev
, PCI_COMMAND
,
597 PCI_COMMAND_PARITY
| PCI_COMMAND_IO
|
598 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
599 pci_write_config_word(dev
, 0x40, 0xA0F3);
601 pci_write_config_dword(dev
,0x4C, 0x02040204);
602 pci_write_config_byte(dev
, 0x42, 0x36);
603 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x20);
606 static unsigned int init_chipset_it821x(struct pci_dev
*dev
)
609 static char *mode
[2] = { "pass through", "smart" };
611 /* Force the card into bypass mode if so requested */
613 printk(KERN_INFO DRV_NAME
" %s: forcing bypass mode\n",
615 it8212_disable_raid(dev
);
617 pci_read_config_byte(dev
, 0x50, &conf
);
618 printk(KERN_INFO DRV_NAME
" %s: controller in %s mode\n",
619 pci_name(dev
), mode
[conf
& 1]);
623 static const struct ide_port_ops it821x_port_ops
= {
624 /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
625 .set_pio_mode
= it821x_set_pio_mode
,
626 .set_dma_mode
= it821x_set_dma_mode
,
627 .quirkproc
= it821x_quirkproc
,
628 .cable_detect
= it821x_cable_detect
,
631 static const struct ide_port_info it821x_chipset __devinitdata
= {
633 .init_chipset
= init_chipset_it821x
,
634 .init_hwif
= init_hwif_it821x
,
635 .port_ops
= &it821x_port_ops
,
636 .pio_mask
= ATA_PIO4
,
640 * it821x_init_one - pci layer discovery entry
642 * @id: ident table entry
644 * Called by the PCI code when it finds an ITE821x controller.
645 * We then use the IDE PCI generic helper to do most of the work.
648 static int __devinit
it821x_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
650 struct it821x_dev
*itdevs
;
653 itdevs
= kzalloc(2 * sizeof(*itdevs
), GFP_KERNEL
);
654 if (itdevs
== NULL
) {
655 printk(KERN_ERR DRV_NAME
" %s: out of memory\n", pci_name(dev
));
659 rc
= ide_pci_init_one(dev
, &it821x_chipset
, itdevs
);
666 static void __devexit
it821x_remove(struct pci_dev
*dev
)
668 struct ide_host
*host
= pci_get_drvdata(dev
);
669 struct it821x_dev
*itdevs
= host
->host_priv
;
675 static const struct pci_device_id it821x_pci_tbl
[] = {
676 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8211
), 0 },
677 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8212
), 0 },
681 MODULE_DEVICE_TABLE(pci
, it821x_pci_tbl
);
683 static struct pci_driver driver
= {
684 .name
= "ITE821x IDE",
685 .id_table
= it821x_pci_tbl
,
686 .probe
= it821x_init_one
,
687 .remove
= __devexit_p(it821x_remove
),
688 .suspend
= ide_pci_suspend
,
689 .resume
= ide_pci_resume
,
692 static int __init
it821x_ide_init(void)
694 return ide_pci_register_driver(&driver
);
697 static void __exit
it821x_ide_exit(void)
699 pci_unregister_driver(&driver
);
702 module_init(it821x_ide_init
);
703 module_exit(it821x_ide_exit
);
705 module_param_named(noraid
, it8212_noraid
, int, S_IRUGO
);
706 MODULE_PARM_DESC(noraid
, "Force card into bypass mode");
708 MODULE_AUTHOR("Alan Cox");
709 MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
710 MODULE_LICENSE("GPL");