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ide: rework the code for selecting the best DMA transfer mode (v3)
[deliverable/linux.git] / drivers / ide / pci / pdc202xx_old.c
1 /*
2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
3 *
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc.
6 *
7 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
8 * compiled into the kernel if you have more than one card installed.
9 * Note that BIOS v1.29 is reported to fix the problem. Since this is
10 * safe chipset tuning, including this support is harmless
11 *
12 * Promise Ultra66 cards with BIOS v1.11 this
13 * compiled into the kernel if you have more than one card installed.
14 *
15 * Promise Ultra100 cards.
16 *
17 * The latest chipset code will support the following ::
18 * Three Ultra33 controllers and 12 drives.
19 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
20 * The 8/4 ratio is a BIOS code limit by promise.
21 *
22 * UNLESS you enable "CONFIG_PDC202XX_BURST"
23 *
24 */
25
26 /*
27 * Portions Copyright (C) 1999 Promise Technology, Inc.
28 * Author: Frank Tiernan (frankt@promise.com)
29 * Released under terms of General Public License
30 */
31
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/timer.h>
37 #include <linux/mm.h>
38 #include <linux/ioport.h>
39 #include <linux/blkdev.h>
40 #include <linux/hdreg.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/ide.h>
45
46 #include <asm/io.h>
47 #include <asm/irq.h>
48
49 #define PDC202_DEBUG_CABLE 0
50 #define PDC202XX_DEBUG_DRIVE_INFO 0
51
52 static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
61 NULL
62 };
63
64 /* A Register */
65 #define SYNC_ERRDY_EN 0xC0
66
67 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
68 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
69 #define IORDY_EN 0x20 /* PIO: IOREADY */
70 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
71
72 #define PA3 0x08 /* PIO"A" timing */
73 #define PA2 0x04 /* PIO"A" timing */
74 #define PA1 0x02 /* PIO"A" timing */
75 #define PA0 0x01 /* PIO"A" timing */
76
77 /* B Register */
78
79 #define MB2 0x80 /* DMA"B" timing */
80 #define MB1 0x40 /* DMA"B" timing */
81 #define MB0 0x20 /* DMA"B" timing */
82
83 #define PB4 0x10 /* PIO_FORCE 1:0 */
84
85 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
86 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
87 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
88 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
89
90 /* C Register */
91 #define IORDYp_NO_SPEED 0x4F
92 #define SPEED_DIS 0x0F
93
94 #define DMARQp 0x80
95 #define IORDYp 0x40
96 #define DMAR_EN 0x20
97 #define DMAW_EN 0x10
98
99 #define MC3 0x08 /* DMA"C" timing */
100 #define MC2 0x04 /* DMA"C" timing */
101 #define MC1 0x02 /* DMA"C" timing */
102 #define MC0 0x01 /* DMA"C" timing */
103
104 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
105 {
106 ide_hwif_t *hwif = HWIF(drive);
107 struct pci_dev *dev = hwif->pci_dev;
108 u8 drive_pci = 0x60 + (drive->dn << 2);
109 u8 speed = ide_rate_filter(drive, xferspeed);
110
111 u32 drive_conf;
112 u8 AP, BP, CP, DP;
113 u8 TA = 0, TB = 0, TC = 0;
114
115 if (drive->media != ide_disk &&
116 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
117 return -1;
118
119 pci_read_config_dword(dev, drive_pci, &drive_conf);
120 pci_read_config_byte(dev, (drive_pci), &AP);
121 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
122 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
123 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
124
125 if (speed < XFER_SW_DMA_0) {
126 if ((AP & 0x0F) || (BP & 0x07)) {
127 /* clear PIO modes of lower 8421 bits of A Register */
128 pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
129 pci_read_config_byte(dev, (drive_pci), &AP);
130
131 /* clear PIO modes of lower 421 bits of B Register */
132 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
133 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
134
135 pci_read_config_byte(dev, (drive_pci), &AP);
136 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
137 }
138 } else {
139 if ((BP & 0xF0) && (CP & 0x0F)) {
140 /* clear DMA modes of upper 842 bits of B Register */
141 /* clear PIO forced mode upper 1 bit of B Register */
142 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
143 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
144
145 /* clear DMA modes of lower 8421 bits of C Register */
146 pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
147 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
148 }
149 }
150
151 pci_read_config_byte(dev, (drive_pci), &AP);
152 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
153 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
154
155 switch(speed) {
156 case XFER_UDMA_6: speed = XFER_UDMA_5;
157 case XFER_UDMA_5:
158 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
159 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
160 case XFER_UDMA_3:
161 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
162 case XFER_UDMA_0:
163 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
164 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
165 case XFER_MW_DMA_0:
166 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
167 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
168 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
169 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
170 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
171 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
172 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
173 case XFER_PIO_0:
174 default: TA = 0x09; TB = 0x13; break;
175 }
176
177 if (speed < XFER_SW_DMA_0) {
178 pci_write_config_byte(dev, (drive_pci), AP|TA);
179 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
180 } else {
181 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
182 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
183 }
184
185 #if PDC202XX_DEBUG_DRIVE_INFO
186 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
187 drive->name, ide_xfer_verbose(speed),
188 drive->dn, drive_conf);
189 pci_read_config_dword(dev, drive_pci, &drive_conf);
190 printk("0x%08x\n", drive_conf);
191 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
192
193 return (ide_config_drive_speed(drive, speed));
194 }
195
196
197 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
198 {
199 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
200 pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
201 }
202
203 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
204 {
205 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
206 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
207 return (CIS & mask) ? 1 : 0;
208 }
209
210 /*
211 * Set the control register to use the 66MHz system
212 * clock for UDMA 3/4/5 mode operation when necessary.
213 *
214 * It may also be possible to leave the 66MHz clock on
215 * and readjust the timing parameters.
216 */
217 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
218 {
219 unsigned long clock_reg = hwif->dma_master + 0x11;
220 u8 clock = inb(clock_reg);
221
222 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
223 }
224
225 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
226 {
227 unsigned long clock_reg = hwif->dma_master + 0x11;
228 u8 clock = inb(clock_reg);
229
230 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
231 }
232
233 static int config_chipset_for_dma (ide_drive_t *drive)
234 {
235 struct hd_driveid *id = drive->id;
236 ide_hwif_t *hwif = HWIF(drive);
237 struct pci_dev *dev = hwif->pci_dev;
238 u32 drive_conf = 0;
239 u8 drive_pci = 0x60 + (drive->dn << 2);
240 u8 test1 = 0, test2 = 0, speed = -1;
241 u8 AP = 0, cable = 0;
242
243 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
244 (id->dma_ultra & 0x0008)) ? 1 : 0;
245
246 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
247 cable = pdc202xx_old_cable_detect(hwif);
248 else
249 ultra_66 = 0;
250
251 if (ultra_66 && cable) {
252 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
253 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
254 }
255
256 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
257 pdc_old_disable_66MHz_clock(drive->hwif);
258
259 drive_pci = 0x60 + (drive->dn << 2);
260 pci_read_config_dword(dev, drive_pci, &drive_conf);
261 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
262 goto chipset_is_set;
263
264 pci_read_config_byte(dev, drive_pci, &test1);
265 if (!(test1 & SYNC_ERRDY_EN)) {
266 if (drive->select.b.unit & 0x01) {
267 pci_read_config_byte(dev, drive_pci - 4, &test2);
268 if ((test2 & SYNC_ERRDY_EN) &&
269 !(test1 & SYNC_ERRDY_EN)) {
270 pci_write_config_byte(dev, drive_pci,
271 test1|SYNC_ERRDY_EN);
272 }
273 } else {
274 pci_write_config_byte(dev, drive_pci,
275 test1|SYNC_ERRDY_EN);
276 }
277 }
278
279 chipset_is_set:
280
281 pci_read_config_byte(dev, (drive_pci), &AP);
282 if (id->capability & 4) /* IORDY_EN */
283 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
284 pci_read_config_byte(dev, (drive_pci), &AP);
285 if (drive->media == ide_disk) /* PREFETCH_EN */
286 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
287
288 speed = ide_max_dma_mode(drive);
289
290 if (!(speed)) {
291 /* restore original pci-config space */
292 pci_write_config_dword(dev, drive_pci, drive_conf);
293 return 0;
294 }
295
296 (void) hwif->speedproc(drive, speed);
297 return ide_dma_enable(drive);
298 }
299
300 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
301 {
302 drive->init_speed = 0;
303
304 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
305 return 0;
306
307 if (ide_use_fast_pio(drive))
308 pdc202xx_tune_drive(drive, 255);
309
310 return -1;
311 }
312
313 static int pdc202xx_quirkproc (ide_drive_t *drive)
314 {
315 const char **list, *model = drive->id->model;
316
317 for (list = pdc_quirk_drives; *list != NULL; list++)
318 if (strstr(model, *list) != NULL)
319 return 2;
320 return 0;
321 }
322
323 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
324 {
325 if (drive->current_speed > XFER_UDMA_2)
326 pdc_old_enable_66MHz_clock(drive->hwif);
327 if (drive->media != ide_disk || drive->addressing == 1) {
328 struct request *rq = HWGROUP(drive)->rq;
329 ide_hwif_t *hwif = HWIF(drive);
330 unsigned long high_16 = hwif->dma_master;
331 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
332 u32 word_count = 0;
333 u8 clock = inb(high_16 + 0x11);
334
335 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
336 word_count = (rq->nr_sectors << 8);
337 word_count = (rq_data_dir(rq) == READ) ?
338 word_count | 0x05000000 :
339 word_count | 0x06000000;
340 outl(word_count, atapi_reg);
341 }
342 ide_dma_start(drive);
343 }
344
345 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
346 {
347 if (drive->media != ide_disk || drive->addressing == 1) {
348 ide_hwif_t *hwif = HWIF(drive);
349 unsigned long high_16 = hwif->dma_master;
350 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
351 u8 clock = 0;
352
353 outl(0, atapi_reg); /* zero out extra */
354 clock = inb(high_16 + 0x11);
355 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
356 }
357 if (drive->current_speed > XFER_UDMA_2)
358 pdc_old_disable_66MHz_clock(drive->hwif);
359 return __ide_dma_end(drive);
360 }
361
362 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
363 {
364 ide_hwif_t *hwif = HWIF(drive);
365 unsigned long high_16 = hwif->dma_master;
366 u8 dma_stat = inb(hwif->dma_status);
367 u8 sc1d = inb(high_16 + 0x001d);
368
369 if (hwif->channel) {
370 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
371 if ((sc1d & 0x50) == 0x50)
372 goto somebody_else;
373 else if ((sc1d & 0x40) == 0x40)
374 return (dma_stat & 4) == 4;
375 } else {
376 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
377 if ((sc1d & 0x05) == 0x05)
378 goto somebody_else;
379 else if ((sc1d & 0x04) == 0x04)
380 return (dma_stat & 4) == 4;
381 }
382 somebody_else:
383 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
384 }
385
386 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
387 {
388 if (HWIF(drive)->resetproc != NULL)
389 HWIF(drive)->resetproc(drive);
390 return __ide_dma_lostirq(drive);
391 }
392
393 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
394 {
395 if (HWIF(drive)->resetproc != NULL)
396 HWIF(drive)->resetproc(drive);
397 return __ide_dma_timeout(drive);
398 }
399
400 static void pdc202xx_reset_host (ide_hwif_t *hwif)
401 {
402 unsigned long high_16 = hwif->dma_master;
403 u8 udma_speed_flag = inb(high_16 | 0x001f);
404
405 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
406 mdelay(100);
407 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
408 mdelay(2000); /* 2 seconds ?! */
409
410 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
411 hwif->channel ? "Secondary" : "Primary");
412 }
413
414 static void pdc202xx_reset (ide_drive_t *drive)
415 {
416 ide_hwif_t *hwif = HWIF(drive);
417 ide_hwif_t *mate = hwif->mate;
418
419 pdc202xx_reset_host(hwif);
420 pdc202xx_reset_host(mate);
421 pdc202xx_tune_drive(drive, 255);
422 }
423
424 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
425 const char *name)
426 {
427 /* This doesn't appear needed */
428 if (dev->resource[PCI_ROM_RESOURCE].start) {
429 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
430 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
431 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
432 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
433 }
434
435 return dev->irq;
436 }
437
438 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
439 {
440 struct pci_dev *dev = hwif->pci_dev;
441
442 /* PDC20265 has problems with large LBA48 requests */
443 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
444 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
445 hwif->rqsize = 256;
446
447 hwif->autodma = 0;
448 hwif->tuneproc = &pdc202xx_tune_drive;
449 hwif->quirkproc = &pdc202xx_quirkproc;
450
451 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
452 hwif->resetproc = &pdc202xx_reset;
453
454 hwif->speedproc = &pdc202xx_tune_chipset;
455
456 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
457
458 hwif->ultra_mask = hwif->cds->udma_mask;
459 hwif->mwdma_mask = 0x07;
460 hwif->swdma_mask = 0x07;
461 hwif->atapi_dma = 1;
462
463 hwif->err_stops_fifo = 1;
464
465 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
466 hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
467 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
468
469 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
470 if (!(hwif->udma_four))
471 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
472 hwif->dma_start = &pdc202xx_old_ide_dma_start;
473 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
474 }
475 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
476
477 if (!noautodma)
478 hwif->autodma = 1;
479 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
480 #if PDC202_DEBUG_CABLE
481 printk(KERN_DEBUG "%s: %s-pin cable\n",
482 hwif->name, hwif->udma_four ? "80" : "40");
483 #endif /* PDC202_DEBUG_CABLE */
484 }
485
486 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
487 {
488 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
489
490 if (hwif->channel) {
491 ide_setup_dma(hwif, dmabase, 8);
492 return;
493 }
494
495 udma_speed_flag = inb(dmabase | 0x1f);
496 primary_mode = inb(dmabase | 0x1a);
497 secondary_mode = inb(dmabase | 0x1b);
498 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
499 "Primary %s Mode " \
500 "Secondary %s Mode.\n", hwif->cds->name,
501 (udma_speed_flag & 1) ? "EN" : "DIS",
502 (primary_mode & 1) ? "MASTER" : "PCI",
503 (secondary_mode & 1) ? "MASTER" : "PCI" );
504
505 #ifdef CONFIG_PDC202XX_BURST
506 if (!(udma_speed_flag & 1)) {
507 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
508 hwif->cds->name, udma_speed_flag,
509 (udma_speed_flag|1));
510 outb(udma_speed_flag | 1, dmabase | 0x1f);
511 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
512 }
513 #endif /* CONFIG_PDC202XX_BURST */
514
515 ide_setup_dma(hwif, dmabase, 8);
516 }
517
518 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
519 ide_pci_device_t *d)
520 {
521 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
522 u8 irq = 0, irq2 = 0;
523 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
524 /* 0xbc */
525 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
526 if (irq != irq2) {
527 pci_write_config_byte(dev,
528 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
529 printk(KERN_INFO "%s: pci-config space interrupt "
530 "mirror fixed.\n", d->name);
531 }
532 }
533 return ide_setup_pci_device(dev, d);
534 }
535
536 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
537 ide_pci_device_t *d)
538 {
539 if ((dev->bus->self) &&
540 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
541 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
542 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
543 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
544 "attached to I2O RAID controller.\n");
545 return -ENODEV;
546 }
547 return ide_setup_pci_device(dev, d);
548 }
549
550 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
551 ide_pci_device_t *d)
552 {
553 return ide_setup_pci_device(dev, d);
554 }
555
556 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
557 { /* 0 */
558 .name = "PDC20246",
559 .init_setup = init_setup_pdc202ata4,
560 .init_chipset = init_chipset_pdc202xx,
561 .init_hwif = init_hwif_pdc202xx,
562 .init_dma = init_dma_pdc202xx,
563 .channels = 2,
564 .autodma = AUTODMA,
565 .bootable = OFF_BOARD,
566 .extra = 16,
567 .udma_mask = 0x07, /* udma0-2 */
568 },{ /* 1 */
569 .name = "PDC20262",
570 .init_setup = init_setup_pdc202ata4,
571 .init_chipset = init_chipset_pdc202xx,
572 .init_hwif = init_hwif_pdc202xx,
573 .init_dma = init_dma_pdc202xx,
574 .channels = 2,
575 .autodma = AUTODMA,
576 .bootable = OFF_BOARD,
577 .extra = 48,
578 .udma_mask = 0x1f, /* udma0-4 */
579 },{ /* 2 */
580 .name = "PDC20263",
581 .init_setup = init_setup_pdc202ata4,
582 .init_chipset = init_chipset_pdc202xx,
583 .init_hwif = init_hwif_pdc202xx,
584 .init_dma = init_dma_pdc202xx,
585 .channels = 2,
586 .autodma = AUTODMA,
587 .bootable = OFF_BOARD,
588 .extra = 48,
589 .udma_mask = 0x1f, /* udma0-4 */
590 },{ /* 3 */
591 .name = "PDC20265",
592 .init_setup = init_setup_pdc20265,
593 .init_chipset = init_chipset_pdc202xx,
594 .init_hwif = init_hwif_pdc202xx,
595 .init_dma = init_dma_pdc202xx,
596 .channels = 2,
597 .autodma = AUTODMA,
598 .bootable = OFF_BOARD,
599 .extra = 48,
600 .udma_mask = 0x3f, /* udma0-5 */
601 },{ /* 4 */
602 .name = "PDC20267",
603 .init_setup = init_setup_pdc202xx,
604 .init_chipset = init_chipset_pdc202xx,
605 .init_hwif = init_hwif_pdc202xx,
606 .init_dma = init_dma_pdc202xx,
607 .channels = 2,
608 .autodma = AUTODMA,
609 .bootable = OFF_BOARD,
610 .extra = 48,
611 .udma_mask = 0x3f, /* udma0-5 */
612 }
613 };
614
615 /**
616 * pdc202xx_init_one - called when a PDC202xx is found
617 * @dev: the pdc202xx device
618 * @id: the matching pci id
619 *
620 * Called when the PCI registration layer (or the IDE initialization)
621 * finds a device matching our IDE device tables.
622 */
623
624 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
625 {
626 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
627
628 return d->init_setup(dev, d);
629 }
630
631 static struct pci_device_id pdc202xx_pci_tbl[] = {
632 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
633 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
634 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
635 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
636 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
637 { 0, },
638 };
639 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
640
641 static struct pci_driver driver = {
642 .name = "Promise_Old_IDE",
643 .id_table = pdc202xx_pci_tbl,
644 .probe = pdc202xx_init_one,
645 };
646
647 static int __init pdc202xx_ide_init(void)
648 {
649 return ide_pci_register_driver(&driver);
650 }
651
652 module_init(pdc202xx_ide_init);
653
654 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
655 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
656 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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