drivers/ide/pci/scc_pata.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ide/pci/siimage.c:
   7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/hdreg.h>
  30 #include <linux/ide.h>
  31 #include <linux/init.h>
  32
  33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  34
  35 #define SCC_PATA_NAME           "scc IDE"
  36
  37 #define TDVHSEL_MASTER          0x00000001
  38 #define TDVHSEL_SLAVE           0x00000004
  39
  40 #define MODE_JCUSFEN            0x00000080
  41
  42 #define CCKCTRL_ATARESET        0x00040000
  43 #define CCKCTRL_BUFCNT          0x00020000
  44 #define CCKCTRL_CRST            0x00010000
  45 #define CCKCTRL_OCLKEN          0x00000100
  46 #define CCKCTRL_ATACLKOEN       0x00000002
  47 #define CCKCTRL_LCLKEN          0x00000001
  48
  49 #define QCHCD_IOS_SS            0x00000001
  50
  51 #define QCHSD_STPDIAG           0x00020000
  52
  53 #define INTMASK_MSK             0xD1000012
  54 #define INTSTS_SERROR           0x80000000
  55 #define INTSTS_PRERR            0x40000000
  56 #define INTSTS_RERR             0x10000000
  57 #define INTSTS_ICERR            0x01000000
  58 #define INTSTS_BMSINT           0x00000010
  59 #define INTSTS_BMHE             0x00000008
  60 #define INTSTS_IOIRQS           0x00000004
  61 #define INTSTS_INTRQ            0x00000002
  62 #define INTSTS_ACTEINT          0x00000001
  63
  64 #define ECMODE_VALUE 0x01
  65
  66 static struct scc_ports {
  67         unsigned long ctl, dma;
  68         unsigned char hwif_id;  /* for removing hwif from system */
  69 } scc_ports[MAX_HWIFS];
  70
  71 /* PIO transfer mode  table */
  72 /* JCHST */
  73 static unsigned long JCHSTtbl[2][7] = {
  74         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  75         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  76 };
  77
  78 /* JCHHT */
  79 static unsigned long JCHHTtbl[2][7] = {
  80         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  81         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  82 };
  83
  84 /* JCHCT */
  85 static unsigned long JCHCTtbl[2][7] = {
  86         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  87         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  88 };
  89
  90
  91 /* DMA transfer mode  table */
  92 /* JCHDCTM/JCHDCTS */
  93 static unsigned long JCHDCTxtbl[2][7] = {
  94         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  95         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  96 };
  97
  98 /* JCSTWTM/JCSTWTS  */
  99 static unsigned long JCSTWTxtbl[2][7] = {
 100         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 101         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 102 };
 103
 104 /* JCTSS */
 105 static unsigned long JCTSStbl[2][7] = {
 106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 107         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 108 };
 109
 110 /* JCENVT */
 111 static unsigned long JCENVTtbl[2][7] = {
 112         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 113         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 114 };
 115
 116 /* JCACTSELS/JCACTSELM */
 117 static unsigned long JCACTSELtbl[2][7] = {
 118         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 119         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 120 };
 121
 122
 123 static u8 scc_ide_inb(unsigned long port)
 124 {
 125         u32 data = in_be32((void*)port);
 126         return (u8)data;
 127 }
 128
 129 static u16 scc_ide_inw(unsigned long port)
 130 {
 131         u32 data = in_be32((void*)port);
 132         return (u16)data;
 133 }
 134
 135 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 136 {
 137         u16 *ptr = (u16 *)addr;
 138         while (count--) {
 139                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 140         }
 141 }
 142
 143 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 144 {
 145         u16 *ptr = (u16 *)addr;
 146         while (count--) {
 147                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 148                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 149         }
 150 }
 151
 152 static void scc_ide_outb(u8 addr, unsigned long port)
 153 {
 154         out_be32((void*)port, addr);
 155 }
 156
 157 static void scc_ide_outw(u16 addr, unsigned long port)
 158 {
 159         out_be32((void*)port, addr);
 160 }
 161
 162 static void
 163 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
 164 {
 165         ide_hwif_t *hwif = HWIF(drive);
 166
 167         out_be32((void*)port, addr);
 168         eieio();
 169         in_be32((void*)(hwif->dma_base + 0x01c));
 170         eieio();
 171 }
 172
 173 static void
 174 scc_ide_outsw(unsigned long port, void *addr, u32 count)
 175 {
 176         u16 *ptr = (u16 *)addr;
 177         while (count--) {
 178                 out_be32((void*)port, cpu_to_le16(*ptr++));
 179         }
 180 }
 181
 182 static void
 183 scc_ide_outsl(unsigned long port, void *addr, u32 count)
 184 {
 185         u16 *ptr = (u16 *)addr;
 186         while (count--) {
 187                 out_be32((void*)port, cpu_to_le16(*ptr++));
 188                 out_be32((void*)port, cpu_to_le16(*ptr++));
 189         }
 190 }
 191
 192 /**
 193  *      scc_set_pio_mode        -       set host controller for PIO mode
 194  *      @drive: drive
 195  *      @pio: PIO mode number
 196  *
 197  *      Load the timing settings for this device mode into the
 198  *      controller.
 199  */
 200
 201 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
 202 {
 203         ide_hwif_t *hwif = HWIF(drive);
 204         struct scc_ports *ports = ide_get_hwifdata(hwif);
 205         unsigned long ctl_base = ports->ctl;
 206         unsigned long cckctrl_port = ctl_base + 0xff0;
 207         unsigned long piosht_port = ctl_base + 0x000;
 208         unsigned long pioct_port = ctl_base + 0x004;
 209         unsigned long reg;
 210         int offset;
 211
 212         reg = in_be32((void __iomem *)cckctrl_port);
 213         if (reg & CCKCTRL_ATACLKOEN) {
 214                 offset = 1; /* 133MHz */
 215         } else {
 216                 offset = 0; /* 100MHz */
 217         }
 218         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 219         out_be32((void __iomem *)piosht_port, reg);
 220         reg = JCHCTtbl[offset][pio];
 221         out_be32((void __iomem *)pioct_port, reg);
 222 }
 223
 224 /**
 225  *      scc_set_dma_mode        -       set host controller for DMA mode
 226  *      @drive: drive
 227  *      @speed: DMA mode
 228  *
 229  *      Load the timing settings for this device mode into the
 230  *      controller.
 231  */
 232
 233 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
 234 {
 235         ide_hwif_t *hwif = HWIF(drive);
 236         struct scc_ports *ports = ide_get_hwifdata(hwif);
 237         unsigned long ctl_base = ports->ctl;
 238         unsigned long cckctrl_port = ctl_base + 0xff0;
 239         unsigned long mdmact_port = ctl_base + 0x008;
 240         unsigned long mcrcst_port = ctl_base + 0x00c;
 241         unsigned long sdmact_port = ctl_base + 0x010;
 242         unsigned long scrcst_port = ctl_base + 0x014;
 243         unsigned long udenvt_port = ctl_base + 0x018;
 244         unsigned long tdvhsel_port   = ctl_base + 0x020;
 245         int is_slave = (&hwif->drives[1] == drive);
 246         int offset, idx;
 247         unsigned long reg;
 248         unsigned long jcactsel;
 249
 250         reg = in_be32((void __iomem *)cckctrl_port);
 251         if (reg & CCKCTRL_ATACLKOEN) {
 252                 offset = 1; /* 133MHz */
 253         } else {
 254                 offset = 0; /* 100MHz */
 255         }
 256
 257         switch (speed) {
 258         case XFER_UDMA_6:
 259         case XFER_UDMA_5:
 260         case XFER_UDMA_4:
 261         case XFER_UDMA_3:
 262         case XFER_UDMA_2:
 263         case XFER_UDMA_1:
 264         case XFER_UDMA_0:
 265                 idx = speed - XFER_UDMA_0;
 266                 break;
 267         default:
 268                 return;
 269         }
 270
 271         jcactsel = JCACTSELtbl[offset][idx];
 272         if (is_slave) {
 273                 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
 274                 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
 275                 jcactsel = jcactsel << 2;
 276                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
 277         } else {
 278                 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
 279                 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
 280                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
 281         }
 282         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 283         out_be32((void __iomem *)udenvt_port, reg);
 284 }
 285
 286 /**
 287  *      scc_configure_drive_for_dma     -       set up for DMA transfers
 288  *      @drive: drive we are going to set up
 289  *
 290  *      Set up the drive for DMA, tune the controller and drive as
 291  *      required.
 292  *      If the drive isn't suitable for DMA or we hit other problems
 293  *      then we will drop down to PIO and set up PIO appropriately.
 294  *      (return -1)
 295  */
 296
 297 static int scc_config_drive_for_dma(ide_drive_t *drive)
 298 {
 299         if (ide_tune_dma(drive))
 300                 return 0;
 301
 302         if (ide_use_fast_pio(drive))
 303                 ide_set_max_pio(drive);
 304
 305         return -1;
 306 }
 307
 308 /**
 309  *      scc_ide_dma_setup       -       begin a DMA phase
 310  *      @drive: target device
 311  *
 312  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 313  *      and then set up the DMA transfer registers.
 314  *
 315  *      Returns 0 on success. If a PIO fallback is required then 1
 316  *      is returned.
 317  */
 318
 319 static int scc_dma_setup(ide_drive_t *drive)
 320 {
 321         ide_hwif_t *hwif = drive->hwif;
 322         struct request *rq = HWGROUP(drive)->rq;
 323         unsigned int reading;
 324         u8 dma_stat;
 325
 326         if (rq_data_dir(rq))
 327                 reading = 0;
 328         else
 329                 reading = 1 << 3;
 330
 331         /* fall back to pio! */
 332         if (!ide_build_dmatable(drive, rq)) {
 333                 ide_map_sg(drive, rq);
 334                 return 1;
 335         }
 336
 337         /* PRD table */
 338         out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
 339
 340         /* specify r/w */
 341         out_be32((void __iomem *)hwif->dma_command, reading);
 342
 343         /* read dma_status for INTR & ERROR flags */
 344         dma_stat = in_be32((void __iomem *)hwif->dma_status);
 345
 346         /* clear INTR & ERROR flags */
 347         out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
 348         drive->waiting_for_dma = 1;
 349         return 0;
 350 }
 351
 352
 353 /**
 354  *      scc_ide_dma_end -       Stop DMA
 355  *      @drive: IDE drive
 356  *
 357  *      Check and clear INT Status register.
 358  *      Then call __ide_dma_end().
 359  */
 360
 361 static int scc_ide_dma_end(ide_drive_t * drive)
 362 {
 363         ide_hwif_t *hwif = HWIF(drive);
 364         unsigned long intsts_port = hwif->dma_base + 0x014;
 365         u32 reg;
 366         int dma_stat, data_loss = 0;
 367         static int retry = 0;
 368
 369         /* errata A308 workaround: Step5 (check data loss) */
 370         /* We don't check non ide_disk because it is limited to UDMA4 */
 371         if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 372             drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
 373                 reg = in_be32((void __iomem *)intsts_port);
 374                 if (!(reg & INTSTS_ACTEINT)) {
 375                         printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
 376                                drive->name);
 377                         data_loss = 1;
 378                         if (retry++) {
 379                                 struct request *rq = HWGROUP(drive)->rq;
 380                                 int unit;
 381                                 /* ERROR_RESET and drive->crc_count are needed
 382                                  * to reduce DMA transfer mode in retry process.
 383                                  */
 384                                 if (rq)
 385                                         rq->errors |= ERROR_RESET;
 386                                 for (unit = 0; unit < MAX_DRIVES; unit++) {
 387                                         ide_drive_t *drive = &hwif->drives[unit];
 388                                         drive->crc_count++;
 389                                 }
 390                         }
 391                 }
 392         }
 393
 394         while (1) {
 395                 reg = in_be32((void __iomem *)intsts_port);
 396
 397                 if (reg & INTSTS_SERROR) {
 398                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 399                         out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
 400
 401                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 402                         continue;
 403                 }
 404
 405                 if (reg & INTSTS_PRERR) {
 406                         u32 maea0, maec0;
 407                         unsigned long ctl_base = hwif->config_data;
 408
 409                         maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
 410                         maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
 411
 412                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 413
 414                         out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
 415
 416                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 417                         continue;
 418                 }
 419
 420                 if (reg & INTSTS_RERR) {
 421                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 422                         out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
 423
 424                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 425                         continue;
 426                 }
 427
 428                 if (reg & INTSTS_ICERR) {
 429                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 430
 431                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 432                         out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
 433                         continue;
 434                 }
 435
 436                 if (reg & INTSTS_BMSINT) {
 437                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 438                         out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
 439
 440                         ide_do_reset(drive);
 441                         continue;
 442                 }
 443
 444                 if (reg & INTSTS_BMHE) {
 445                         out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
 446                         continue;
 447                 }
 448
 449                 if (reg & INTSTS_ACTEINT) {
 450                         out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
 451                         continue;
 452                 }
 453
 454                 if (reg & INTSTS_IOIRQS) {
 455                         out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
 456                         continue;
 457                 }
 458                 break;
 459         }
 460
 461         dma_stat = __ide_dma_end(drive);
 462         if (data_loss)
 463                 dma_stat |= 2; /* emulate DMA error (to retry command) */
 464         return dma_stat;
 465 }
 466
 467 /* returns 1 if dma irq issued, 0 otherwise */
 468 static int scc_dma_test_irq(ide_drive_t *drive)
 469 {
 470         ide_hwif_t *hwif = HWIF(drive);
 471         u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
 472
 473         /* SCC errata A252,A308 workaround: Step4 */
 474         if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 475             (int_stat & INTSTS_INTRQ))
 476                 return 1;
 477
 478         /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
 479         if (int_stat & INTSTS_IOIRQS)
 480                 return 1;
 481
 482         if (!drive->waiting_for_dma)
 483                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 484                         drive->name, __FUNCTION__);
 485         return 0;
 486 }
 487
 488 static u8 scc_udma_filter(ide_drive_t *drive)
 489 {
 490         ide_hwif_t *hwif = drive->hwif;
 491         u8 mask = hwif->ultra_mask;
 492
 493         /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
 494         if ((drive->media != ide_disk) && (mask & 0xE0)) {
 495                 printk(KERN_INFO "%s: limit %s to UDMA4\n",
 496                        SCC_PATA_NAME, drive->name);
 497                 mask = 0x1F;
 498         }
 499
 500         return mask;
 501 }
 502
 503 /**
 504  *      setup_mmio_scc  -       map CTRL/BMID region
 505  *      @dev: PCI device we are configuring
 506  *      @name: device name
 507  *
 508  */
 509
 510 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 511 {
 512         unsigned long ctl_base = pci_resource_start(dev, 0);
 513         unsigned long dma_base = pci_resource_start(dev, 1);
 514         unsigned long ctl_size = pci_resource_len(dev, 0);
 515         unsigned long dma_size = pci_resource_len(dev, 1);
 516         void __iomem *ctl_addr;
 517         void __iomem *dma_addr;
 518         int i;
 519
 520         for (i = 0; i < MAX_HWIFS; i++) {
 521                 if (scc_ports[i].ctl == 0)
 522                         break;
 523         }
 524         if (i >= MAX_HWIFS)
 525                 return -ENOMEM;
 526
 527         if (!request_mem_region(ctl_base, ctl_size, name)) {
 528                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 529                 goto fail_0;
 530         }
 531
 532         if (!request_mem_region(dma_base, dma_size, name)) {
 533                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 534                 goto fail_1;
 535         }
 536
 537         if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
 538                 goto fail_2;
 539
 540         if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
 541                 goto fail_3;
 542
 543         pci_set_master(dev);
 544         scc_ports[i].ctl = (unsigned long)ctl_addr;
 545         scc_ports[i].dma = (unsigned long)dma_addr;
 546         pci_set_drvdata(dev, (void *) &scc_ports[i]);
 547
 548         return 1;
 549
 550  fail_3:
 551         iounmap(ctl_addr);
 552  fail_2:
 553         release_mem_region(dma_base, dma_size);
 554  fail_1:
 555         release_mem_region(ctl_base, ctl_size);
 556  fail_0:
 557         return -ENOMEM;
 558 }
 559
 560 /**
 561  *      init_setup_scc  -       set up an SCC PATA Controller
 562  *      @dev: PCI device
 563  *      @d: IDE PCI device
 564  *
 565  *      Perform the initial set up for this device.
 566  */
 567
 568 static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
 569 {
 570         unsigned long ctl_base;
 571         unsigned long dma_base;
 572         unsigned long cckctrl_port;
 573         unsigned long intmask_port;
 574         unsigned long mode_port;
 575         unsigned long ecmode_port;
 576         unsigned long dma_status_port;
 577         u32 reg = 0;
 578         struct scc_ports *ports;
 579         int rc;
 580
 581         rc = setup_mmio_scc(dev, d->name);
 582         if (rc < 0) {
 583                 return rc;
 584         }
 585
 586         ports = pci_get_drvdata(dev);
 587         ctl_base = ports->ctl;
 588         dma_base = ports->dma;
 589         cckctrl_port = ctl_base + 0xff0;
 590         intmask_port = dma_base + 0x010;
 591         mode_port = ctl_base + 0x024;
 592         ecmode_port = ctl_base + 0xf00;
 593         dma_status_port = dma_base + 0x004;
 594
 595         /* controller initialization */
 596         reg = 0;
 597         out_be32((void*)cckctrl_port, reg);
 598         reg |= CCKCTRL_ATACLKOEN;
 599         out_be32((void*)cckctrl_port, reg);
 600         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 601         out_be32((void*)cckctrl_port, reg);
 602         reg |= CCKCTRL_CRST;
 603         out_be32((void*)cckctrl_port, reg);
 604
 605         for (;;) {
 606                 reg = in_be32((void*)cckctrl_port);
 607                 if (reg & CCKCTRL_CRST)
 608                         break;
 609                 udelay(5000);
 610         }
 611
 612         reg |= CCKCTRL_ATARESET;
 613         out_be32((void*)cckctrl_port, reg);
 614
 615         out_be32((void*)ecmode_port, ECMODE_VALUE);
 616         out_be32((void*)mode_port, MODE_JCUSFEN);
 617         out_be32((void*)intmask_port, INTMASK_MSK);
 618
 619         return ide_setup_pci_device(dev, d);
 620 }
 621
 622 /**
 623  *      init_mmio_iops_scc      -       set up the iops for MMIO
 624  *      @hwif: interface to set up
 625  *
 626  */
 627
 628 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 629 {
 630         struct pci_dev *dev = hwif->pci_dev;
 631         struct scc_ports *ports = pci_get_drvdata(dev);
 632         unsigned long dma_base = ports->dma;
 633
 634         ide_set_hwifdata(hwif, ports);
 635
 636         hwif->INB = scc_ide_inb;
 637         hwif->INW = scc_ide_inw;
 638         hwif->INSW = scc_ide_insw;
 639         hwif->INSL = scc_ide_insl;
 640         hwif->OUTB = scc_ide_outb;
 641         hwif->OUTBSYNC = scc_ide_outbsync;
 642         hwif->OUTW = scc_ide_outw;
 643         hwif->OUTSW = scc_ide_outsw;
 644         hwif->OUTSL = scc_ide_outsl;
 645
 646         hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
 647         hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
 648         hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
 649         hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
 650         hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
 651         hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
 652         hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
 653         hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
 654         hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
 655
 656         hwif->irq = hwif->pci_dev->irq;
 657         hwif->dma_base = dma_base;
 658         hwif->config_data = ports->ctl;
 659         hwif->mmio = 1;
 660 }
 661
 662 /**
 663  *      init_iops_scc   -       set up iops
 664  *      @hwif: interface to set up
 665  *
 666  *      Do the basic setup for the SCC hardware interface
 667  *      and then do the MMIO setup.
 668  */
 669
 670 static void __devinit init_iops_scc(ide_hwif_t *hwif)
 671 {
 672         struct pci_dev *dev =  hwif->pci_dev;
 673         hwif->hwif_data = NULL;
 674         if (pci_get_drvdata(dev) == NULL)
 675                 return;
 676         init_mmio_iops_scc(hwif);
 677 }
 678
 679 /**
 680  *      init_hwif_scc   -       set up hwif
 681  *      @hwif: interface to set up
 682  *
 683  *      We do the basic set up of the interface structure. The SCC
 684  *      requires several custom handlers so we override the default
 685  *      ide DMA handlers appropriately.
 686  */
 687
 688 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 689 {
 690         struct scc_ports *ports = ide_get_hwifdata(hwif);
 691
 692         ports->hwif_id = hwif->index;
 693
 694         hwif->dma_command = hwif->dma_base;
 695         hwif->dma_status = hwif->dma_base + 0x04;
 696         hwif->dma_prdtable = hwif->dma_base + 0x08;
 697
 698         /* PTERADD */
 699         out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
 700
 701         hwif->dma_setup = scc_dma_setup;
 702         hwif->ide_dma_end = scc_ide_dma_end;
 703         hwif->set_pio_mode = scc_set_pio_mode;
 704         hwif->set_dma_mode = scc_set_dma_mode;
 705         hwif->ide_dma_check = scc_config_drive_for_dma;
 706         hwif->ide_dma_test_irq = scc_dma_test_irq;
 707         hwif->udma_filter = scc_udma_filter;
 708
 709         hwif->drives[0].autotune = IDE_TUNE_AUTO;
 710         hwif->drives[1].autotune = IDE_TUNE_AUTO;
 711
 712         if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
 713                 hwif->ultra_mask = 0x7f; /* 133MHz */
 714         } else {
 715                 hwif->ultra_mask = 0x3f; /* 100MHz */
 716         }
 717         hwif->mwdma_mask = 0x00;
 718         hwif->swdma_mask = 0x00;
 719         hwif->atapi_dma = 1;
 720
 721         /* we support 80c cable only. */
 722         hwif->cbl = ATA_CBL_PATA80;
 723
 724         hwif->autodma = 0;
 725         if (!noautodma)
 726                 hwif->autodma = 1;
 727         hwif->drives[0].autodma = hwif->autodma;
 728         hwif->drives[1].autodma = hwif->autodma;
 729 }
 730
 731 #define DECLARE_SCC_DEV(name_str)                       \
 732   {                                                     \
 733       .name             = name_str,                     \
 734       .init_setup       = init_setup_scc,               \
 735       .init_iops        = init_iops_scc,                \
 736       .init_hwif        = init_hwif_scc,                \
 737       .autodma  = AUTODMA,                              \
 738       .bootable = ON_BOARD,                             \
 739       .host_flags       = IDE_HFLAG_SINGLE,             \
 740       .pio_mask         = ATA_PIO4,                     \
 741   }
 742
 743 static ide_pci_device_t scc_chipsets[] __devinitdata = {
 744         /* 0 */ DECLARE_SCC_DEV("sccIDE"),
 745 };
 746
 747 /**
 748  *      scc_init_one    -       pci layer discovery entry
 749  *      @dev: PCI device
 750  *      @id: ident table entry
 751  *
 752  *      Called by the PCI code when it finds an SCC PATA controller.
 753  *      We then use the IDE PCI generic helper to do most of the work.
 754  */
 755
 756 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 757 {
 758         ide_pci_device_t *d = &scc_chipsets[id->driver_data];
 759         return d->init_setup(dev, d);
 760 }
 761
 762 /**
 763  *      scc_remove      -       pci layer remove entry
 764  *      @dev: PCI device
 765  *
 766  *      Called by the PCI code when it removes an SCC PATA controller.
 767  */
 768
 769 static void __devexit scc_remove(struct pci_dev *dev)
 770 {
 771         struct scc_ports *ports = pci_get_drvdata(dev);
 772         ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
 773         unsigned long ctl_base = pci_resource_start(dev, 0);
 774         unsigned long dma_base = pci_resource_start(dev, 1);
 775         unsigned long ctl_size = pci_resource_len(dev, 0);
 776         unsigned long dma_size = pci_resource_len(dev, 1);
 777
 778         if (hwif->dmatable_cpu) {
 779                 pci_free_consistent(hwif->pci_dev,
 780                                     PRD_ENTRIES * PRD_BYTES,
 781                                     hwif->dmatable_cpu,
 782                                     hwif->dmatable_dma);
 783                 hwif->dmatable_cpu = NULL;
 784         }
 785
 786         ide_unregister(hwif->index);
 787
 788         hwif->chipset = ide_unknown;
 789         iounmap((void*)ports->dma);
 790         iounmap((void*)ports->ctl);
 791         release_mem_region(dma_base, dma_size);
 792         release_mem_region(ctl_base, ctl_size);
 793         memset(ports, 0, sizeof(*ports));
 794 }
 795
 796 static struct pci_device_id scc_pci_tbl[] = {
 797         { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 798         { 0, },
 799 };
 800 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 801
 802 static struct pci_driver driver = {
 803         .name = "SCC IDE",
 804         .id_table = scc_pci_tbl,
 805         .probe = scc_init_one,
 806         .remove = scc_remove,
 807 };
 808
 809 static int scc_ide_init(void)
 810 {
 811         return ide_pci_register_driver(&driver);
 812 }
 813
 814 module_init(scc_ide_init);
 815 /* -- No exit code?
 816 static void scc_ide_exit(void)
 817 {
 818         ide_pci_unregister_driver(&driver);
 819 }
 820 module_exit(scc_ide_exit);
 821  */
 822
 823
 824 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 825 MODULE_LICENSE("GPL");