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ide: keep pointer to struct device instead of struct pci_dev in ide_hwif_t
[deliverable/linux.git] / drivers / ide / pci / sgiioc4.c
1 /*
2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 *
16 * For further information regarding this notice, see:
17 *
18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
19 */
20
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/timer.h>
29 #include <linux/mm.h>
30 #include <linux/ioport.h>
31 #include <linux/blkdev.h>
32 #include <linux/scatterlist.h>
33 #include <linux/ioc4.h>
34 #include <asm/io.h>
35
36 #include <linux/ide.h>
37
38 #define DRV_NAME "SGIIOC4"
39
40 /* IOC4 Specific Definitions */
41 #define IOC4_CMD_OFFSET 0x100
42 #define IOC4_CTRL_OFFSET 0x120
43 #define IOC4_DMA_OFFSET 0x140
44 #define IOC4_INTR_OFFSET 0x0
45
46 #define IOC4_TIMING 0x00
47 #define IOC4_DMA_PTR_L 0x01
48 #define IOC4_DMA_PTR_H 0x02
49 #define IOC4_DMA_ADDR_L 0x03
50 #define IOC4_DMA_ADDR_H 0x04
51 #define IOC4_BC_DEV 0x05
52 #define IOC4_BC_MEM 0x06
53 #define IOC4_DMA_CTRL 0x07
54 #define IOC4_DMA_END_ADDR 0x08
55
56 /* Bits in the IOC4 Control/Status Register */
57 #define IOC4_S_DMA_START 0x01
58 #define IOC4_S_DMA_STOP 0x02
59 #define IOC4_S_DMA_DIR 0x04
60 #define IOC4_S_DMA_ACTIVE 0x08
61 #define IOC4_S_DMA_ERROR 0x10
62 #define IOC4_ATA_MEMERR 0x02
63
64 /* Read/Write Directions */
65 #define IOC4_DMA_WRITE 0x04
66 #define IOC4_DMA_READ 0x00
67
68 /* Interrupt Register Offsets */
69 #define IOC4_INTR_REG 0x03
70 #define IOC4_INTR_SET 0x05
71 #define IOC4_INTR_CLEAR 0x07
72
73 #define IOC4_IDE_CACHELINE_SIZE 128
74 #define IOC4_CMD_CTL_BLK_SIZE 0x20
75 #define IOC4_SUPPORTED_FIRMWARE_REV 46
76
77 typedef struct {
78 u32 timing_reg0;
79 u32 timing_reg1;
80 u32 low_mem_ptr;
81 u32 high_mem_ptr;
82 u32 low_mem_addr;
83 u32 high_mem_addr;
84 u32 dev_byte_count;
85 u32 mem_byte_count;
86 u32 status;
87 } ioc4_dma_regs_t;
88
89 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
90 /* IOC4 has only 1 IDE channel */
91 #define IOC4_PRD_BYTES 16
92 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
93
94
95 static void
96 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
97 unsigned long ctrl_port, unsigned long irq_port)
98 {
99 unsigned long reg = data_port;
100 int i;
101
102 /* Registers are word (32 bit) aligned */
103 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
104 hw->io_ports[i] = reg + i * 4;
105
106 if (ctrl_port)
107 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
108
109 if (irq_port)
110 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
111 }
112
113 static void
114 sgiioc4_maskproc(ide_drive_t * drive, int mask)
115 {
116 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
117 (void __iomem *)IDE_CONTROL_REG);
118 }
119
120
121 static int
122 sgiioc4_checkirq(ide_hwif_t * hwif)
123 {
124 unsigned long intr_addr =
125 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
126
127 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
128 return 1;
129
130 return 0;
131 }
132
133 static u8 sgiioc4_INB(unsigned long);
134
135 static int
136 sgiioc4_clearirq(ide_drive_t * drive)
137 {
138 u32 intr_reg;
139 ide_hwif_t *hwif = HWIF(drive);
140 unsigned long other_ir =
141 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
142
143 /* Code to check for PCI error conditions */
144 intr_reg = readl((void __iomem *)other_ir);
145 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
146 /*
147 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
148 * of clearing the interrupt. The first read should clear it
149 * if it is set. The second read should return a "clear" status
150 * if it got cleared. If not, then spin for a bit trying to
151 * clear it.
152 */
153 u8 stat = sgiioc4_INB(IDE_STATUS_REG);
154 int count = 0;
155 stat = sgiioc4_INB(IDE_STATUS_REG);
156 while ((stat & 0x80) && (count++ < 100)) {
157 udelay(1);
158 stat = sgiioc4_INB(IDE_STATUS_REG);
159 }
160
161 if (intr_reg & 0x02) {
162 struct pci_dev *dev = to_pci_dev(hwif->dev);
163 /* Error when transferring DMA data on PCI bus */
164 u32 pci_err_addr_low, pci_err_addr_high,
165 pci_stat_cmd_reg;
166
167 pci_err_addr_low =
168 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
169 pci_err_addr_high =
170 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
171 pci_read_config_dword(dev, PCI_COMMAND,
172 &pci_stat_cmd_reg);
173 printk(KERN_ERR
174 "%s(%s) : PCI Bus Error when doing DMA:"
175 " status-cmd reg is 0x%x\n",
176 __FUNCTION__, drive->name, pci_stat_cmd_reg);
177 printk(KERN_ERR
178 "%s(%s) : PCI Error Address is 0x%x%x\n",
179 __FUNCTION__, drive->name,
180 pci_err_addr_high, pci_err_addr_low);
181 /* Clear the PCI Error indicator */
182 pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
183 }
184
185 /* Clear the Interrupt, Error bits on the IOC4 */
186 writel(0x03, (void __iomem *)other_ir);
187
188 intr_reg = readl((void __iomem *)other_ir);
189 }
190
191 return intr_reg & 3;
192 }
193
194 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
195 {
196 ide_hwif_t *hwif = HWIF(drive);
197 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
198 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
199 unsigned int temp_reg = reg | IOC4_S_DMA_START;
200
201 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
202 }
203
204 static u32
205 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
206 {
207 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
208 u32 ioc4_dma;
209 int count;
210
211 count = 0;
212 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
213 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
214 udelay(1);
215 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
216 }
217 return ioc4_dma;
218 }
219
220 /* Stops the IOC4 DMA Engine */
221 static int
222 sgiioc4_ide_dma_end(ide_drive_t * drive)
223 {
224 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
225 ide_hwif_t *hwif = HWIF(drive);
226 unsigned long dma_base = hwif->dma_base;
227 int dma_stat = 0;
228 unsigned long *ending_dma = ide_get_hwifdata(hwif);
229
230 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
231
232 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
233
234 if (ioc4_dma & IOC4_S_DMA_STOP) {
235 printk(KERN_ERR
236 "%s(%s): IOC4 DMA STOP bit is still 1 :"
237 "ioc4_dma_reg 0x%x\n",
238 __FUNCTION__, drive->name, ioc4_dma);
239 dma_stat = 1;
240 }
241
242 /*
243 * The IOC4 will DMA 1's to the ending dma area to indicate that
244 * previous data DMA is complete. This is necessary because of relaxed
245 * ordering between register reads and DMA writes on the Altix.
246 */
247 while ((cnt++ < 200) && (!valid)) {
248 for (num = 0; num < 16; num++) {
249 if (ending_dma[num]) {
250 valid = 1;
251 break;
252 }
253 }
254 udelay(1);
255 }
256 if (!valid) {
257 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
258 drive->name);
259 dma_stat = 1;
260 }
261
262 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
263 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
264
265 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
266 if (bc_dev > bc_mem + 8) {
267 printk(KERN_ERR
268 "%s(%s): WARNING!! byte_count_dev %d "
269 "!= byte_count_mem %d\n",
270 __FUNCTION__, drive->name, bc_dev, bc_mem);
271 }
272 }
273
274 drive->waiting_for_dma = 0;
275 ide_destroy_dmatable(drive);
276
277 return dma_stat;
278 }
279
280 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
281 {
282 }
283
284 /* returns 1 if dma irq issued, 0 otherwise */
285 static int
286 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
287 {
288 return sgiioc4_checkirq(HWIF(drive));
289 }
290
291 static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
292 {
293 if (!on)
294 sgiioc4_clearirq(drive);
295 }
296
297 static void
298 sgiioc4_resetproc(ide_drive_t * drive)
299 {
300 sgiioc4_ide_dma_end(drive);
301 sgiioc4_clearirq(drive);
302 }
303
304 static void
305 sgiioc4_dma_lost_irq(ide_drive_t * drive)
306 {
307 sgiioc4_resetproc(drive);
308
309 ide_dma_lost_irq(drive);
310 }
311
312 static u8
313 sgiioc4_INB(unsigned long port)
314 {
315 u8 reg = (u8) readb((void __iomem *) port);
316
317 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
318 if (reg & 0x51) { /* Not busy...check for interrupt */
319 unsigned long other_ir = port - 0x110;
320 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
321
322 /* Clear the Interrupt, Error bits on the IOC4 */
323 if (intr_reg & 0x03) {
324 writel(0x03, (void __iomem *) other_ir);
325 intr_reg = (u32) readl((void __iomem *) other_ir);
326 }
327 }
328 }
329
330 return reg;
331 }
332
333 /* Creates a dma map for the scatter-gather list entries */
334 static int __devinit
335 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
336 {
337 struct pci_dev *dev = to_pci_dev(hwif->dev);
338 void __iomem *virt_dma_base;
339 int num_ports = sizeof (ioc4_dma_regs_t);
340 void *pad;
341
342 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
343 dma_base, dma_base + num_ports - 1);
344
345 if (!request_mem_region(dma_base, num_ports, hwif->name)) {
346 printk(KERN_ERR
347 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
348 "ALREADY in use\n",
349 __FUNCTION__, hwif->name, (void *) dma_base,
350 (void *) dma_base + num_ports - 1);
351 return -1;
352 }
353
354 virt_dma_base = ioremap(dma_base, num_ports);
355 if (virt_dma_base == NULL) {
356 printk(KERN_ERR
357 "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
358 __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
359 goto dma_remap_failure;
360 }
361 hwif->dma_base = (unsigned long) virt_dma_base;
362
363 hwif->dmatable_cpu = pci_alloc_consistent(dev,
364 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
365 &hwif->dmatable_dma);
366
367 if (!hwif->dmatable_cpu)
368 goto dma_pci_alloc_failure;
369
370 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
371
372 pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
373 (dma_addr_t *) &(hwif->dma_status));
374
375 if (pad) {
376 ide_set_hwifdata(hwif, pad);
377 return 0;
378 }
379
380 pci_free_consistent(dev, IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
381 hwif->dmatable_cpu, hwif->dmatable_dma);
382 printk(KERN_INFO
383 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
384 __FUNCTION__, hwif->name);
385 printk(KERN_INFO
386 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
387
388 dma_pci_alloc_failure:
389 iounmap(virt_dma_base);
390
391 dma_remap_failure:
392 release_mem_region(dma_base, num_ports);
393
394 return -1;
395 }
396
397 /* Initializes the IOC4 DMA Engine */
398 static void
399 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
400 {
401 u32 ioc4_dma;
402 ide_hwif_t *hwif = HWIF(drive);
403 unsigned long dma_base = hwif->dma_base;
404 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
405 u32 dma_addr, ending_dma_addr;
406
407 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
408
409 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
410 printk(KERN_WARNING
411 "%s(%s):Warning!! DMA from previous transfer was still active\n",
412 __FUNCTION__, drive->name);
413 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
414 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
415
416 if (ioc4_dma & IOC4_S_DMA_STOP)
417 printk(KERN_ERR
418 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
419 __FUNCTION__, drive->name);
420 }
421
422 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
423 if (ioc4_dma & IOC4_S_DMA_ERROR) {
424 printk(KERN_WARNING
425 "%s(%s) : Warning!! - DMA Error during Previous"
426 " transfer | status 0x%x\n",
427 __FUNCTION__, drive->name, ioc4_dma);
428 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
429 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
430
431 if (ioc4_dma & IOC4_S_DMA_STOP)
432 printk(KERN_ERR
433 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
434 __FUNCTION__, drive->name);
435 }
436
437 /* Address of the Scatter Gather List */
438 dma_addr = cpu_to_le32(hwif->dmatable_dma);
439 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
440
441 /* Address of the Ending DMA */
442 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
443 ending_dma_addr = cpu_to_le32(hwif->dma_status);
444 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
445
446 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
447 drive->waiting_for_dma = 1;
448 }
449
450 /* IOC4 Scatter Gather list Format */
451 /* 128 Bit entries to support 64 bit addresses in the future */
452 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
453 /* --------------------------------------------------------------------- */
454 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
455 /* --------------------------------------------------------------------- */
456 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
457 /* --------------------------------------------------------------------- */
458 /* Creates the scatter gather list, DMA Table */
459 static unsigned int
460 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
461 {
462 ide_hwif_t *hwif = HWIF(drive);
463 unsigned int *table = hwif->dmatable_cpu;
464 unsigned int count = 0, i = 1;
465 struct scatterlist *sg;
466
467 hwif->sg_nents = i = ide_build_sglist(drive, rq);
468
469 if (!i)
470 return 0; /* sglist of length Zero */
471
472 sg = hwif->sg_table;
473 while (i && sg_dma_len(sg)) {
474 dma_addr_t cur_addr;
475 int cur_len;
476 cur_addr = sg_dma_address(sg);
477 cur_len = sg_dma_len(sg);
478
479 while (cur_len) {
480 if (count++ >= IOC4_PRD_ENTRIES) {
481 printk(KERN_WARNING
482 "%s: DMA table too small\n",
483 drive->name);
484 goto use_pio_instead;
485 } else {
486 u32 bcount =
487 0x10000 - (cur_addr & 0xffff);
488
489 if (bcount > cur_len)
490 bcount = cur_len;
491
492 /* put the addr, length in
493 * the IOC4 dma-table format */
494 *table = 0x0;
495 table++;
496 *table = cpu_to_be32(cur_addr);
497 table++;
498 *table = 0x0;
499 table++;
500
501 *table = cpu_to_be32(bcount);
502 table++;
503
504 cur_addr += bcount;
505 cur_len -= bcount;
506 }
507 }
508
509 sg = sg_next(sg);
510 i--;
511 }
512
513 if (count) {
514 table--;
515 *table |= cpu_to_be32(0x80000000);
516 return count;
517 }
518
519 use_pio_instead:
520 ide_destroy_dmatable(drive);
521
522 return 0; /* revert to PIO for this request */
523 }
524
525 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
526 {
527 struct request *rq = HWGROUP(drive)->rq;
528 unsigned int count = 0;
529 int ddir;
530
531 if (rq_data_dir(rq))
532 ddir = PCI_DMA_TODEVICE;
533 else
534 ddir = PCI_DMA_FROMDEVICE;
535
536 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
537 /* try PIO instead of DMA */
538 ide_map_sg(drive, rq);
539 return 1;
540 }
541
542 if (rq_data_dir(rq))
543 /* Writes TO the IOC4 FROM Main Memory */
544 ddir = IOC4_DMA_READ;
545 else
546 /* Writes FROM the IOC4 TO Main Memory */
547 ddir = IOC4_DMA_WRITE;
548
549 sgiioc4_configure_for_dma(ddir, drive);
550
551 return 0;
552 }
553
554 static void __devinit
555 ide_init_sgiioc4(ide_hwif_t * hwif)
556 {
557 hwif->mmio = 1;
558 hwif->pio_mask = 0x00;
559 hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */
560 hwif->set_dma_mode = &sgiioc4_set_dma_mode;
561 hwif->selectproc = NULL;/* Use the default routine to select drive */
562 hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
563 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
564 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
565 clear interrupts */
566 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
567 hwif->quirkproc = NULL;
568 hwif->busproc = NULL;
569
570 hwif->INB = &sgiioc4_INB;
571
572 if (hwif->dma_base == 0)
573 return;
574
575 hwif->mwdma_mask = ATA_MWDMA2_ONLY;
576
577 hwif->dma_host_set = &sgiioc4_dma_host_set;
578 hwif->dma_setup = &sgiioc4_ide_dma_setup;
579 hwif->dma_start = &sgiioc4_ide_dma_start;
580 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
581 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
582 hwif->dma_lost_irq = &sgiioc4_dma_lost_irq;
583 hwif->dma_timeout = &ide_dma_timeout;
584 }
585
586 static int __devinit
587 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
588 {
589 unsigned long cmd_base, dma_base, irqport;
590 unsigned long bar0, cmd_phys_base, ctl;
591 void __iomem *virt_base;
592 ide_hwif_t *hwif;
593 int h;
594 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
595 hw_regs_t hw;
596
597 /*
598 * Find an empty HWIF; if none available, return -ENOMEM.
599 */
600 for (h = 0; h < MAX_HWIFS; ++h) {
601 hwif = &ide_hwifs[h];
602 if (hwif->chipset == ide_unknown)
603 break;
604 }
605 if (h == MAX_HWIFS) {
606 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n",
607 DRV_NAME);
608 return -ENOMEM;
609 }
610
611 /* Get the CmdBlk and CtrlBlk Base Registers */
612 bar0 = pci_resource_start(dev, 0);
613 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
614 if (virt_base == NULL) {
615 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
616 DRV_NAME, bar0);
617 return -ENOMEM;
618 }
619 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
620 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
621 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
622 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
623
624 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
625 if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
626 hwif->name)) {
627 printk(KERN_ERR
628 "%s : %s -- ERROR, Addresses "
629 "0x%p to 0x%p ALREADY in use\n",
630 __FUNCTION__, hwif->name, (void *) cmd_phys_base,
631 (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
632 return -ENOMEM;
633 }
634
635 /* Initialize the IO registers */
636 memset(&hw, 0, sizeof(hw));
637 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
638 hw.irq = dev->irq;
639 hw.chipset = ide_pci;
640 hw.dev = &dev->dev;
641 ide_init_port_hw(hwif, &hw);
642
643 hwif->dev = &dev->dev;
644 hwif->channel = 0; /* Single Channel chip */
645
646 /* The IOC4 uses MMIO rather than Port IO. */
647 default_hwif_mmiops(hwif);
648
649 /* Initializing chipset IRQ Registers */
650 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
651
652 if (dma_base == 0 || ide_dma_sgiioc4(hwif, dma_base))
653 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
654 hwif->name, DRV_NAME);
655
656 ide_init_sgiioc4(hwif);
657
658 idx[0] = hwif->index;
659
660 if (ide_device_add(idx))
661 return -EIO;
662
663 return 0;
664 }
665
666 static unsigned int __devinit
667 pci_init_sgiioc4(struct pci_dev *dev)
668 {
669 int ret;
670
671 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
672 DRV_NAME, pci_name(dev), dev->revision);
673
674 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
675 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
676 "firmware is obsolete - please upgrade to "
677 "revision46 or higher\n",
678 DRV_NAME, pci_name(dev));
679 ret = -EAGAIN;
680 goto out;
681 }
682 ret = sgiioc4_ide_setup_pci_device(dev);
683 out:
684 return ret;
685 }
686
687 int
688 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
689 {
690 /* PCI-RT does not bring out IDE connection.
691 * Do not attach to this particular IOC4.
692 */
693 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
694 return 0;
695
696 return pci_init_sgiioc4(idd->idd_pdev);
697 }
698
699 static struct ioc4_submodule ioc4_ide_submodule = {
700 .is_name = "IOC4_ide",
701 .is_owner = THIS_MODULE,
702 .is_probe = ioc4_ide_attach_one,
703 /* .is_remove = ioc4_ide_remove_one, */
704 };
705
706 static int __init ioc4_ide_init(void)
707 {
708 return ioc4_register_submodule(&ioc4_ide_submodule);
709 }
710
711 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
712
713 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
714 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
715 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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