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[deliverable/linux.git] / drivers / ide / pci / sgiioc4.c
1 /*
2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 *
16 * For further information regarding this notice, see:
17 *
18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
19 */
20
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/ioport.h>
29 #include <linux/blkdev.h>
30 #include <linux/scatterlist.h>
31 #include <linux/ioc4.h>
32 #include <asm/io.h>
33
34 #include <linux/ide.h>
35
36 #define DRV_NAME "SGIIOC4"
37
38 /* IOC4 Specific Definitions */
39 #define IOC4_CMD_OFFSET 0x100
40 #define IOC4_CTRL_OFFSET 0x120
41 #define IOC4_DMA_OFFSET 0x140
42 #define IOC4_INTR_OFFSET 0x0
43
44 #define IOC4_TIMING 0x00
45 #define IOC4_DMA_PTR_L 0x01
46 #define IOC4_DMA_PTR_H 0x02
47 #define IOC4_DMA_ADDR_L 0x03
48 #define IOC4_DMA_ADDR_H 0x04
49 #define IOC4_BC_DEV 0x05
50 #define IOC4_BC_MEM 0x06
51 #define IOC4_DMA_CTRL 0x07
52 #define IOC4_DMA_END_ADDR 0x08
53
54 /* Bits in the IOC4 Control/Status Register */
55 #define IOC4_S_DMA_START 0x01
56 #define IOC4_S_DMA_STOP 0x02
57 #define IOC4_S_DMA_DIR 0x04
58 #define IOC4_S_DMA_ACTIVE 0x08
59 #define IOC4_S_DMA_ERROR 0x10
60 #define IOC4_ATA_MEMERR 0x02
61
62 /* Read/Write Directions */
63 #define IOC4_DMA_WRITE 0x04
64 #define IOC4_DMA_READ 0x00
65
66 /* Interrupt Register Offsets */
67 #define IOC4_INTR_REG 0x03
68 #define IOC4_INTR_SET 0x05
69 #define IOC4_INTR_CLEAR 0x07
70
71 #define IOC4_IDE_CACHELINE_SIZE 128
72 #define IOC4_CMD_CTL_BLK_SIZE 0x20
73 #define IOC4_SUPPORTED_FIRMWARE_REV 46
74
75 typedef struct {
76 u32 timing_reg0;
77 u32 timing_reg1;
78 u32 low_mem_ptr;
79 u32 high_mem_ptr;
80 u32 low_mem_addr;
81 u32 high_mem_addr;
82 u32 dev_byte_count;
83 u32 mem_byte_count;
84 u32 status;
85 } ioc4_dma_regs_t;
86
87 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
88 /* IOC4 has only 1 IDE channel */
89 #define IOC4_PRD_BYTES 16
90 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
91
92
93 static void
94 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
95 unsigned long ctrl_port, unsigned long irq_port)
96 {
97 unsigned long reg = data_port;
98 int i;
99
100 /* Registers are word (32 bit) aligned */
101 for (i = 0; i <= 7; i++)
102 hw->io_ports_array[i] = reg + i * 4;
103
104 if (ctrl_port)
105 hw->io_ports.ctl_addr = ctrl_port;
106
107 if (irq_port)
108 hw->io_ports.irq_addr = irq_port;
109 }
110
111 static void
112 sgiioc4_maskproc(ide_drive_t * drive, int mask)
113 {
114 writeb(ATA_DEVCTL_OBS | (mask ? 2 : 0),
115 (void __iomem *)drive->hwif->io_ports.ctl_addr);
116 }
117
118 static int
119 sgiioc4_checkirq(ide_hwif_t * hwif)
120 {
121 unsigned long intr_addr =
122 hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
123
124 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
125 return 1;
126
127 return 0;
128 }
129
130 static u8 sgiioc4_INB(unsigned long);
131
132 static int
133 sgiioc4_clearirq(ide_drive_t * drive)
134 {
135 u32 intr_reg;
136 ide_hwif_t *hwif = HWIF(drive);
137 struct ide_io_ports *io_ports = &hwif->io_ports;
138 unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
139
140 /* Code to check for PCI error conditions */
141 intr_reg = readl((void __iomem *)other_ir);
142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
143 /*
144 * Using sgiioc4_INB to read the Status register has a side
145 * effect of clearing the interrupt. The first read should
146 * clear it if it is set. The second read should return
147 * a "clear" status if it got cleared. If not, then spin
148 * for a bit trying to clear it.
149 */
150 u8 stat = sgiioc4_INB(io_ports->status_addr);
151 int count = 0;
152 stat = sgiioc4_INB(io_ports->status_addr);
153 while ((stat & 0x80) && (count++ < 100)) {
154 udelay(1);
155 stat = sgiioc4_INB(io_ports->status_addr);
156 }
157
158 if (intr_reg & 0x02) {
159 struct pci_dev *dev = to_pci_dev(hwif->dev);
160 /* Error when transferring DMA data on PCI bus */
161 u32 pci_err_addr_low, pci_err_addr_high,
162 pci_stat_cmd_reg;
163
164 pci_err_addr_low =
165 readl((void __iomem *)io_ports->irq_addr);
166 pci_err_addr_high =
167 readl((void __iomem *)(io_ports->irq_addr + 4));
168 pci_read_config_dword(dev, PCI_COMMAND,
169 &pci_stat_cmd_reg);
170 printk(KERN_ERR
171 "%s(%s) : PCI Bus Error when doing DMA:"
172 " status-cmd reg is 0x%x\n",
173 __func__, drive->name, pci_stat_cmd_reg);
174 printk(KERN_ERR
175 "%s(%s) : PCI Error Address is 0x%x%x\n",
176 __func__, drive->name,
177 pci_err_addr_high, pci_err_addr_low);
178 /* Clear the PCI Error indicator */
179 pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
180 }
181
182 /* Clear the Interrupt, Error bits on the IOC4 */
183 writel(0x03, (void __iomem *)other_ir);
184
185 intr_reg = readl((void __iomem *)other_ir);
186 }
187
188 return intr_reg & 3;
189 }
190
191 static void sgiioc4_dma_start(ide_drive_t *drive)
192 {
193 ide_hwif_t *hwif = HWIF(drive);
194 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
195 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
196 unsigned int temp_reg = reg | IOC4_S_DMA_START;
197
198 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
199 }
200
201 static u32
202 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
203 {
204 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
205 u32 ioc4_dma;
206 int count;
207
208 count = 0;
209 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
210 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
211 udelay(1);
212 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
213 }
214 return ioc4_dma;
215 }
216
217 /* Stops the IOC4 DMA Engine */
218 static int sgiioc4_dma_end(ide_drive_t *drive)
219 {
220 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
221 ide_hwif_t *hwif = HWIF(drive);
222 unsigned long dma_base = hwif->dma_base;
223 int dma_stat = 0;
224 unsigned long *ending_dma = ide_get_hwifdata(hwif);
225
226 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
227
228 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
229
230 if (ioc4_dma & IOC4_S_DMA_STOP) {
231 printk(KERN_ERR
232 "%s(%s): IOC4 DMA STOP bit is still 1 :"
233 "ioc4_dma_reg 0x%x\n",
234 __func__, drive->name, ioc4_dma);
235 dma_stat = 1;
236 }
237
238 /*
239 * The IOC4 will DMA 1's to the ending dma area to indicate that
240 * previous data DMA is complete. This is necessary because of relaxed
241 * ordering between register reads and DMA writes on the Altix.
242 */
243 while ((cnt++ < 200) && (!valid)) {
244 for (num = 0; num < 16; num++) {
245 if (ending_dma[num]) {
246 valid = 1;
247 break;
248 }
249 }
250 udelay(1);
251 }
252 if (!valid) {
253 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __func__,
254 drive->name);
255 dma_stat = 1;
256 }
257
258 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
259 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
260
261 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
262 if (bc_dev > bc_mem + 8) {
263 printk(KERN_ERR
264 "%s(%s): WARNING!! byte_count_dev %d "
265 "!= byte_count_mem %d\n",
266 __func__, drive->name, bc_dev, bc_mem);
267 }
268 }
269
270 drive->waiting_for_dma = 0;
271 ide_destroy_dmatable(drive);
272
273 return dma_stat;
274 }
275
276 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
277 {
278 }
279
280 /* returns 1 if dma irq issued, 0 otherwise */
281 static int sgiioc4_dma_test_irq(ide_drive_t *drive)
282 {
283 return sgiioc4_checkirq(HWIF(drive));
284 }
285
286 static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
287 {
288 if (!on)
289 sgiioc4_clearirq(drive);
290 }
291
292 static void
293 sgiioc4_resetproc(ide_drive_t * drive)
294 {
295 sgiioc4_dma_end(drive);
296 sgiioc4_clearirq(drive);
297 }
298
299 static void
300 sgiioc4_dma_lost_irq(ide_drive_t * drive)
301 {
302 sgiioc4_resetproc(drive);
303
304 ide_dma_lost_irq(drive);
305 }
306
307 static u8
308 sgiioc4_INB(unsigned long port)
309 {
310 u8 reg = (u8) readb((void __iomem *) port);
311
312 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
313 if (reg & 0x51) { /* Not busy...check for interrupt */
314 unsigned long other_ir = port - 0x110;
315 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
316
317 /* Clear the Interrupt, Error bits on the IOC4 */
318 if (intr_reg & 0x03) {
319 writel(0x03, (void __iomem *) other_ir);
320 intr_reg = (u32) readl((void __iomem *) other_ir);
321 }
322 }
323 }
324
325 return reg;
326 }
327
328 /* Creates a dma map for the scatter-gather list entries */
329 static int __devinit
330 ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
331 {
332 struct pci_dev *dev = to_pci_dev(hwif->dev);
333 unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
334 void __iomem *virt_dma_base;
335 int num_ports = sizeof (ioc4_dma_regs_t);
336 void *pad;
337
338 if (dma_base == 0)
339 return -1;
340
341 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
342 dma_base, dma_base + num_ports - 1);
343
344 if (!request_mem_region(dma_base, num_ports, hwif->name)) {
345 printk(KERN_ERR
346 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
347 "ALREADY in use\n",
348 __func__, hwif->name, (void *) dma_base,
349 (void *) dma_base + num_ports - 1);
350 return -1;
351 }
352
353 virt_dma_base = ioremap(dma_base, num_ports);
354 if (virt_dma_base == NULL) {
355 printk(KERN_ERR
356 "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
357 __func__, hwif->name, dma_base, dma_base + num_ports - 1);
358 goto dma_remap_failure;
359 }
360 hwif->dma_base = (unsigned long) virt_dma_base;
361
362 hwif->dmatable_cpu = pci_alloc_consistent(dev,
363 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
364 &hwif->dmatable_dma);
365
366 if (!hwif->dmatable_cpu)
367 goto dma_pci_alloc_failure;
368
369 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
370
371 pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
372 (dma_addr_t *)&hwif->extra_base);
373 if (pad) {
374 ide_set_hwifdata(hwif, pad);
375 return 0;
376 }
377
378 pci_free_consistent(dev, IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
379 hwif->dmatable_cpu, hwif->dmatable_dma);
380 printk(KERN_INFO
381 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
382 __func__, hwif->name);
383 printk(KERN_INFO
384 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
385
386 dma_pci_alloc_failure:
387 iounmap(virt_dma_base);
388
389 dma_remap_failure:
390 release_mem_region(dma_base, num_ports);
391
392 return -1;
393 }
394
395 /* Initializes the IOC4 DMA Engine */
396 static void
397 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
398 {
399 u32 ioc4_dma;
400 ide_hwif_t *hwif = HWIF(drive);
401 unsigned long dma_base = hwif->dma_base;
402 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
403 u32 dma_addr, ending_dma_addr;
404
405 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
406
407 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
408 printk(KERN_WARNING
409 "%s(%s):Warning!! DMA from previous transfer was still active\n",
410 __func__, drive->name);
411 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
412 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
413
414 if (ioc4_dma & IOC4_S_DMA_STOP)
415 printk(KERN_ERR
416 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
417 __func__, drive->name);
418 }
419
420 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
421 if (ioc4_dma & IOC4_S_DMA_ERROR) {
422 printk(KERN_WARNING
423 "%s(%s) : Warning!! - DMA Error during Previous"
424 " transfer | status 0x%x\n",
425 __func__, drive->name, ioc4_dma);
426 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
427 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
428
429 if (ioc4_dma & IOC4_S_DMA_STOP)
430 printk(KERN_ERR
431 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
432 __func__, drive->name);
433 }
434
435 /* Address of the Scatter Gather List */
436 dma_addr = cpu_to_le32(hwif->dmatable_dma);
437 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
438
439 /* Address of the Ending DMA */
440 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
441 ending_dma_addr = cpu_to_le32(hwif->extra_base);
442 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
443
444 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
445 drive->waiting_for_dma = 1;
446 }
447
448 /* IOC4 Scatter Gather list Format */
449 /* 128 Bit entries to support 64 bit addresses in the future */
450 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
451 /* --------------------------------------------------------------------- */
452 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
453 /* --------------------------------------------------------------------- */
454 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
455 /* --------------------------------------------------------------------- */
456 /* Creates the scatter gather list, DMA Table */
457 static unsigned int
458 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
459 {
460 ide_hwif_t *hwif = HWIF(drive);
461 unsigned int *table = hwif->dmatable_cpu;
462 unsigned int count = 0, i = 1;
463 struct scatterlist *sg;
464
465 hwif->sg_nents = i = ide_build_sglist(drive, rq);
466
467 if (!i)
468 return 0; /* sglist of length Zero */
469
470 sg = hwif->sg_table;
471 while (i && sg_dma_len(sg)) {
472 dma_addr_t cur_addr;
473 int cur_len;
474 cur_addr = sg_dma_address(sg);
475 cur_len = sg_dma_len(sg);
476
477 while (cur_len) {
478 if (count++ >= IOC4_PRD_ENTRIES) {
479 printk(KERN_WARNING
480 "%s: DMA table too small\n",
481 drive->name);
482 goto use_pio_instead;
483 } else {
484 u32 bcount =
485 0x10000 - (cur_addr & 0xffff);
486
487 if (bcount > cur_len)
488 bcount = cur_len;
489
490 /* put the addr, length in
491 * the IOC4 dma-table format */
492 *table = 0x0;
493 table++;
494 *table = cpu_to_be32(cur_addr);
495 table++;
496 *table = 0x0;
497 table++;
498
499 *table = cpu_to_be32(bcount);
500 table++;
501
502 cur_addr += bcount;
503 cur_len -= bcount;
504 }
505 }
506
507 sg = sg_next(sg);
508 i--;
509 }
510
511 if (count) {
512 table--;
513 *table |= cpu_to_be32(0x80000000);
514 return count;
515 }
516
517 use_pio_instead:
518 ide_destroy_dmatable(drive);
519
520 return 0; /* revert to PIO for this request */
521 }
522
523 static int sgiioc4_dma_setup(ide_drive_t *drive)
524 {
525 struct request *rq = HWGROUP(drive)->rq;
526 unsigned int count = 0;
527 int ddir;
528
529 if (rq_data_dir(rq))
530 ddir = PCI_DMA_TODEVICE;
531 else
532 ddir = PCI_DMA_FROMDEVICE;
533
534 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
535 /* try PIO instead of DMA */
536 ide_map_sg(drive, rq);
537 return 1;
538 }
539
540 if (rq_data_dir(rq))
541 /* Writes TO the IOC4 FROM Main Memory */
542 ddir = IOC4_DMA_READ;
543 else
544 /* Writes FROM the IOC4 TO Main Memory */
545 ddir = IOC4_DMA_WRITE;
546
547 sgiioc4_configure_for_dma(ddir, drive);
548
549 return 0;
550 }
551
552 static const struct ide_port_ops sgiioc4_port_ops = {
553 .set_dma_mode = sgiioc4_set_dma_mode,
554 /* reset DMA engine, clear IRQs */
555 .resetproc = sgiioc4_resetproc,
556 /* mask on/off NIEN register */
557 .maskproc = sgiioc4_maskproc,
558 };
559
560 static const struct ide_dma_ops sgiioc4_dma_ops = {
561 .dma_host_set = sgiioc4_dma_host_set,
562 .dma_setup = sgiioc4_dma_setup,
563 .dma_start = sgiioc4_dma_start,
564 .dma_end = sgiioc4_dma_end,
565 .dma_test_irq = sgiioc4_dma_test_irq,
566 .dma_lost_irq = sgiioc4_dma_lost_irq,
567 .dma_timeout = ide_dma_timeout,
568 };
569
570 static const struct ide_port_info sgiioc4_port_info __devinitdata = {
571 .name = DRV_NAME,
572 .chipset = ide_pci,
573 .init_dma = ide_dma_sgiioc4,
574 .port_ops = &sgiioc4_port_ops,
575 .dma_ops = &sgiioc4_dma_ops,
576 .host_flags = IDE_HFLAG_MMIO,
577 .mwdma_mask = ATA_MWDMA2_ONLY,
578 };
579
580 static int __devinit
581 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
582 {
583 unsigned long cmd_base, irqport;
584 unsigned long bar0, cmd_phys_base, ctl;
585 void __iomem *virt_base;
586 ide_hwif_t *hwif;
587 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
588 hw_regs_t hw;
589 struct ide_port_info d = sgiioc4_port_info;
590
591 /* Get the CmdBlk and CtrlBlk Base Registers */
592 bar0 = pci_resource_start(dev, 0);
593 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
594 if (virt_base == NULL) {
595 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
596 DRV_NAME, bar0);
597 return -ENOMEM;
598 }
599 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
600 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
601 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
602
603 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
604 if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
605 DRV_NAME)) {
606 printk(KERN_ERR
607 "%s : %s -- ERROR, Addresses "
608 "0x%p to 0x%p ALREADY in use\n",
609 __func__, DRV_NAME, (void *) cmd_phys_base,
610 (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
611 return -ENOMEM;
612 }
613
614 /* Initialize the IO registers */
615 memset(&hw, 0, sizeof(hw));
616 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
617 hw.irq = dev->irq;
618 hw.chipset = ide_pci;
619 hw.dev = &dev->dev;
620
621 hwif = ide_find_port_slot(&d);
622 if (hwif == NULL)
623 goto err;
624
625 ide_init_port_hw(hwif, &hw);
626
627 /* The IOC4 uses MMIO rather than Port IO. */
628 default_hwif_mmiops(hwif);
629
630 /* Initializing chipset IRQ Registers */
631 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
632
633 hwif->INB = &sgiioc4_INB;
634
635 idx[0] = hwif->index;
636
637 if (ide_device_add(idx, &d))
638 return -EIO;
639
640 return 0;
641 err:
642 release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE);
643 iounmap(virt_base);
644 return -ENOMEM;
645 }
646
647 static unsigned int __devinit
648 pci_init_sgiioc4(struct pci_dev *dev)
649 {
650 int ret;
651
652 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
653 DRV_NAME, pci_name(dev), dev->revision);
654
655 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
656 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
657 "firmware is obsolete - please upgrade to "
658 "revision46 or higher\n",
659 DRV_NAME, pci_name(dev));
660 ret = -EAGAIN;
661 goto out;
662 }
663 ret = sgiioc4_ide_setup_pci_device(dev);
664 out:
665 return ret;
666 }
667
668 int
669 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
670 {
671 /* PCI-RT does not bring out IDE connection.
672 * Do not attach to this particular IOC4.
673 */
674 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
675 return 0;
676
677 return pci_init_sgiioc4(idd->idd_pdev);
678 }
679
680 static struct ioc4_submodule ioc4_ide_submodule = {
681 .is_name = "IOC4_ide",
682 .is_owner = THIS_MODULE,
683 .is_probe = ioc4_ide_attach_one,
684 /* .is_remove = ioc4_ide_remove_one, */
685 };
686
687 static int __init ioc4_ide_init(void)
688 {
689 return ioc4_register_submodule(&ioc4_ide_submodule);
690 }
691
692 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
693
694 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
695 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
696 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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