drivers/ide/pci/slc90e66.c

   1 /*
   2  *  linux/drivers/ide/pci/slc90e66.c    Version 0.17    Aug 2, 2007
   3  *
   4  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
   8  * but this keeps the ISA-Bridge and slots alive.
   9  *
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/ioport.h>
  16 #include <linux/pci.h>
  17 #include <linux/hdreg.h>
  18 #include <linux/ide.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21
  22 #include <asm/io.h>
  23
  24 static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
  25 {
  26         ide_hwif_t *hwif        = HWIF(drive);
  27         struct pci_dev *dev     = hwif->pci_dev;
  28         int is_slave            = drive->dn & 1;
  29         int master_port         = hwif->channel ? 0x42 : 0x40;
  30         int slave_port          = 0x44;
  31         unsigned long flags;
  32         u16 master_data;
  33         u8 slave_data;
  34         int control = 0;
  35                                      /* ISP  RTC */
  36         static const u8 timings[][2]= {
  37                                         { 0, 0 },
  38                                         { 0, 0 },
  39                                         { 1, 0 },
  40                                         { 2, 1 },
  41                                         { 2, 3 }, };
  42
  43         spin_lock_irqsave(&ide_lock, flags);
  44         pci_read_config_word(dev, master_port, &master_data);
  45
  46         if (pio > 1)
  47                 control |= 1;   /* Programmable timing on */
  48         if (drive->media == ide_disk)
  49                 control |= 4;   /* Prefetch, post write */
  50         if (pio > 2)
  51                 control |= 2;   /* IORDY */
  52         if (is_slave) {
  53                 master_data |=  0x4000;
  54                 master_data &= ~0x0070;
  55                 if (pio > 1) {
  56                         /* Set PPE, IE and TIME */
  57                         master_data |= control << 4;
  58                 }
  59                 pci_read_config_byte(dev, slave_port, &slave_data);
  60                 slave_data &= hwif->channel ? 0x0f : 0xf0;
  61                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  62                                (hwif->channel ? 4 : 0);
  63         } else {
  64                 master_data &= ~0x3307;
  65                 if (pio > 1) {
  66                         /* enable PPE, IE and TIME */
  67                         master_data |= control;
  68                 }
  69                 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  70         }
  71         pci_write_config_word(dev, master_port, master_data);
  72         if (is_slave)
  73                 pci_write_config_byte(dev, slave_port, slave_data);
  74         spin_unlock_irqrestore(&ide_lock, flags);
  75 }
  76
  77 static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
  78 {
  79         ide_hwif_t *hwif        = HWIF(drive);
  80         struct pci_dev *dev     = hwif->pci_dev;
  81         u8 maslave              = hwif->channel ? 0x42 : 0x40;
  82         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
  83         int u_speed = 0, u_flag = 1 << drive->dn;
  84         u16                     reg4042, reg44, reg48, reg4a;
  85         u8                      pio;
  86
  87         pci_read_config_word(dev, maslave, &reg4042);
  88         sitre = (reg4042 & 0x4000) ? 1 : 0;
  89         pci_read_config_word(dev, 0x44, &reg44);
  90         pci_read_config_word(dev, 0x48, &reg48);
  91         pci_read_config_word(dev, 0x4a, &reg4a);
  92
  93         switch(speed) {
  94                 case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
  95                 case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
  96                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
  97                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
  98                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
  99                 case XFER_MW_DMA_2:
 100                 case XFER_MW_DMA_1:
 101                 case XFER_SW_DMA_2:     break;
 102                 default:                return;
 103         }
 104
 105         if (speed >= XFER_UDMA_0) {
 106                 if (!(reg48 & u_flag))
 107                         pci_write_config_word(dev, 0x48, reg48|u_flag);
 108                 /* FIXME: (reg4a & a_speed) ? */
 109                 if ((reg4a & u_speed) != u_speed) {
 110                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 111                         pci_read_config_word(dev, 0x4a, &reg4a);
 112                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
 113                 }
 114
 115                 pio = 4;
 116         } else {
 117                 const u8 mwdma_to_pio[] = { 0, 3, 4 };
 118
 119                 if (reg48 & u_flag)
 120                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
 121                 if (reg4a & a_speed)
 122                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 123
 124                 if (speed >= XFER_MW_DMA_0)
 125                         pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
 126                 else
 127                         pio = 2; /* only SWDMA2 is allowed */
 128         }
 129
 130         slc90e66_set_pio_mode(drive, pio);
 131 }
 132
 133 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
 134 {
 135         u8 reg47 = 0;
 136         u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */
 137
 138         hwif->autodma = 0;
 139
 140         if (!hwif->irq)
 141                 hwif->irq = hwif->channel ? 15 : 14;
 142
 143         hwif->set_pio_mode = &slc90e66_set_pio_mode;
 144         hwif->set_dma_mode = &slc90e66_set_dma_mode;
 145
 146         pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
 147
 148         hwif->drives[0].autotune = 1;
 149         hwif->drives[1].autotune = 1;
 150
 151         if (hwif->dma_base == 0)
 152                 return;
 153
 154         hwif->atapi_dma = 1;
 155         hwif->ultra_mask = 0x1f;
 156         hwif->mwdma_mask = 0x06;
 157         hwif->swdma_mask = 0x04;
 158
 159         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 160                 /* bit[0(1)]: 0:80, 1:40 */
 161                 hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 162
 163         if (!noautodma)
 164                 hwif->autodma = 1;
 165         hwif->drives[0].autodma = hwif->autodma;
 166         hwif->drives[1].autodma = hwif->autodma;
 167 }
 168
 169 static ide_pci_device_t slc90e66_chipset __devinitdata = {
 170         .name           = "SLC90E66",
 171         .init_hwif      = init_hwif_slc90e66,
 172         .autodma        = AUTODMA,
 173         .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
 174         .bootable       = ON_BOARD,
 175         .pio_mask       = ATA_PIO4,
 176 };
 177
 178 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 179 {
 180         return ide_setup_pci_device(dev, &slc90e66_chipset);
 181 }
 182
 183 static struct pci_device_id slc90e66_pci_tbl[] = {
 184         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
 185         { 0, },
 186 };
 187 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
 188
 189 static struct pci_driver driver = {
 190         .name           = "SLC90e66_IDE",
 191         .id_table       = slc90e66_pci_tbl,
 192         .probe          = slc90e66_init_one,
 193 };
 194
 195 static int __init slc90e66_ide_init(void)
 196 {
 197         return ide_pci_register_driver(&driver);
 198 }
 199
 200 module_init(slc90e66_ide_init);
 201
 202 MODULE_AUTHOR("Andre Hedrick");
 203 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
 204 MODULE_LICENSE("GPL");