2 * Support for IDE interfaces on PowerMacs.
4 * These IDE interfaces are memory-mapped and have a DBDMA channel
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
8 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * Some code taken from drivers/ide/ide-dma.c:
17 * Copyright (c) 1995-1998 Mark Lord
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/pci.h>
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #include <linux/scatterlist.h>
39 #include <asm/dbdma.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
43 #include <asm/pmac_feature.h>
44 #include <asm/sections.h>
48 #include <asm/mediabay.h>
51 #define DRV_NAME "ide-pmac"
55 #define DMA_WAIT_TIMEOUT 50
57 typedef struct pmac_ide_hwif
{
58 unsigned long regbase
;
62 unsigned mediabay
: 1;
63 unsigned broken_dma
: 1;
64 unsigned broken_dma_warn
: 1;
65 struct device_node
* node
;
66 struct macio_dev
*mdev
;
68 volatile u32 __iomem
* *kauai_fcr
;
69 /* Those fields are duplicating what is in hwif. We currently
70 * can't use the hwif ones because of some assumptions that are
71 * beeing done by the generic code about the kind of dma controller
72 * and format of the dma table. This will have to be fixed though.
74 volatile struct dbdma_regs __iomem
* dma_regs
;
75 struct dbdma_cmd
* dma_table_cpu
;
79 controller_ohare
, /* OHare based */
80 controller_heathrow
, /* Heathrow/Paddington */
81 controller_kl_ata3
, /* KeyLargo ATA-3 */
82 controller_kl_ata4
, /* KeyLargo ATA-4 */
83 controller_un_ata6
, /* UniNorth2 ATA-6 */
84 controller_k2_ata6
, /* K2 ATA-6 */
85 controller_sh_ata6
, /* Shasta ATA-6 */
88 static const char* model_name
[] = {
89 "OHare ATA", /* OHare based */
90 "Heathrow ATA", /* Heathrow/Paddington */
91 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
92 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
93 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
94 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
95 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
99 * Extra registers, both 32-bit little-endian
101 #define IDE_TIMING_CONFIG 0x200
102 #define IDE_INTERRUPT 0x300
104 /* Kauai (U2) ATA has different register setup */
105 #define IDE_KAUAI_PIO_CONFIG 0x200
106 #define IDE_KAUAI_ULTRA_CONFIG 0x210
107 #define IDE_KAUAI_POLL_CONFIG 0x220
110 * Timing configuration register definitions
113 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
114 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
115 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
116 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
117 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
119 /* 133Mhz cell, found in shasta.
120 * See comments about 100 Mhz Uninorth 2...
121 * Note that PIO_MASK and MDMA_MASK seem to overlap
123 #define TR_133_PIOREG_PIO_MASK 0xff000fff
124 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
125 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
126 #define TR_133_UDMAREG_UDMA_EN 0x00000001
128 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
129 * this one yet, it appears as a pci device (106b/0033) on uninorth
130 * internal PCI bus and it's clock is controlled like gem or fw. It
131 * appears to be an evolution of keylargo ATA4 with a timing register
132 * extended to 2 32bits registers and a similar DBDMA channel. Other
133 * registers seem to exist but I can't tell much about them.
135 * So far, I'm using pre-calculated tables for this extracted from
136 * the values used by the MacOS X driver.
138 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
139 * register controls the UDMA timings. At least, it seems bit 0
140 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
141 * cycle time in units of 10ns. Bits 8..15 are used by I don't
142 * know their meaning yet
144 #define TR_100_PIOREG_PIO_MASK 0xff000fff
145 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
146 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
147 #define TR_100_UDMAREG_UDMA_EN 0x00000001
150 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
151 * 40 connector cable and to 4 on 80 connector one.
152 * Clock unit is 15ns (66Mhz)
154 * 3 Values can be programmed:
155 * - Write data setup, which appears to match the cycle time. They
156 * also call it DIOW setup.
157 * - Ready to pause time (from spec)
158 * - Address setup. That one is weird. I don't see where exactly
159 * it fits in UDMA cycles, I got it's name from an obscure piece
160 * of commented out code in Darwin. They leave it to 0, we do as
161 * well, despite a comment that would lead to think it has a
163 * Apple also add 60ns to the write data setup (or cycle time ?) on
166 #define TR_66_UDMA_MASK 0xfff00000
167 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
168 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
169 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
170 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
171 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
172 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
173 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
174 #define TR_66_MDMA_MASK 0x000ffc00
175 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
176 #define TR_66_MDMA_RECOVERY_SHIFT 15
177 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
178 #define TR_66_MDMA_ACCESS_SHIFT 10
179 #define TR_66_PIO_MASK 0x000003ff
180 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
181 #define TR_66_PIO_RECOVERY_SHIFT 5
182 #define TR_66_PIO_ACCESS_MASK 0x0000001f
183 #define TR_66_PIO_ACCESS_SHIFT 0
185 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
186 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
188 * The access time and recovery time can be programmed. Some older
189 * Darwin code base limit OHare to 150ns cycle time. I decided to do
190 * the same here fore safety against broken old hardware ;)
191 * The HalfTick bit, when set, adds half a clock (15ns) to the access
192 * time and removes one from recovery. It's not supported on KeyLargo
193 * implementation afaik. The E bit appears to be set for PIO mode 0 and
194 * is used to reach long timings used in this mode.
196 #define TR_33_MDMA_MASK 0x003ff800
197 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
198 #define TR_33_MDMA_RECOVERY_SHIFT 16
199 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
200 #define TR_33_MDMA_ACCESS_SHIFT 11
201 #define TR_33_MDMA_HALFTICK 0x00200000
202 #define TR_33_PIO_MASK 0x000007ff
203 #define TR_33_PIO_E 0x00000400
204 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
205 #define TR_33_PIO_RECOVERY_SHIFT 5
206 #define TR_33_PIO_ACCESS_MASK 0x0000001f
207 #define TR_33_PIO_ACCESS_SHIFT 0
210 * Interrupt register definitions
212 #define IDE_INTR_DMA 0x80000000
213 #define IDE_INTR_DEVICE 0x40000000
216 * FCR Register on Kauai. Not sure what bit 0x4 is ...
218 #define KAUAI_FCR_UATA_MAGIC 0x00000004
219 #define KAUAI_FCR_UATA_RESET_N 0x00000002
220 #define KAUAI_FCR_UATA_ENABLE 0x00000001
222 /* Rounded Multiword DMA timings
224 * I gave up finding a generic formula for all controller
225 * types and instead, built tables based on timing values
226 * used by Apple in Darwin's implementation.
228 struct mdma_timings_t
{
234 struct mdma_timings_t mdma_timings_33
[] =
247 struct mdma_timings_t mdma_timings_33k
[] =
260 struct mdma_timings_t mdma_timings_66
[] =
273 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
275 int addrSetup
; /* ??? */
278 } kl66_udma_timings
[] =
280 { 0, 180, 120 }, /* Mode 0 */
281 { 0, 150, 90 }, /* 1 */
282 { 0, 120, 60 }, /* 2 */
283 { 0, 90, 45 }, /* 3 */
284 { 0, 90, 30 } /* 4 */
287 /* UniNorth 2 ATA/100 timings */
288 struct kauai_timing
{
293 static struct kauai_timing kauai_pio_timings
[] =
295 { 930 , 0x08000fff },
296 { 600 , 0x08000a92 },
297 { 383 , 0x0800060f },
298 { 360 , 0x08000492 },
299 { 330 , 0x0800048f },
300 { 300 , 0x080003cf },
301 { 270 , 0x080003cc },
302 { 240 , 0x0800038b },
303 { 239 , 0x0800030c },
304 { 180 , 0x05000249 },
305 { 120 , 0x04000148 },
309 static struct kauai_timing kauai_mdma_timings
[] =
311 { 1260 , 0x00fff000 },
312 { 480 , 0x00618000 },
313 { 360 , 0x00492000 },
314 { 270 , 0x0038e000 },
315 { 240 , 0x0030c000 },
316 { 210 , 0x002cb000 },
317 { 180 , 0x00249000 },
318 { 150 , 0x00209000 },
319 { 120 , 0x00148000 },
323 static struct kauai_timing kauai_udma_timings
[] =
325 { 120 , 0x000070c0 },
334 static struct kauai_timing shasta_pio_timings
[] =
336 { 930 , 0x08000fff },
337 { 600 , 0x0A000c97 },
338 { 383 , 0x07000712 },
339 { 360 , 0x040003cd },
340 { 330 , 0x040003cd },
341 { 300 , 0x040003cd },
342 { 270 , 0x040003cd },
343 { 240 , 0x040003cd },
344 { 239 , 0x040003cd },
345 { 180 , 0x0400028b },
346 { 120 , 0x0400010a },
350 static struct kauai_timing shasta_mdma_timings
[] =
352 { 1260 , 0x00fff000 },
353 { 480 , 0x00820800 },
354 { 360 , 0x00820800 },
355 { 270 , 0x00820800 },
356 { 240 , 0x00820800 },
357 { 210 , 0x00820800 },
358 { 180 , 0x00820800 },
359 { 150 , 0x0028b000 },
360 { 120 , 0x001ca000 },
364 static struct kauai_timing shasta_udma133_timings
[] =
366 { 120 , 0x00035901, },
367 { 90 , 0x000348b1, },
368 { 60 , 0x00033881, },
369 { 45 , 0x00033861, },
370 { 30 , 0x00033841, },
371 { 20 , 0x00033031, },
372 { 15 , 0x00033021, },
378 kauai_lookup_timing(struct kauai_timing
* table
, int cycle_time
)
382 for (i
=0; table
[i
].cycle_time
; i
++)
383 if (cycle_time
> table
[i
+1].cycle_time
)
384 return table
[i
].timing_reg
;
389 /* allow up to 256 DBDMA commands per xfer */
390 #define MAX_DCMDS 256
393 * Wait 1s for disk to answer on IDE bus after a hard reset
394 * of the device (via GPIO/FCR).
396 * Some devices seem to "pollute" the bus even after dropping
397 * the BSY bit (typically some combo drives slave on the UDMA
398 * bus) after a hard reset. Since we hard reset all drives on
399 * KeyLargo ATA66, we have to keep that delay around. I may end
400 * up not hard resetting anymore on these and keep the delay only
401 * for older interfaces instead (we have to reset when coming
402 * from MacOS...) --BenH.
404 #define IDE_WAKEUP_DELAY (1*HZ)
406 static int pmac_ide_init_dma(ide_hwif_t
*, const struct ide_port_info
*);
407 static void pmac_ide_selectproc(ide_drive_t
*drive
);
408 static void pmac_ide_kauai_selectproc(ide_drive_t
*drive
);
410 #define PMAC_IDE_REG(x) \
411 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
414 * Apply the timings of the proper unit (master/slave) to the shared
415 * timing register when selecting that unit. This version is for
416 * ASICs with a single timing register
419 pmac_ide_selectproc(ide_drive_t
*drive
)
421 ide_hwif_t
*hwif
= drive
->hwif
;
422 pmac_ide_hwif_t
*pmif
=
423 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
426 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
428 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
429 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
433 * Apply the timings of the proper unit (master/slave) to the shared
434 * timing register when selecting that unit. This version is for
435 * ASICs with a dual timing register (Kauai)
438 pmac_ide_kauai_selectproc(ide_drive_t
*drive
)
440 ide_hwif_t
*hwif
= drive
->hwif
;
441 pmac_ide_hwif_t
*pmif
=
442 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
445 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
446 writel(pmif
->timings
[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
448 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
449 writel(pmif
->timings
[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
451 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
455 * Force an update of controller timing values for a given drive
458 pmac_ide_do_update_timings(ide_drive_t
*drive
)
460 ide_hwif_t
*hwif
= drive
->hwif
;
461 pmac_ide_hwif_t
*pmif
=
462 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
464 if (pmif
->kind
== controller_sh_ata6
||
465 pmif
->kind
== controller_un_ata6
||
466 pmif
->kind
== controller_k2_ata6
)
467 pmac_ide_kauai_selectproc(drive
);
469 pmac_ide_selectproc(drive
);
472 static void pmac_exec_command(ide_hwif_t
*hwif
, u8 cmd
)
474 writeb(cmd
, (void __iomem
*)hwif
->io_ports
.command_addr
);
475 (void)readl((void __iomem
*)(hwif
->io_ports
.data_addr
476 + IDE_TIMING_CONFIG
));
479 static void pmac_set_irq(ide_hwif_t
*hwif
, int on
)
481 u8 ctl
= ATA_DEVCTL_OBS
;
483 if (on
== 4) { /* hack for SRST */
490 writeb(ctl
, (void __iomem
*)hwif
->io_ports
.ctl_addr
);
491 (void)readl((void __iomem
*)(hwif
->io_ports
.data_addr
492 + IDE_TIMING_CONFIG
));
496 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
499 pmac_ide_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
501 ide_hwif_t
*hwif
= drive
->hwif
;
502 pmac_ide_hwif_t
*pmif
=
503 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
504 struct ide_timing
*tim
= ide_timing_find_mode(XFER_PIO_0
+ pio
);
506 unsigned accessTicks
, recTicks
;
507 unsigned accessTime
, recTime
;
508 unsigned int cycle_time
;
510 /* which drive is it ? */
511 timings
= &pmif
->timings
[drive
->dn
& 1];
514 cycle_time
= ide_pio_cycle_time(drive
, pio
);
516 switch (pmif
->kind
) {
517 case controller_sh_ata6
: {
519 u32 tr
= kauai_lookup_timing(shasta_pio_timings
, cycle_time
);
520 t
= (t
& ~TR_133_PIOREG_PIO_MASK
) | tr
;
523 case controller_un_ata6
:
524 case controller_k2_ata6
: {
526 u32 tr
= kauai_lookup_timing(kauai_pio_timings
, cycle_time
);
527 t
= (t
& ~TR_100_PIOREG_PIO_MASK
) | tr
;
530 case controller_kl_ata4
:
532 recTime
= cycle_time
- tim
->active
- tim
->setup
;
533 recTime
= max(recTime
, 150U);
534 accessTime
= tim
->active
;
535 accessTime
= max(accessTime
, 150U);
536 accessTicks
= SYSCLK_TICKS_66(accessTime
);
537 accessTicks
= min(accessTicks
, 0x1fU
);
538 recTicks
= SYSCLK_TICKS_66(recTime
);
539 recTicks
= min(recTicks
, 0x1fU
);
540 t
= (t
& ~TR_66_PIO_MASK
) |
541 (accessTicks
<< TR_66_PIO_ACCESS_SHIFT
) |
542 (recTicks
<< TR_66_PIO_RECOVERY_SHIFT
);
547 recTime
= cycle_time
- tim
->active
- tim
->setup
;
548 recTime
= max(recTime
, 150U);
549 accessTime
= tim
->active
;
550 accessTime
= max(accessTime
, 150U);
551 accessTicks
= SYSCLK_TICKS(accessTime
);
552 accessTicks
= min(accessTicks
, 0x1fU
);
553 accessTicks
= max(accessTicks
, 4U);
554 recTicks
= SYSCLK_TICKS(recTime
);
555 recTicks
= min(recTicks
, 0x1fU
);
556 recTicks
= max(recTicks
, 5U) - 4;
558 recTicks
--; /* guess, but it's only for PIO0, so... */
561 t
= (t
& ~TR_33_PIO_MASK
) |
562 (accessTicks
<< TR_33_PIO_ACCESS_SHIFT
) |
563 (recTicks
<< TR_33_PIO_RECOVERY_SHIFT
);
570 #ifdef IDE_PMAC_DEBUG
571 printk(KERN_ERR
"%s: Set PIO timing for mode %d, reg: 0x%08x\n",
572 drive
->name
, pio
, *timings
);
576 pmac_ide_do_update_timings(drive
);
580 * Calculate KeyLargo ATA/66 UDMA timings
583 set_timings_udma_ata4(u32
*timings
, u8 speed
)
585 unsigned rdyToPauseTicks
, wrDataSetupTicks
, addrTicks
;
587 if (speed
> XFER_UDMA_4
)
590 rdyToPauseTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].rdy2pause
);
591 wrDataSetupTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].wrDataSetup
);
592 addrTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].addrSetup
);
594 *timings
= ((*timings
) & ~(TR_66_UDMA_MASK
| TR_66_MDMA_MASK
)) |
595 (wrDataSetupTicks
<< TR_66_UDMA_WRDATASETUP_SHIFT
) |
596 (rdyToPauseTicks
<< TR_66_UDMA_RDY2PAUS_SHIFT
) |
597 (addrTicks
<<TR_66_UDMA_ADDRSETUP_SHIFT
) |
599 #ifdef IDE_PMAC_DEBUG
600 printk(KERN_ERR
"ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
601 speed
& 0xf, *timings
);
608 * Calculate Kauai ATA/100 UDMA timings
611 set_timings_udma_ata6(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
613 struct ide_timing
*t
= ide_timing_find_mode(speed
);
616 if (speed
> XFER_UDMA_5
|| t
== NULL
)
618 tr
= kauai_lookup_timing(kauai_udma_timings
, (int)t
->udma
);
619 *ultra_timings
= ((*ultra_timings
) & ~TR_100_UDMAREG_UDMA_MASK
) | tr
;
620 *ultra_timings
= (*ultra_timings
) | TR_100_UDMAREG_UDMA_EN
;
626 * Calculate Shasta ATA/133 UDMA timings
629 set_timings_udma_shasta(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
631 struct ide_timing
*t
= ide_timing_find_mode(speed
);
634 if (speed
> XFER_UDMA_6
|| t
== NULL
)
636 tr
= kauai_lookup_timing(shasta_udma133_timings
, (int)t
->udma
);
637 *ultra_timings
= ((*ultra_timings
) & ~TR_133_UDMAREG_UDMA_MASK
) | tr
;
638 *ultra_timings
= (*ultra_timings
) | TR_133_UDMAREG_UDMA_EN
;
644 * Calculate MDMA timings for all cells
647 set_timings_mdma(ide_drive_t
*drive
, int intf_type
, u32
*timings
, u32
*timings2
,
651 int cycleTime
, accessTime
= 0, recTime
= 0;
652 unsigned accessTicks
, recTicks
;
653 struct mdma_timings_t
* tm
= NULL
;
656 /* Get default cycle time for mode */
657 switch(speed
& 0xf) {
658 case 0: cycleTime
= 480; break;
659 case 1: cycleTime
= 150; break;
660 case 2: cycleTime
= 120; break;
666 /* Check if drive provides explicit DMA cycle time */
667 if ((id
[ATA_ID_FIELD_VALID
] & 2) && id
[ATA_ID_EIDE_DMA_TIME
])
668 cycleTime
= max_t(int, id
[ATA_ID_EIDE_DMA_TIME
], cycleTime
);
670 /* OHare limits according to some old Apple sources */
671 if ((intf_type
== controller_ohare
) && (cycleTime
< 150))
673 /* Get the proper timing array for this controller */
675 case controller_sh_ata6
:
676 case controller_un_ata6
:
677 case controller_k2_ata6
:
679 case controller_kl_ata4
:
680 tm
= mdma_timings_66
;
682 case controller_kl_ata3
:
683 tm
= mdma_timings_33k
;
686 tm
= mdma_timings_33
;
690 /* Lookup matching access & recovery times */
693 if (tm
[i
+1].cycleTime
< cycleTime
)
697 cycleTime
= tm
[i
].cycleTime
;
698 accessTime
= tm
[i
].accessTime
;
699 recTime
= tm
[i
].recoveryTime
;
701 #ifdef IDE_PMAC_DEBUG
702 printk(KERN_ERR
"%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
703 drive
->name
, cycleTime
, accessTime
, recTime
);
707 case controller_sh_ata6
: {
709 u32 tr
= kauai_lookup_timing(shasta_mdma_timings
, cycleTime
);
710 *timings
= ((*timings
) & ~TR_133_PIOREG_MDMA_MASK
) | tr
;
711 *timings2
= (*timings2
) & ~TR_133_UDMAREG_UDMA_EN
;
713 case controller_un_ata6
:
714 case controller_k2_ata6
: {
716 u32 tr
= kauai_lookup_timing(kauai_mdma_timings
, cycleTime
);
717 *timings
= ((*timings
) & ~TR_100_PIOREG_MDMA_MASK
) | tr
;
718 *timings2
= (*timings2
) & ~TR_100_UDMAREG_UDMA_EN
;
721 case controller_kl_ata4
:
723 accessTicks
= SYSCLK_TICKS_66(accessTime
);
724 accessTicks
= min(accessTicks
, 0x1fU
);
725 accessTicks
= max(accessTicks
, 0x1U
);
726 recTicks
= SYSCLK_TICKS_66(recTime
);
727 recTicks
= min(recTicks
, 0x1fU
);
728 recTicks
= max(recTicks
, 0x3U
);
729 /* Clear out mdma bits and disable udma */
730 *timings
= ((*timings
) & ~(TR_66_MDMA_MASK
| TR_66_UDMA_MASK
)) |
731 (accessTicks
<< TR_66_MDMA_ACCESS_SHIFT
) |
732 (recTicks
<< TR_66_MDMA_RECOVERY_SHIFT
);
734 case controller_kl_ata3
:
735 /* 33Mhz cell on KeyLargo */
736 accessTicks
= SYSCLK_TICKS(accessTime
);
737 accessTicks
= max(accessTicks
, 1U);
738 accessTicks
= min(accessTicks
, 0x1fU
);
739 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
740 recTicks
= SYSCLK_TICKS(recTime
);
741 recTicks
= max(recTicks
, 1U);
742 recTicks
= min(recTicks
, 0x1fU
);
743 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
744 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
745 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
748 /* 33Mhz cell on others */
750 int origAccessTime
= accessTime
;
751 int origRecTime
= recTime
;
753 accessTicks
= SYSCLK_TICKS(accessTime
);
754 accessTicks
= max(accessTicks
, 1U);
755 accessTicks
= min(accessTicks
, 0x1fU
);
756 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
757 recTicks
= SYSCLK_TICKS(recTime
);
758 recTicks
= max(recTicks
, 2U) - 1;
759 recTicks
= min(recTicks
, 0x1fU
);
760 recTime
= (recTicks
+ 1) * IDE_SYSCLK_NS
;
761 if ((accessTicks
> 1) &&
762 ((accessTime
- IDE_SYSCLK_NS
/2) >= origAccessTime
) &&
763 ((recTime
- IDE_SYSCLK_NS
/2) >= origRecTime
)) {
767 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
768 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
769 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
771 *timings
|= TR_33_MDMA_HALFTICK
;
774 #ifdef IDE_PMAC_DEBUG
775 printk(KERN_ERR
"%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
776 drive
->name
, speed
& 0xf, *timings
);
780 static void pmac_ide_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
782 ide_hwif_t
*hwif
= drive
->hwif
;
783 pmac_ide_hwif_t
*pmif
=
784 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
786 u32
*timings
, *timings2
, tl
[2];
787 u8 unit
= drive
->dn
& 1;
789 timings
= &pmif
->timings
[unit
];
790 timings2
= &pmif
->timings
[unit
+2];
792 /* Copy timings to local image */
796 if (speed
>= XFER_UDMA_0
) {
797 if (pmif
->kind
== controller_kl_ata4
)
798 ret
= set_timings_udma_ata4(&tl
[0], speed
);
799 else if (pmif
->kind
== controller_un_ata6
800 || pmif
->kind
== controller_k2_ata6
)
801 ret
= set_timings_udma_ata6(&tl
[0], &tl
[1], speed
);
802 else if (pmif
->kind
== controller_sh_ata6
)
803 ret
= set_timings_udma_shasta(&tl
[0], &tl
[1], speed
);
807 set_timings_mdma(drive
, pmif
->kind
, &tl
[0], &tl
[1], speed
);
812 /* Apply timings to controller */
816 pmac_ide_do_update_timings(drive
);
820 * Blast some well known "safe" values to the timing registers at init or
821 * wakeup from sleep time, before we do real calculation
824 sanitize_timings(pmac_ide_hwif_t
*pmif
)
826 unsigned int value
, value2
= 0;
829 case controller_sh_ata6
:
833 case controller_un_ata6
:
834 case controller_k2_ata6
:
838 case controller_kl_ata4
:
841 case controller_kl_ata3
:
844 case controller_heathrow
:
845 case controller_ohare
:
850 pmif
->timings
[0] = pmif
->timings
[1] = value
;
851 pmif
->timings
[2] = pmif
->timings
[3] = value2
;
854 /* Suspend call back, should be called after the child devices
855 * have actually been suspended
857 static int pmac_ide_do_suspend(pmac_ide_hwif_t
*pmif
)
859 /* We clear the timings */
860 pmif
->timings
[0] = 0;
861 pmif
->timings
[1] = 0;
863 disable_irq(pmif
->irq
);
865 /* The media bay will handle itself just fine */
869 /* Kauai has bus control FCRs directly here */
870 if (pmif
->kauai_fcr
) {
871 u32 fcr
= readl(pmif
->kauai_fcr
);
872 fcr
&= ~(KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
);
873 writel(fcr
, pmif
->kauai_fcr
);
876 /* Disable the bus on older machines and the cell on kauai */
877 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
,
883 /* Resume call back, should be called before the child devices
886 static int pmac_ide_do_resume(pmac_ide_hwif_t
*pmif
)
888 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
889 if (!pmif
->mediabay
) {
890 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 1);
891 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
, 1);
893 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 0);
895 /* Kauai has it different */
896 if (pmif
->kauai_fcr
) {
897 u32 fcr
= readl(pmif
->kauai_fcr
);
898 fcr
|= KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
;
899 writel(fcr
, pmif
->kauai_fcr
);
902 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
905 /* Sanitize drive timings */
906 sanitize_timings(pmif
);
908 enable_irq(pmif
->irq
);
913 static u8
pmac_ide_cable_detect(ide_hwif_t
*hwif
)
915 pmac_ide_hwif_t
*pmif
=
916 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
917 struct device_node
*np
= pmif
->node
;
918 const char *cable
= of_get_property(np
, "cable-type", NULL
);
920 /* Get cable type from device-tree. */
921 if (cable
&& !strncmp(cable
, "80-", 3))
922 return ATA_CBL_PATA80
;
925 * G5's seem to have incorrect cable type in device-tree.
926 * Let's assume they have a 80 conductor cable, this seem
927 * to be always the case unless the user mucked around.
929 if (of_device_is_compatible(np
, "K2-UATA") ||
930 of_device_is_compatible(np
, "shasta-ata"))
931 return ATA_CBL_PATA80
;
933 return ATA_CBL_PATA40
;
936 static void pmac_ide_init_dev(ide_drive_t
*drive
)
938 ide_hwif_t
*hwif
= drive
->hwif
;
939 pmac_ide_hwif_t
*pmif
=
940 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
942 if (pmif
->mediabay
) {
943 #ifdef CONFIG_PMAC_MEDIABAY
944 if (check_media_bay_by_base(pmif
->regbase
, MB_CD
) == 0) {
945 drive
->dev_flags
&= ~IDE_DFLAG_NOPROBE
;
949 drive
->dev_flags
|= IDE_DFLAG_NOPROBE
;
953 static const struct ide_tp_ops pmac_tp_ops
= {
954 .exec_command
= pmac_exec_command
,
955 .read_status
= ide_read_status
,
956 .read_altstatus
= ide_read_altstatus
,
958 .set_irq
= pmac_set_irq
,
960 .tf_load
= ide_tf_load
,
961 .tf_read
= ide_tf_read
,
963 .input_data
= ide_input_data
,
964 .output_data
= ide_output_data
,
967 static const struct ide_port_ops pmac_ide_ata6_port_ops
= {
968 .init_dev
= pmac_ide_init_dev
,
969 .set_pio_mode
= pmac_ide_set_pio_mode
,
970 .set_dma_mode
= pmac_ide_set_dma_mode
,
971 .selectproc
= pmac_ide_kauai_selectproc
,
972 .cable_detect
= pmac_ide_cable_detect
,
975 static const struct ide_port_ops pmac_ide_ata4_port_ops
= {
976 .init_dev
= pmac_ide_init_dev
,
977 .set_pio_mode
= pmac_ide_set_pio_mode
,
978 .set_dma_mode
= pmac_ide_set_dma_mode
,
979 .selectproc
= pmac_ide_selectproc
,
980 .cable_detect
= pmac_ide_cable_detect
,
983 static const struct ide_port_ops pmac_ide_port_ops
= {
984 .init_dev
= pmac_ide_init_dev
,
985 .set_pio_mode
= pmac_ide_set_pio_mode
,
986 .set_dma_mode
= pmac_ide_set_dma_mode
,
987 .selectproc
= pmac_ide_selectproc
,
990 static const struct ide_dma_ops pmac_dma_ops
;
992 static const struct ide_port_info pmac_port_info
= {
994 .init_dma
= pmac_ide_init_dma
,
996 .tp_ops
= &pmac_tp_ops
,
997 .port_ops
= &pmac_ide_port_ops
,
998 .dma_ops
= &pmac_dma_ops
,
999 .host_flags
= IDE_HFLAG_SET_PIO_MODE_KEEP_DMA
|
1000 IDE_HFLAG_POST_SET_MODE
|
1002 IDE_HFLAG_UNMASK_IRQS
,
1003 .pio_mask
= ATA_PIO4
,
1004 .mwdma_mask
= ATA_MWDMA2
,
1008 * Setup, register & probe an IDE channel driven by this driver, this is
1009 * called by one of the 2 probe functions (macio or PCI).
1011 static int __devinit
pmac_ide_setup_device(pmac_ide_hwif_t
*pmif
, hw_regs_t
*hw
)
1013 struct device_node
*np
= pmif
->node
;
1015 struct ide_host
*host
;
1017 hw_regs_t
*hws
[] = { hw
, NULL
, NULL
, NULL
};
1018 struct ide_port_info d
= pmac_port_info
;
1021 pmif
->broken_dma
= pmif
->broken_dma_warn
= 0;
1022 if (of_device_is_compatible(np
, "shasta-ata")) {
1023 pmif
->kind
= controller_sh_ata6
;
1024 d
.port_ops
= &pmac_ide_ata6_port_ops
;
1025 d
.udma_mask
= ATA_UDMA6
;
1026 } else if (of_device_is_compatible(np
, "kauai-ata")) {
1027 pmif
->kind
= controller_un_ata6
;
1028 d
.port_ops
= &pmac_ide_ata6_port_ops
;
1029 d
.udma_mask
= ATA_UDMA5
;
1030 } else if (of_device_is_compatible(np
, "K2-UATA")) {
1031 pmif
->kind
= controller_k2_ata6
;
1032 d
.port_ops
= &pmac_ide_ata6_port_ops
;
1033 d
.udma_mask
= ATA_UDMA5
;
1034 } else if (of_device_is_compatible(np
, "keylargo-ata")) {
1035 if (strcmp(np
->name
, "ata-4") == 0) {
1036 pmif
->kind
= controller_kl_ata4
;
1037 d
.port_ops
= &pmac_ide_ata4_port_ops
;
1038 d
.udma_mask
= ATA_UDMA4
;
1040 pmif
->kind
= controller_kl_ata3
;
1041 } else if (of_device_is_compatible(np
, "heathrow-ata")) {
1042 pmif
->kind
= controller_heathrow
;
1044 pmif
->kind
= controller_ohare
;
1045 pmif
->broken_dma
= 1;
1048 bidp
= of_get_property(np
, "AAPL,bus-id", NULL
);
1049 pmif
->aapl_bus_id
= bidp
? *bidp
: 0;
1051 /* On Kauai-type controllers, we make sure the FCR is correct */
1052 if (pmif
->kauai_fcr
)
1053 writel(KAUAI_FCR_UATA_MAGIC
|
1054 KAUAI_FCR_UATA_RESET_N
|
1055 KAUAI_FCR_UATA_ENABLE
, pmif
->kauai_fcr
);
1059 /* Make sure we have sane timings */
1060 sanitize_timings(pmif
);
1062 host
= ide_host_alloc(&d
, hws
);
1065 hwif
= host
->ports
[0];
1067 #ifndef CONFIG_PPC64
1068 /* XXX FIXME: Media bay stuff need re-organizing */
1069 if (np
->parent
&& np
->parent
->name
1070 && strcasecmp(np
->parent
->name
, "media-bay") == 0) {
1071 #ifdef CONFIG_PMAC_MEDIABAY
1072 media_bay_set_ide_infos(np
->parent
, pmif
->regbase
, pmif
->irq
,
1074 #endif /* CONFIG_PMAC_MEDIABAY */
1077 pmif
->aapl_bus_id
= 1;
1078 } else if (pmif
->kind
== controller_ohare
) {
1079 /* The code below is having trouble on some ohare machines
1080 * (timing related ?). Until I can put my hand on one of these
1081 * units, I keep the old way
1083 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, 0, 1);
1087 /* This is necessary to enable IDE when net-booting */
1088 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 1);
1089 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, pmif
->aapl_bus_id
, 1);
1091 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 0);
1092 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1095 printk(KERN_INFO DRV_NAME
": Found Apple %s controller (%s), "
1096 "bus ID %d%s, irq %d\n", model_name
[pmif
->kind
],
1097 pmif
->mdev
? "macio" : "PCI", pmif
->aapl_bus_id
,
1098 pmif
->mediabay
? " (mediabay)" : "", hw
->irq
);
1100 rc
= ide_host_register(host
, &d
, hws
);
1102 ide_host_free(host
);
1109 static void __devinit
pmac_ide_init_ports(hw_regs_t
*hw
, unsigned long base
)
1113 for (i
= 0; i
< 8; ++i
)
1114 hw
->io_ports_array
[i
] = base
+ i
* 0x10;
1116 hw
->io_ports
.ctl_addr
= base
+ 0x160;
1120 * Attach to a macio probed interface
1122 static int __devinit
1123 pmac_ide_macio_attach(struct macio_dev
*mdev
, const struct of_device_id
*match
)
1126 unsigned long regbase
;
1127 pmac_ide_hwif_t
*pmif
;
1131 pmif
= kzalloc(sizeof(*pmif
), GFP_KERNEL
);
1135 if (macio_resource_count(mdev
) == 0) {
1136 printk(KERN_WARNING
"ide-pmac: no address for %s\n",
1137 mdev
->ofdev
.node
->full_name
);
1142 /* Request memory resource for IO ports */
1143 if (macio_request_resource(mdev
, 0, "ide-pmac (ports)")) {
1144 printk(KERN_ERR
"ide-pmac: can't request MMIO resource for "
1145 "%s!\n", mdev
->ofdev
.node
->full_name
);
1150 /* XXX This is bogus. Should be fixed in the registry by checking
1151 * the kind of host interrupt controller, a bit like gatwick
1152 * fixes in irq.c. That works well enough for the single case
1153 * where that happens though...
1155 if (macio_irq_count(mdev
) == 0) {
1156 printk(KERN_WARNING
"ide-pmac: no intrs for device %s, using "
1157 "13\n", mdev
->ofdev
.node
->full_name
);
1158 irq
= irq_create_mapping(NULL
, 13);
1160 irq
= macio_irq(mdev
, 0);
1162 base
= ioremap(macio_resource_start(mdev
, 0), 0x400);
1163 regbase
= (unsigned long) base
;
1166 pmif
->node
= mdev
->ofdev
.node
;
1167 pmif
->regbase
= regbase
;
1169 pmif
->kauai_fcr
= NULL
;
1171 if (macio_resource_count(mdev
) >= 2) {
1172 if (macio_request_resource(mdev
, 1, "ide-pmac (dma)"))
1173 printk(KERN_WARNING
"ide-pmac: can't request DMA "
1174 "resource for %s!\n",
1175 mdev
->ofdev
.node
->full_name
);
1177 pmif
->dma_regs
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
1179 pmif
->dma_regs
= NULL
;
1181 dev_set_drvdata(&mdev
->ofdev
.dev
, pmif
);
1183 memset(&hw
, 0, sizeof(hw
));
1184 pmac_ide_init_ports(&hw
, pmif
->regbase
);
1186 hw
.dev
= &mdev
->bus
->pdev
->dev
;
1187 hw
.parent
= &mdev
->ofdev
.dev
;
1189 rc
= pmac_ide_setup_device(pmif
, &hw
);
1191 /* The inteface is released to the common IDE layer */
1192 dev_set_drvdata(&mdev
->ofdev
.dev
, NULL
);
1194 if (pmif
->dma_regs
) {
1195 iounmap(pmif
->dma_regs
);
1196 macio_release_resource(mdev
, 1);
1198 macio_release_resource(mdev
, 0);
1210 pmac_ide_macio_suspend(struct macio_dev
*mdev
, pm_message_t mesg
)
1212 pmac_ide_hwif_t
*pmif
=
1213 (pmac_ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1216 if (mesg
.event
!= mdev
->ofdev
.dev
.power
.power_state
.event
1217 && (mesg
.event
& PM_EVENT_SLEEP
)) {
1218 rc
= pmac_ide_do_suspend(pmif
);
1220 mdev
->ofdev
.dev
.power
.power_state
= mesg
;
1227 pmac_ide_macio_resume(struct macio_dev
*mdev
)
1229 pmac_ide_hwif_t
*pmif
=
1230 (pmac_ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1233 if (mdev
->ofdev
.dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1234 rc
= pmac_ide_do_resume(pmif
);
1236 mdev
->ofdev
.dev
.power
.power_state
= PMSG_ON
;
1243 * Attach to a PCI probed interface
1245 static int __devinit
1246 pmac_ide_pci_attach(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1248 struct device_node
*np
;
1249 pmac_ide_hwif_t
*pmif
;
1251 unsigned long rbase
, rlen
;
1255 np
= pci_device_to_OF_node(pdev
);
1257 printk(KERN_ERR
"ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1261 pmif
= kzalloc(sizeof(*pmif
), GFP_KERNEL
);
1265 if (pci_enable_device(pdev
)) {
1266 printk(KERN_WARNING
"ide-pmac: Can't enable PCI device for "
1267 "%s\n", np
->full_name
);
1271 pci_set_master(pdev
);
1273 if (pci_request_regions(pdev
, "Kauai ATA")) {
1274 printk(KERN_ERR
"ide-pmac: Cannot obtain PCI resources for "
1275 "%s\n", np
->full_name
);
1283 rbase
= pci_resource_start(pdev
, 0);
1284 rlen
= pci_resource_len(pdev
, 0);
1286 base
= ioremap(rbase
, rlen
);
1287 pmif
->regbase
= (unsigned long) base
+ 0x2000;
1288 pmif
->dma_regs
= base
+ 0x1000;
1289 pmif
->kauai_fcr
= base
;
1290 pmif
->irq
= pdev
->irq
;
1292 pci_set_drvdata(pdev
, pmif
);
1294 memset(&hw
, 0, sizeof(hw
));
1295 pmac_ide_init_ports(&hw
, pmif
->regbase
);
1297 hw
.dev
= &pdev
->dev
;
1299 rc
= pmac_ide_setup_device(pmif
, &hw
);
1301 /* The inteface is released to the common IDE layer */
1302 pci_set_drvdata(pdev
, NULL
);
1304 pci_release_regions(pdev
);
1316 pmac_ide_pci_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1318 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)pci_get_drvdata(pdev
);
1321 if (mesg
.event
!= pdev
->dev
.power
.power_state
.event
1322 && (mesg
.event
& PM_EVENT_SLEEP
)) {
1323 rc
= pmac_ide_do_suspend(pmif
);
1325 pdev
->dev
.power
.power_state
= mesg
;
1332 pmac_ide_pci_resume(struct pci_dev
*pdev
)
1334 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)pci_get_drvdata(pdev
);
1337 if (pdev
->dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1338 rc
= pmac_ide_do_resume(pmif
);
1340 pdev
->dev
.power
.power_state
= PMSG_ON
;
1346 static struct of_device_id pmac_ide_macio_match
[] =
1363 static struct macio_driver pmac_ide_macio_driver
=
1366 .match_table
= pmac_ide_macio_match
,
1367 .probe
= pmac_ide_macio_attach
,
1368 .suspend
= pmac_ide_macio_suspend
,
1369 .resume
= pmac_ide_macio_resume
,
1372 static const struct pci_device_id pmac_ide_pci_match
[] = {
1373 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_ATA
), 0 },
1374 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID_ATA100
), 0 },
1375 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_K2_ATA100
), 0 },
1376 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_SH_ATA
), 0 },
1377 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID2_ATA
), 0 },
1381 static struct pci_driver pmac_ide_pci_driver
= {
1383 .id_table
= pmac_ide_pci_match
,
1384 .probe
= pmac_ide_pci_attach
,
1385 .suspend
= pmac_ide_pci_suspend
,
1386 .resume
= pmac_ide_pci_resume
,
1388 MODULE_DEVICE_TABLE(pci
, pmac_ide_pci_match
);
1390 int __init
pmac_ide_probe(void)
1394 if (!machine_is(powermac
))
1397 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1398 error
= pci_register_driver(&pmac_ide_pci_driver
);
1401 error
= macio_register_driver(&pmac_ide_macio_driver
);
1403 pci_unregister_driver(&pmac_ide_pci_driver
);
1407 error
= macio_register_driver(&pmac_ide_macio_driver
);
1410 error
= pci_register_driver(&pmac_ide_pci_driver
);
1412 macio_unregister_driver(&pmac_ide_macio_driver
);
1421 * pmac_ide_build_dmatable builds the DBDMA command list
1422 * for a transfer and sets the DBDMA channel to point to it.
1424 static int pmac_ide_build_dmatable(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
1426 ide_hwif_t
*hwif
= drive
->hwif
;
1427 pmac_ide_hwif_t
*pmif
=
1428 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
1429 struct dbdma_cmd
*table
;
1430 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1431 struct scatterlist
*sg
;
1432 int wr
= !!(cmd
->tf_flags
& IDE_TFLAG_WRITE
);
1433 int i
= cmd
->sg_nents
, count
= 0;
1435 /* DMA table is already aligned */
1436 table
= (struct dbdma_cmd
*) pmif
->dma_table_cpu
;
1438 /* Make sure DMA controller is stopped (necessary ?) */
1439 writel((RUN
|PAUSE
|FLUSH
|WAKE
|DEAD
) << 16, &dma
->control
);
1440 while (readl(&dma
->status
) & RUN
)
1443 /* Build DBDMA commands list */
1444 sg
= hwif
->sg_table
;
1445 while (i
&& sg_dma_len(sg
)) {
1449 cur_addr
= sg_dma_address(sg
);
1450 cur_len
= sg_dma_len(sg
);
1452 if (pmif
->broken_dma
&& cur_addr
& (L1_CACHE_BYTES
- 1)) {
1453 if (pmif
->broken_dma_warn
== 0) {
1454 printk(KERN_WARNING
"%s: DMA on non aligned address, "
1455 "switching to PIO on Ohare chipset\n", drive
->name
);
1456 pmif
->broken_dma_warn
= 1;
1461 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
1463 if (count
++ >= MAX_DCMDS
) {
1464 printk(KERN_WARNING
"%s: DMA table too small\n",
1468 st_le16(&table
->command
, wr
? OUTPUT_MORE
: INPUT_MORE
);
1469 st_le16(&table
->req_count
, tc
);
1470 st_le32(&table
->phy_addr
, cur_addr
);
1472 table
->xfer_status
= 0;
1473 table
->res_count
= 0;
1482 /* convert the last command to an input/output last command */
1484 st_le16(&table
[-1].command
, wr
? OUTPUT_LAST
: INPUT_LAST
);
1485 /* add the stop command to the end of the list */
1486 memset(table
, 0, sizeof(struct dbdma_cmd
));
1487 st_le16(&table
->command
, DBDMA_STOP
);
1489 writel(hwif
->dmatable_dma
, &dma
->cmdptr
);
1493 printk(KERN_DEBUG
"%s: empty DMA table?\n", drive
->name
);
1495 return 0; /* revert to PIO for this request */
1499 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1500 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1502 static int pmac_ide_dma_setup(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
1504 ide_hwif_t
*hwif
= drive
->hwif
;
1505 pmac_ide_hwif_t
*pmif
=
1506 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
1507 u8 unit
= drive
->dn
& 1, ata4
= (pmif
->kind
== controller_kl_ata4
);
1508 u8 write
= !!(cmd
->tf_flags
& IDE_TFLAG_WRITE
);
1510 if (pmac_ide_build_dmatable(drive
, cmd
) == 0)
1513 /* Apple adds 60ns to wrDataSetup on reads */
1514 if (ata4
&& (pmif
->timings
[unit
] & TR_66_UDMA_EN
)) {
1515 writel(pmif
->timings
[unit
] + (write
? 0 : 0x00800000UL
),
1516 PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1517 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1520 drive
->waiting_for_dma
= 1;
1526 * Kick the DMA controller into life after the DMA command has been issued
1530 pmac_ide_dma_start(ide_drive_t
*drive
)
1532 ide_hwif_t
*hwif
= drive
->hwif
;
1533 pmac_ide_hwif_t
*pmif
=
1534 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
1535 volatile struct dbdma_regs __iomem
*dma
;
1537 dma
= pmif
->dma_regs
;
1539 writel((RUN
<< 16) | RUN
, &dma
->control
);
1540 /* Make sure it gets to the controller right now */
1541 (void)readl(&dma
->control
);
1545 * After a DMA transfer, make sure the controller is stopped
1548 pmac_ide_dma_end (ide_drive_t
*drive
)
1550 ide_hwif_t
*hwif
= drive
->hwif
;
1551 pmac_ide_hwif_t
*pmif
=
1552 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
1553 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1556 drive
->waiting_for_dma
= 0;
1557 dstat
= readl(&dma
->status
);
1558 writel(((RUN
|WAKE
|DEAD
) << 16), &dma
->control
);
1560 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1561 * in theory, but with ATAPI decices doing buffer underruns, that would
1562 * cause us to disable DMA, which isn't what we want
1564 return (dstat
& (RUN
|DEAD
)) != RUN
;
1568 * Check out that the interrupt we got was for us. We can't always know this
1569 * for sure with those Apple interfaces (well, we could on the recent ones but
1570 * that's not implemented yet), on the other hand, we don't have shared interrupts
1571 * so it's not really a problem
1574 pmac_ide_dma_test_irq (ide_drive_t
*drive
)
1576 ide_hwif_t
*hwif
= drive
->hwif
;
1577 pmac_ide_hwif_t
*pmif
=
1578 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
1579 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1580 unsigned long status
, timeout
;
1582 /* We have to things to deal with here:
1584 * - The dbdma won't stop if the command was started
1585 * but completed with an error without transferring all
1586 * datas. This happens when bad blocks are met during
1587 * a multi-block transfer.
1589 * - The dbdma fifo hasn't yet finished flushing to
1590 * to system memory when the disk interrupt occurs.
1594 /* If ACTIVE is cleared, the STOP command have passed and
1595 * transfer is complete.
1597 status
= readl(&dma
->status
);
1598 if (!(status
& ACTIVE
))
1601 /* If dbdma didn't execute the STOP command yet, the
1602 * active bit is still set. We consider that we aren't
1603 * sharing interrupts (which is hopefully the case with
1604 * those controllers) and so we just try to flush the
1605 * channel for pending data in the fifo
1608 writel((FLUSH
<< 16) | FLUSH
, &dma
->control
);
1612 status
= readl(&dma
->status
);
1613 if ((status
& FLUSH
) == 0)
1615 if (++timeout
> 100) {
1616 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1617 timeout flushing channel\n", hwif
->index
);
1624 static void pmac_ide_dma_host_set(ide_drive_t
*drive
, int on
)
1629 pmac_ide_dma_lost_irq (ide_drive_t
*drive
)
1631 ide_hwif_t
*hwif
= drive
->hwif
;
1632 pmac_ide_hwif_t
*pmif
=
1633 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
1634 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1635 unsigned long status
= readl(&dma
->status
);
1637 printk(KERN_ERR
"ide-pmac lost interrupt, dma status: %lx\n", status
);
1640 static const struct ide_dma_ops pmac_dma_ops
= {
1641 .dma_host_set
= pmac_ide_dma_host_set
,
1642 .dma_setup
= pmac_ide_dma_setup
,
1643 .dma_start
= pmac_ide_dma_start
,
1644 .dma_end
= pmac_ide_dma_end
,
1645 .dma_test_irq
= pmac_ide_dma_test_irq
,
1646 .dma_lost_irq
= pmac_ide_dma_lost_irq
,
1650 * Allocate the data structures needed for using DMA with an interface
1651 * and fill the proper list of functions pointers
1653 static int __devinit
pmac_ide_init_dma(ide_hwif_t
*hwif
,
1654 const struct ide_port_info
*d
)
1656 pmac_ide_hwif_t
*pmif
=
1657 (pmac_ide_hwif_t
*)dev_get_drvdata(hwif
->gendev
.parent
);
1658 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1660 /* We won't need pci_dev if we switch to generic consistent
1663 if (dev
== NULL
|| pmif
->dma_regs
== 0)
1666 * Allocate space for the DBDMA commands.
1667 * The +2 is +1 for the stop command and +1 to allow for
1668 * aligning the start address to a multiple of 16 bytes.
1670 pmif
->dma_table_cpu
= (struct dbdma_cmd
*)pci_alloc_consistent(
1672 (MAX_DCMDS
+ 2) * sizeof(struct dbdma_cmd
),
1673 &hwif
->dmatable_dma
);
1674 if (pmif
->dma_table_cpu
== NULL
) {
1675 printk(KERN_ERR
"%s: unable to allocate DMA command list\n",
1680 hwif
->sg_max_nents
= MAX_DCMDS
;
1685 module_init(pmac_ide_probe
);
1687 MODULE_LICENSE("GPL");