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ide: add struct ide_port_ops (take 2)
[deliverable/linux.git] / drivers / ide / ppc / mpc8xx.c
1 /*
2 * Copyright (C) 2000, 2001 Wolfgang Denk, wd@denx.de
3 * Modified for direct IDE interface
4 * by Thomas Lange, thomas@corelatus.com
5 * Modified for direct IDE interface on 8xx without using the PCMCIA
6 * controller
7 * by Steven.Scholz@imc-berlin.de
8 * Moved out of arch/ppc/kernel/m8xx_setup.c, other minor cleanups
9 * by Mathew Locke <mattl@mvista.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/mm.h>
15 #include <linux/stddef.h>
16 #include <linux/unistd.h>
17 #include <linux/ptrace.h>
18 #include <linux/slab.h>
19 #include <linux/user.h>
20 #include <linux/tty.h>
21 #include <linux/major.h>
22 #include <linux/interrupt.h>
23 #include <linux/reboot.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/ide.h>
27 #include <linux/bootmem.h>
28
29 #include <asm/mpc8xx.h>
30 #include <asm/mmu.h>
31 #include <asm/processor.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/ide.h>
35 #include <asm/8xx_immap.h>
36 #include <asm/machdep.h>
37 #include <asm/irq.h>
38
39 #define DRV_NAME "ide-mpc8xx"
40
41 static int identify (volatile u8 *p);
42 static void print_fixed (volatile u8 *p);
43 static void print_funcid (int func);
44 static int check_ide_device (unsigned long base);
45
46 static void ide_interrupt_ack (void *dev);
47 static void m8xx_ide_set_pio_mode(ide_drive_t *drive, const u8 pio);
48
49 typedef struct ide_ioport_desc {
50 unsigned long base_off; /* Offset to PCMCIA memory */
51 unsigned long reg_off[IDE_NR_PORTS]; /* controller register offsets */
52 int irq; /* IRQ */
53 } ide_ioport_desc_t;
54
55 ide_ioport_desc_t ioport_dsc[MAX_HWIFS] = {
56 #ifdef IDE0_BASE_OFFSET
57 { IDE0_BASE_OFFSET,
58 {
59 IDE0_DATA_REG_OFFSET,
60 IDE0_ERROR_REG_OFFSET,
61 IDE0_NSECTOR_REG_OFFSET,
62 IDE0_SECTOR_REG_OFFSET,
63 IDE0_LCYL_REG_OFFSET,
64 IDE0_HCYL_REG_OFFSET,
65 IDE0_SELECT_REG_OFFSET,
66 IDE0_STATUS_REG_OFFSET,
67 IDE0_CONTROL_REG_OFFSET,
68 IDE0_IRQ_REG_OFFSET,
69 },
70 IDE0_INTERRUPT,
71 },
72 #ifdef IDE1_BASE_OFFSET
73 { IDE1_BASE_OFFSET,
74 {
75 IDE1_DATA_REG_OFFSET,
76 IDE1_ERROR_REG_OFFSET,
77 IDE1_NSECTOR_REG_OFFSET,
78 IDE1_SECTOR_REG_OFFSET,
79 IDE1_LCYL_REG_OFFSET,
80 IDE1_HCYL_REG_OFFSET,
81 IDE1_SELECT_REG_OFFSET,
82 IDE1_STATUS_REG_OFFSET,
83 IDE1_CONTROL_REG_OFFSET,
84 IDE1_IRQ_REG_OFFSET,
85 },
86 IDE1_INTERRUPT,
87 },
88 #endif /* IDE1_BASE_OFFSET */
89 #endif /* IDE0_BASE_OFFSET */
90 };
91
92 ide_pio_timings_t ide_pio_clocks[6];
93 int hold_time[6] = {30, 20, 15, 10, 10, 10 }; /* PIO Mode 5 with IORDY (nonstandard) */
94
95 /*
96 * Warning: only 1 (ONE) PCMCIA slot supported here,
97 * which must be correctly initialized by the firmware (PPCBoot).
98 */
99 static int _slot_ = -1; /* will be read from PCMCIA registers */
100
101 /* Make clock cycles and always round up */
102 #define PCMCIA_MK_CLKS( t, T ) (( (t) * ((T)/1000000) + 999U ) / 1000U )
103
104 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
105 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
106
107 /*
108 * The TQM850L hardware has two pins swapped! Grrrrgh!
109 */
110 #ifdef CONFIG_TQM850L
111 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
112 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
113 #else
114 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
115 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
116 #endif
117
118 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
119 #define PCMCIA_SCHLVL IDE0_INTERRUPT /* Status Change Interrupt Level */
120 static int pcmcia_schlvl = PCMCIA_SCHLVL;
121 #endif
122
123 /*
124 * See include/linux/ide.h for definition of hw_regs_t (p, base)
125 */
126
127 /*
128 * m8xx_ide_init_ports() for a direct IDE interface _using_
129 * MPC8xx's internal PCMCIA interface
130 */
131 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
132 static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
133 {
134 unsigned long *p = hw->io_ports;
135 int i;
136
137 typedef struct {
138 ulong br;
139 ulong or;
140 } pcmcia_win_t;
141 volatile pcmcia_win_t *win;
142 volatile pcmconf8xx_t *pcmp;
143
144 uint *pgcrx;
145 u32 pcmcia_phy_base;
146 u32 pcmcia_phy_end;
147 static unsigned long pcmcia_base = 0;
148 unsigned long base;
149
150 *p = 0;
151
152 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
153
154 if (!pcmcia_base) {
155 /*
156 * Read out PCMCIA registers. Since the reset values
157 * are undefined, we sure hope that they have been
158 * set up by firmware
159 */
160
161 /* Scan all registers for valid settings */
162 pcmcia_phy_base = 0xFFFFFFFF;
163 pcmcia_phy_end = 0;
164 /* br0 is start of brX and orX regs */
165 win = (pcmcia_win_t *) \
166 (&(((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0));
167 for (i = 0; i < 8; i++) {
168 if (win->or & 1) { /* This bank is marked as valid */
169 if (win->br < pcmcia_phy_base) {
170 pcmcia_phy_base = win->br;
171 }
172 if ((win->br + PCMCIA_MEM_SIZE) > pcmcia_phy_end) {
173 pcmcia_phy_end = win->br + PCMCIA_MEM_SIZE;
174 }
175 /* Check which slot that has been defined */
176 _slot_ = (win->or >> 2) & 1;
177
178 } /* Valid bank */
179 win++;
180 } /* for */
181
182 printk ("PCMCIA slot %c: phys mem %08x...%08x (size %08x)\n",
183 'A' + _slot_,
184 pcmcia_phy_base, pcmcia_phy_end,
185 pcmcia_phy_end - pcmcia_phy_base);
186
187 if (!request_mem_region(pcmcia_phy_base,
188 pcmcia_phy_end - pcmcia_phy_base,
189 DRV_NAME)) {
190 printk(KERN_ERR "%s: resources busy\n", DRV_NAME);
191 return -EBUSY;
192 }
193
194 pcmcia_base=(unsigned long)ioremap(pcmcia_phy_base,
195 pcmcia_phy_end-pcmcia_phy_base);
196
197 #ifdef DEBUG
198 printk ("PCMCIA virt base: %08lx\n", pcmcia_base);
199 #endif
200 /* Compute clock cycles for PIO timings */
201 for (i=0; i<6; ++i) {
202 bd_t *binfo = (bd_t *)__res;
203
204 hold_time[i] =
205 PCMCIA_MK_CLKS (hold_time[i],
206 binfo->bi_busfreq);
207 ide_pio_clocks[i].setup_time =
208 PCMCIA_MK_CLKS (ide_pio_timings[i].setup_time,
209 binfo->bi_busfreq);
210 ide_pio_clocks[i].active_time =
211 PCMCIA_MK_CLKS (ide_pio_timings[i].active_time,
212 binfo->bi_busfreq);
213 ide_pio_clocks[i].cycle_time =
214 PCMCIA_MK_CLKS (ide_pio_timings[i].cycle_time,
215 binfo->bi_busfreq);
216 #if 0
217 printk ("PIO mode %d timings: %d/%d/%d => %d/%d/%d\n",
218 i,
219 ide_pio_clocks[i].setup_time,
220 ide_pio_clocks[i].active_time,
221 ide_pio_clocks[i].hold_time,
222 ide_pio_clocks[i].cycle_time,
223 ide_pio_timings[i].setup_time,
224 ide_pio_timings[i].active_time,
225 ide_pio_timings[i].hold_time,
226 ide_pio_timings[i].cycle_time);
227 #endif
228 }
229 }
230
231 if (_slot_ == -1) {
232 printk ("PCMCIA slot has not been defined! Using A as default\n");
233 _slot_ = 0;
234 }
235
236 #ifdef CONFIG_IDE_8xx_PCCARD
237
238 #ifdef DEBUG
239 printk ("PIPR = 0x%08X slot %c ==> mask = 0x%X\n",
240 pcmp->pcmc_pipr,
241 'A' + _slot_,
242 M8XX_PCMCIA_CD1(_slot_) | M8XX_PCMCIA_CD2(_slot_) );
243 #endif /* DEBUG */
244
245 if (pcmp->pcmc_pipr & (M8XX_PCMCIA_CD1(_slot_)|M8XX_PCMCIA_CD2(_slot_))) {
246 printk ("No card in slot %c: PIPR=%08x\n",
247 'A' + _slot_, (u32) pcmp->pcmc_pipr);
248 return -ENODEV; /* No card in slot */
249 }
250
251 check_ide_device (pcmcia_base);
252
253 #endif /* CONFIG_IDE_8xx_PCCARD */
254
255 base = pcmcia_base + ioport_dsc[data_port].base_off;
256 #ifdef DEBUG
257 printk ("base: %08x + %08x = %08x\n",
258 pcmcia_base, ioport_dsc[data_port].base_off, base);
259 #endif
260
261 for (i = 0; i < IDE_NR_PORTS; ++i) {
262 #ifdef DEBUG
263 printk ("port[%d]: %08x + %08x = %08x\n",
264 i,
265 base,
266 ioport_dsc[data_port].reg_off[i],
267 i, base + ioport_dsc[data_port].reg_off[i]);
268 #endif
269 *p++ = base + ioport_dsc[data_port].reg_off[i];
270 }
271
272 hw->irq = ioport_dsc[data_port].irq;
273 hw->ack_intr = (ide_ack_intr_t *)ide_interrupt_ack;
274
275 #ifdef CONFIG_IDE_8xx_PCCARD
276 {
277 unsigned int reg;
278
279 if (_slot_)
280 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcrb;
281 else
282 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcra;
283
284 reg = *pgcrx;
285 reg |= mk_int_int_mask (pcmcia_schlvl) << 24;
286 reg |= mk_int_int_mask (pcmcia_schlvl) << 16;
287 *pgcrx = reg;
288 }
289 #endif /* CONFIG_IDE_8xx_PCCARD */
290
291 /* Enable Harddisk Interrupt,
292 * and make it edge sensitive
293 */
294 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
295 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
296 (0x80000000 >> ioport_dsc[data_port].irq);
297
298 #ifdef CONFIG_IDE_8xx_PCCARD
299 /* Make sure we don't get garbage irq */
300 ((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pscr = 0xFFFF;
301
302 /* Enable falling edge irq */
303 pcmp->pcmc_per = 0x100000 >> (16 * _slot_);
304 #endif /* CONFIG_IDE_8xx_PCCARD */
305
306 return 0;
307 }
308 #endif /* CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT */
309
310 /*
311 * m8xx_ide_init_ports() for a direct IDE interface _not_ using
312 * MPC8xx's internal PCMCIA interface
313 */
314 #if defined(CONFIG_IDE_EXT_DIRECT)
315 static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
316 {
317 unsigned long *p = hw->io_ports;
318 int i;
319
320 u32 ide_phy_base;
321 u32 ide_phy_end;
322 static unsigned long ide_base = 0;
323 unsigned long base;
324
325 *p = 0;
326
327 if (!ide_base) {
328
329 /* TODO:
330 * - add code to read ORx, BRx
331 */
332 ide_phy_base = CFG_ATA_BASE_ADDR;
333 ide_phy_end = CFG_ATA_BASE_ADDR + 0x200;
334
335 printk ("IDE phys mem : %08x...%08x (size %08x)\n",
336 ide_phy_base, ide_phy_end,
337 ide_phy_end - ide_phy_base);
338
339 if (!request_mem_region(ide_phy_base, 0x200, DRV_NAME)) {
340 printk(KERN_ERR "%s: resources busy\n", DRV_NAME);
341 return -EBUSY;
342 }
343
344 ide_base=(unsigned long)ioremap(ide_phy_base,
345 ide_phy_end-ide_phy_base);
346
347 #ifdef DEBUG
348 printk ("IDE virt base: %08lx\n", ide_base);
349 #endif
350 }
351
352 base = ide_base + ioport_dsc[data_port].base_off;
353 #ifdef DEBUG
354 printk ("base: %08x + %08x = %08x\n",
355 ide_base, ioport_dsc[data_port].base_off, base);
356 #endif
357
358 for (i = 0; i < IDE_NR_PORTS; ++i) {
359 #ifdef DEBUG
360 printk ("port[%d]: %08x + %08x = %08x\n",
361 i,
362 base,
363 ioport_dsc[data_port].reg_off[i],
364 i, base + ioport_dsc[data_port].reg_off[i]);
365 #endif
366 *p++ = base + ioport_dsc[data_port].reg_off[i];
367 }
368
369 /* direct connected IDE drive, i.e. external IRQ */
370 hw->irq = ioport_dsc[data_port].irq;
371 hw->ack_intr = (ide_ack_intr_t *)ide_interrupt_ack;
372
373 /* Enable Harddisk Interrupt,
374 * and make it edge sensitive
375 */
376 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
377 ((immap_t *) IMAP_ADDR)->im_siu_conf.sc_siel |=
378 (0x80000000 >> ioport_dsc[data_port].irq);
379
380 return 0;
381 }
382 #endif /* CONFIG_IDE_8xx_DIRECT */
383
384
385 /* -------------------------------------------------------------------- */
386
387
388 /* PCMCIA Timing */
389 #ifndef PCMCIA_SHT
390 #define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
391 #define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
392 #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
393 #endif
394
395 /* Calculate PIO timings */
396 static void m8xx_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
397 {
398 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
399 volatile pcmconf8xx_t *pcmp;
400 ulong timing, mask, reg;
401
402 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
403
404 mask = ~(PCMCIA_SHT(0xFF) | PCMCIA_SST(0xFF) | PCMCIA_SL(0xFF));
405
406 timing = PCMCIA_SHT(hold_time[pio] )
407 | PCMCIA_SST(ide_pio_clocks[pio].setup_time )
408 | PCMCIA_SL (ide_pio_clocks[pio].active_time)
409 ;
410
411 #if 1
412 printk ("Setting timing bits 0x%08lx in PCMCIA controller\n", timing);
413 #endif
414 if ((reg = pcmp->pcmc_por0 & mask) != 0)
415 pcmp->pcmc_por0 = reg | timing;
416
417 if ((reg = pcmp->pcmc_por1 & mask) != 0)
418 pcmp->pcmc_por1 = reg | timing;
419
420 if ((reg = pcmp->pcmc_por2 & mask) != 0)
421 pcmp->pcmc_por2 = reg | timing;
422
423 if ((reg = pcmp->pcmc_por3 & mask) != 0)
424 pcmp->pcmc_por3 = reg | timing;
425
426 if ((reg = pcmp->pcmc_por4 & mask) != 0)
427 pcmp->pcmc_por4 = reg | timing;
428
429 if ((reg = pcmp->pcmc_por5 & mask) != 0)
430 pcmp->pcmc_por5 = reg | timing;
431
432 if ((reg = pcmp->pcmc_por6 & mask) != 0)
433 pcmp->pcmc_por6 = reg | timing;
434
435 if ((reg = pcmp->pcmc_por7 & mask) != 0)
436 pcmp->pcmc_por7 = reg | timing;
437
438 #elif defined(CONFIG_IDE_EXT_DIRECT)
439
440 printk("%s[%d] %s: not implemented yet!\n",
441 __FILE__,__LINE__,__FUNCTION__);
442 #endif /* defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_PCMCIA */
443 }
444
445 static const struct ide_port_ops m8xx_port_ops = {
446 .set_pio_mode = m8xx_ide_set_pio_mode,
447 };
448
449 static void
450 ide_interrupt_ack (void *dev)
451 {
452 #ifdef CONFIG_IDE_8xx_PCCARD
453 u_int pscr, pipr;
454
455 #if (PCMCIA_SOCKETS_NO == 2)
456 u_int _slot_;
457 #endif
458
459 /* get interrupt sources */
460
461 pscr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr;
462 pipr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
463
464 /*
465 * report only if both card detect signals are the same
466 * not too nice done,
467 * we depend on that CD2 is the bit to the left of CD1...
468 */
469
470 if(_slot_==-1){
471 printk("PCMCIA slot has not been defined! Using A as default\n");
472 _slot_=0;
473 }
474
475 if(((pipr & M8XX_PCMCIA_CD2(_slot_)) >> 1) ^
476 (pipr & M8XX_PCMCIA_CD1(_slot_)) ) {
477 printk ("card detect interrupt\n");
478 }
479 /* clear the interrupt sources */
480 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = pscr;
481
482 #else /* ! CONFIG_IDE_8xx_PCCARD */
483 /*
484 * Only CONFIG_IDE_8xx_PCCARD is using the interrupt of the
485 * MPC8xx's PCMCIA controller, so there is nothing to be done here
486 * for CONFIG_IDE_8xx_DIRECT and CONFIG_IDE_EXT_DIRECT.
487 * The interrupt is handled somewhere else. -- Steven
488 */
489 #endif /* CONFIG_IDE_8xx_PCCARD */
490 }
491
492
493
494 /*
495 * CIS Tupel codes
496 */
497 #define CISTPL_NULL 0x00
498 #define CISTPL_DEVICE 0x01
499 #define CISTPL_LONGLINK_CB 0x02
500 #define CISTPL_INDIRECT 0x03
501 #define CISTPL_CONFIG_CB 0x04
502 #define CISTPL_CFTABLE_ENTRY_CB 0x05
503 #define CISTPL_LONGLINK_MFC 0x06
504 #define CISTPL_BAR 0x07
505 #define CISTPL_PWR_MGMNT 0x08
506 #define CISTPL_EXTDEVICE 0x09
507 #define CISTPL_CHECKSUM 0x10
508 #define CISTPL_LONGLINK_A 0x11
509 #define CISTPL_LONGLINK_C 0x12
510 #define CISTPL_LINKTARGET 0x13
511 #define CISTPL_NO_LINK 0x14
512 #define CISTPL_VERS_1 0x15
513 #define CISTPL_ALTSTR 0x16
514 #define CISTPL_DEVICE_A 0x17
515 #define CISTPL_JEDEC_C 0x18
516 #define CISTPL_JEDEC_A 0x19
517 #define CISTPL_CONFIG 0x1a
518 #define CISTPL_CFTABLE_ENTRY 0x1b
519 #define CISTPL_DEVICE_OC 0x1c
520 #define CISTPL_DEVICE_OA 0x1d
521 #define CISTPL_DEVICE_GEO 0x1e
522 #define CISTPL_DEVICE_GEO_A 0x1f
523 #define CISTPL_MANFID 0x20
524 #define CISTPL_FUNCID 0x21
525 #define CISTPL_FUNCE 0x22
526 #define CISTPL_SWIL 0x23
527 #define CISTPL_END 0xff
528
529 /*
530 * CIS Function ID codes
531 */
532 #define CISTPL_FUNCID_MULTI 0x00
533 #define CISTPL_FUNCID_MEMORY 0x01
534 #define CISTPL_FUNCID_SERIAL 0x02
535 #define CISTPL_FUNCID_PARALLEL 0x03
536 #define CISTPL_FUNCID_FIXED 0x04
537 #define CISTPL_FUNCID_VIDEO 0x05
538 #define CISTPL_FUNCID_NETWORK 0x06
539 #define CISTPL_FUNCID_AIMS 0x07
540 #define CISTPL_FUNCID_SCSI 0x08
541
542 /*
543 * Fixed Disk FUNCE codes
544 */
545 #define CISTPL_IDE_INTERFACE 0x01
546
547 #define CISTPL_FUNCE_IDE_IFACE 0x01
548 #define CISTPL_FUNCE_IDE_MASTER 0x02
549 #define CISTPL_FUNCE_IDE_SLAVE 0x03
550
551 /* First feature byte */
552 #define CISTPL_IDE_SILICON 0x04
553 #define CISTPL_IDE_UNIQUE 0x08
554 #define CISTPL_IDE_DUAL 0x10
555
556 /* Second feature byte */
557 #define CISTPL_IDE_HAS_SLEEP 0x01
558 #define CISTPL_IDE_HAS_STANDBY 0x02
559 #define CISTPL_IDE_HAS_IDLE 0x04
560 #define CISTPL_IDE_LOW_POWER 0x08
561 #define CISTPL_IDE_REG_INHIBIT 0x10
562 #define CISTPL_IDE_HAS_INDEX 0x20
563 #define CISTPL_IDE_IOIS16 0x40
564
565
566 /* -------------------------------------------------------------------- */
567
568
569 #define MAX_TUPEL_SZ 512
570 #define MAX_FEATURES 4
571
572 static int check_ide_device (unsigned long base)
573 {
574 volatile u8 *ident = NULL;
575 volatile u8 *feature_p[MAX_FEATURES];
576 volatile u8 *p, *start;
577 int n_features = 0;
578 u8 func_id = ~0;
579 u8 code, len;
580 unsigned short config_base = 0;
581 int found = 0;
582 int i;
583
584 #ifdef DEBUG
585 printk ("PCMCIA MEM: %08lX\n", base);
586 #endif
587 start = p = (volatile u8 *) base;
588
589 while ((p - start) < MAX_TUPEL_SZ) {
590
591 code = *p; p += 2;
592
593 if (code == 0xFF) { /* End of chain */
594 break;
595 }
596
597 len = *p; p += 2;
598 #ifdef DEBUG_PCMCIA
599 { volatile u8 *q = p;
600 printk ("\nTuple code %02x length %d\n\tData:",
601 code, len);
602
603 for (i = 0; i < len; ++i) {
604 printk (" %02x", *q);
605 q+= 2;
606 }
607 }
608 #endif /* DEBUG_PCMCIA */
609 switch (code) {
610 case CISTPL_VERS_1:
611 ident = p + 4;
612 break;
613 case CISTPL_FUNCID:
614 func_id = *p;
615 break;
616 case CISTPL_FUNCE:
617 if (n_features < MAX_FEATURES)
618 feature_p[n_features++] = p;
619 break;
620 case CISTPL_CONFIG:
621 config_base = (*(p+6) << 8) + (*(p+4));
622 default:
623 break;
624 }
625 p += 2 * len;
626 }
627
628 found = identify (ident);
629
630 if (func_id != ((u8)~0)) {
631 print_funcid (func_id);
632
633 if (func_id == CISTPL_FUNCID_FIXED)
634 found = 1;
635 else
636 return (1); /* no disk drive */
637 }
638
639 for (i=0; i<n_features; ++i) {
640 print_fixed (feature_p[i]);
641 }
642
643 if (!found) {
644 printk ("unknown card type\n");
645 return (1);
646 }
647
648 /* set level mode irq and I/O mapped device in config reg*/
649 *((u8 *)(base + config_base)) = 0x41;
650
651 return (0);
652 }
653
654 /* ------------------------------------------------------------------------- */
655
656 static void print_funcid (int func)
657 {
658 switch (func) {
659 case CISTPL_FUNCID_MULTI:
660 printk (" Multi-Function");
661 break;
662 case CISTPL_FUNCID_MEMORY:
663 printk (" Memory");
664 break;
665 case CISTPL_FUNCID_SERIAL:
666 printk (" Serial Port");
667 break;
668 case CISTPL_FUNCID_PARALLEL:
669 printk (" Parallel Port");
670 break;
671 case CISTPL_FUNCID_FIXED:
672 printk (" Fixed Disk");
673 break;
674 case CISTPL_FUNCID_VIDEO:
675 printk (" Video Adapter");
676 break;
677 case CISTPL_FUNCID_NETWORK:
678 printk (" Network Adapter");
679 break;
680 case CISTPL_FUNCID_AIMS:
681 printk (" AIMS Card");
682 break;
683 case CISTPL_FUNCID_SCSI:
684 printk (" SCSI Adapter");
685 break;
686 default:
687 printk (" Unknown");
688 break;
689 }
690 printk (" Card\n");
691 }
692
693 /* ------------------------------------------------------------------------- */
694
695 static void print_fixed (volatile u8 *p)
696 {
697 if (p == NULL)
698 return;
699
700 switch (*p) {
701 case CISTPL_FUNCE_IDE_IFACE:
702 { u8 iface = *(p+2);
703
704 printk ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
705 printk (" interface ");
706 break;
707 }
708 case CISTPL_FUNCE_IDE_MASTER:
709 case CISTPL_FUNCE_IDE_SLAVE:
710 { u8 f1 = *(p+2);
711 u8 f2 = *(p+4);
712
713 printk ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
714
715 if (f1 & CISTPL_IDE_UNIQUE)
716 printk (" [unique]");
717
718 printk ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
719
720 if (f2 & CISTPL_IDE_HAS_SLEEP)
721 printk (" [sleep]");
722
723 if (f2 & CISTPL_IDE_HAS_STANDBY)
724 printk (" [standby]");
725
726 if (f2 & CISTPL_IDE_HAS_IDLE)
727 printk (" [idle]");
728
729 if (f2 & CISTPL_IDE_LOW_POWER)
730 printk (" [low power]");
731
732 if (f2 & CISTPL_IDE_REG_INHIBIT)
733 printk (" [reg inhibit]");
734
735 if (f2 & CISTPL_IDE_HAS_INDEX)
736 printk (" [index]");
737
738 if (f2 & CISTPL_IDE_IOIS16)
739 printk (" [IOis16]");
740
741 break;
742 }
743 }
744 printk ("\n");
745 }
746
747 /* ------------------------------------------------------------------------- */
748
749
750 #define MAX_IDENT_CHARS 64
751 #define MAX_IDENT_FIELDS 4
752
753 static u8 *known_cards[] = {
754 "ARGOSY PnPIDE D5",
755 NULL
756 };
757
758 static int identify (volatile u8 *p)
759 {
760 u8 id_str[MAX_IDENT_CHARS];
761 u8 data;
762 u8 *t;
763 u8 **card;
764 int i, done;
765
766 if (p == NULL)
767 return (0); /* Don't know */
768
769 t = id_str;
770 done =0;
771
772 for (i=0; i<=4 && !done; ++i, p+=2) {
773 while ((data = *p) != '\0') {
774 if (data == 0xFF) {
775 done = 1;
776 break;
777 }
778 *t++ = data;
779 if (t == &id_str[MAX_IDENT_CHARS-1]) {
780 done = 1;
781 break;
782 }
783 p += 2;
784 }
785 if (!done)
786 *t++ = ' ';
787 }
788 *t = '\0';
789 while (--t > id_str) {
790 if (*t == ' ')
791 *t = '\0';
792 else
793 break;
794 }
795 printk ("Card ID: %s\n", id_str);
796
797 for (card=known_cards; *card; ++card) {
798 if (strcmp(*card, id_str) == 0) { /* found! */
799 return (1);
800 }
801 }
802
803 return (0); /* don't know */
804 }
805
806 static int __init mpc8xx_ide_probe(void)
807 {
808 hw_regs_t hw;
809 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
810
811 #ifdef IDE0_BASE_OFFSET
812 memset(&hw, 0, sizeof(hw));
813 if (!m8xx_ide_init_ports(&hw, 0)) {
814 ide_hwif_t *hwif = &ide_hwifs[0];
815
816 ide_init_port_hw(hwif, &hw);
817 hwif->mmio = 1;
818 hwif->pio_mask = ATA_PIO4;
819 hwif->port_ops = &m8xx_port_ops;
820
821 idx[0] = 0;
822 }
823 #ifdef IDE1_BASE_OFFSET
824 memset(&hw, 0, sizeof(hw));
825 if (!m8xx_ide_init_ports(&hw, 1)) {
826 ide_hwif_t *mate = &ide_hwifs[1];
827
828 ide_init_port_hw(mate, &hw);
829 mate->mmio = 1;
830 mate->pio_mask = ATA_PIO4;
831 mate->port_ops = &m8xx_port_ops;
832
833 idx[1] = 1;
834 }
835 #endif
836 #endif
837
838 ide_device_add(idx, NULL);
839
840 return 0;
841 }
842
843 module_init(mpc8xx_ide_probe);
844
845 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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