2 * Copyright (C) 1998-2000 Michel Aubry
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
6 * Portions copyright (c) 2001 Sun Microsystems
9 * RCC/ServerWorks IDE driver for Linux
11 * OSB4: `Open South Bridge' IDE Interface (fn 1)
12 * supports UDMA mode 2 (33 MB/s)
14 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
15 * all revisions support UDMA mode 4 (66 MB/s)
16 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
18 * *** The CSB5 does not provide ANY register ***
19 * *** to detect 80-conductor cable presence. ***
21 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
23 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
24 * controller same as the CSB6. Single channel ATA100 only.
27 * Available under NDA only. Errata info very hard to get.
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/pci.h>
35 #include <linux/ide.h>
36 #include <linux/init.h>
40 #define DRV_NAME "serverworks"
42 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
43 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
45 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
46 * can overrun their FIFOs when used with the CSB5 */
47 static const char *svwks_bad_ata100
[] = {
55 static int check_in_drive_lists (ide_drive_t
*drive
, const char **list
)
57 char *m
= (char *)&drive
->id
[ATA_ID_PROD
];
60 if (!strcmp(*list
++, m
))
65 static u8
svwks_udma_filter(ide_drive_t
*drive
)
67 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
69 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
) {
71 } else if (dev
->revision
< SVWKS_CSB5_REVISION_NEW
) {
74 u8 btr
= 0, mode
, mask
;
76 pci_read_config_byte(dev
, 0x5A, &btr
);
79 /* If someone decides to do UDMA133 on CSB5 the same
80 issue will bite so be inclusive */
81 if (mode
> 2 && check_in_drive_lists(drive
, svwks_bad_ata100
))
85 case 3: mask
= 0x3f; break;
86 case 2: mask
= 0x1f; break;
87 case 1: mask
= 0x07; break;
88 default: mask
= 0x00; break;
95 static u8
svwks_csb_check (struct pci_dev
*dev
)
97 switch (dev
->device
) {
98 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
:
99 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
:
100 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
:
101 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
:
109 static void svwks_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
111 static const u8 pio_modes
[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
112 static const u8 drive_pci
[] = { 0x41, 0x40, 0x43, 0x42 };
114 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
116 pci_write_config_byte(dev
, drive_pci
[drive
->dn
], pio_modes
[pio
]);
118 if (svwks_csb_check(dev
)) {
121 pci_read_config_word(dev
, 0x4a, &csb_pio
);
123 csb_pio
&= ~(0x0f << (4 * drive
->dn
));
124 csb_pio
|= (pio
<< (4 * drive
->dn
));
126 pci_write_config_word(dev
, 0x4a, csb_pio
);
130 static void svwks_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
132 static const u8 udma_modes
[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
133 static const u8 dma_modes
[] = { 0x77, 0x21, 0x20 };
134 static const u8 drive_pci2
[] = { 0x45, 0x44, 0x47, 0x46 };
136 ide_hwif_t
*hwif
= drive
->hwif
;
137 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
138 u8 unit
= drive
->dn
& 1;
140 u8 ultra_enable
= 0, ultra_timing
= 0, dma_timing
= 0;
142 pci_read_config_byte(dev
, (0x56|hwif
->channel
), &ultra_timing
);
143 pci_read_config_byte(dev
, 0x54, &ultra_enable
);
145 ultra_timing
&= ~(0x0F << (4*unit
));
146 ultra_enable
&= ~(0x01 << drive
->dn
);
148 if (speed
>= XFER_UDMA_0
) {
149 dma_timing
|= dma_modes
[2];
150 ultra_timing
|= (udma_modes
[speed
- XFER_UDMA_0
] << (4 * unit
));
151 ultra_enable
|= (0x01 << drive
->dn
);
152 } else if (speed
>= XFER_MW_DMA_0
)
153 dma_timing
|= dma_modes
[speed
- XFER_MW_DMA_0
];
155 pci_write_config_byte(dev
, drive_pci2
[drive
->dn
], dma_timing
);
156 pci_write_config_byte(dev
, (0x56|hwif
->channel
), ultra_timing
);
157 pci_write_config_byte(dev
, 0x54, ultra_enable
);
160 static int init_chipset_svwks(struct pci_dev
*dev
)
165 /* force Master Latency Timer value to 64 PCICLKs */
166 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x40);
168 /* OSB4 : South Bridge and IDE */
169 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
170 struct pci_dev
*isa_dev
=
171 pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
172 PCI_DEVICE_ID_SERVERWORKS_OSB4
, NULL
);
174 pci_read_config_dword(isa_dev
, 0x64, ®
);
175 reg
&= ~0x00002000; /* disable 600ns interrupt mask */
176 if(!(reg
& 0x00004000))
177 printk(KERN_DEBUG DRV_NAME
" %s: UDMA not BIOS "
178 "enabled.\n", pci_name(dev
));
179 reg
|= 0x00004000; /* enable UDMA/33 support */
180 pci_write_config_dword(isa_dev
, 0x64, reg
);
181 pci_dev_put(isa_dev
);
185 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
186 else if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
) ||
187 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
188 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) {
190 /* Third Channel Test */
191 if (!(PCI_FUNC(dev
->devfn
) & 1)) {
192 struct pci_dev
* findev
= NULL
;
194 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
195 PCI_DEVICE_ID_SERVERWORKS_CSB5
, NULL
);
197 pci_read_config_dword(findev
, 0x4C, ®4c
);
198 reg4c
&= ~0x000007FF;
201 pci_write_config_dword(findev
, 0x4C, reg4c
);
204 outb_p(0x06, 0x0c00);
205 dev
->irq
= inb_p(0x0c01);
207 struct pci_dev
* findev
= NULL
;
210 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
211 PCI_DEVICE_ID_SERVERWORKS_CSB6
, NULL
);
213 pci_read_config_byte(findev
, 0x41, ®41
);
215 pci_write_config_byte(findev
, 0x41, reg41
);
219 * This is a device pin issue on CSB6.
220 * Since there will be a future raid mode,
221 * early versions of the chipset require the
222 * interrupt pin to be set, and it is a compatibility
225 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
228 // pci_read_config_dword(dev, 0x40, &pioreg)
229 // pci_write_config_dword(dev, 0x40, 0x99999999);
230 // pci_read_config_dword(dev, 0x44, &dmareg);
231 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
232 /* setup the UDMA Control register
234 * 1. clear bit 6 to enable DMA
235 * 2. enable DMA modes with bits 0-1
239 * 11 : udma2/udma4/udma5
241 pci_read_config_byte(dev
, 0x5A, &btr
);
243 if (!(PCI_FUNC(dev
->devfn
) & 1))
246 btr
|= (dev
->revision
>= SVWKS_CSB5_REVISION_NEW
) ? 0x3 : 0x2;
247 pci_write_config_byte(dev
, 0x5A, btr
);
249 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
250 else if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
) {
251 pci_read_config_byte(dev
, 0x5A, &btr
);
254 pci_write_config_byte(dev
, 0x5A, btr
);
260 static u8
ata66_svwks_svwks(ide_hwif_t
*hwif
)
262 return ATA_CBL_PATA80
;
265 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
266 * of the subsystem device ID indicate presence of an 80-pin cable.
267 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
268 * Bit 15 set = secondary IDE channel has 80-pin cable.
269 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
270 * Bit 14 set = primary IDE channel has 80-pin cable.
272 static u8
ata66_svwks_dell(ide_hwif_t
*hwif
)
274 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
276 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
277 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
278 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
||
279 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
))
280 return ((1 << (hwif
->channel
+ 14)) &
281 dev
->subsystem_device
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
282 return ATA_CBL_PATA40
;
285 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
286 * detect issue by attaching the drives directly to the board.
287 * This check follows the Dell precedent (how scary is that?!)
289 * WARNING: this only works on Alpine hardware!
291 static u8
ata66_svwks_cobalt(ide_hwif_t
*hwif
)
293 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
295 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
&&
296 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
297 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
)
298 return ((1 << (hwif
->channel
+ 14)) &
299 dev
->subsystem_device
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
300 return ATA_CBL_PATA40
;
303 static u8
svwks_cable_detect(ide_hwif_t
*hwif
)
305 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
308 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SERVERWORKS
)
309 return ata66_svwks_svwks (hwif
);
312 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
313 return ata66_svwks_dell (hwif
);
316 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
)
317 return ata66_svwks_cobalt (hwif
);
319 /* Per Specified Design by OEM, and ASIC Architect */
320 if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
321 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
))
322 return ATA_CBL_PATA80
;
324 return ATA_CBL_PATA40
;
327 static const struct ide_port_ops osb4_port_ops
= {
328 .set_pio_mode
= svwks_set_pio_mode
,
329 .set_dma_mode
= svwks_set_dma_mode
,
332 static const struct ide_port_ops svwks_port_ops
= {
333 .set_pio_mode
= svwks_set_pio_mode
,
334 .set_dma_mode
= svwks_set_dma_mode
,
335 .udma_filter
= svwks_udma_filter
,
336 .cable_detect
= svwks_cable_detect
,
339 static const struct ide_port_info serverworks_chipsets
[] __devinitdata
= {
342 .init_chipset
= init_chipset_svwks
,
343 .port_ops
= &osb4_port_ops
,
344 .pio_mask
= ATA_PIO4
,
345 .mwdma_mask
= ATA_MWDMA2
,
346 .udma_mask
= 0x00, /* UDMA is problematic on OSB4 */
350 .init_chipset
= init_chipset_svwks
,
351 .port_ops
= &svwks_port_ops
,
352 .pio_mask
= ATA_PIO4
,
353 .mwdma_mask
= ATA_MWDMA2
,
354 .udma_mask
= ATA_UDMA5
,
358 .init_chipset
= init_chipset_svwks
,
359 .port_ops
= &svwks_port_ops
,
360 .pio_mask
= ATA_PIO4
,
361 .mwdma_mask
= ATA_MWDMA2
,
362 .udma_mask
= ATA_UDMA5
,
366 .init_chipset
= init_chipset_svwks
,
367 .port_ops
= &svwks_port_ops
,
368 .host_flags
= IDE_HFLAG_SINGLE
,
369 .pio_mask
= ATA_PIO4
,
370 .mwdma_mask
= ATA_MWDMA2
,
371 .udma_mask
= ATA_UDMA5
,
375 .init_chipset
= init_chipset_svwks
,
376 .port_ops
= &svwks_port_ops
,
377 .host_flags
= IDE_HFLAG_SINGLE
,
378 .pio_mask
= ATA_PIO4
,
379 .mwdma_mask
= ATA_MWDMA2
,
380 .udma_mask
= ATA_UDMA5
,
385 * svwks_init_one - called when a OSB/CSB is found
386 * @dev: the svwks device
387 * @id: the matching pci id
389 * Called when the PCI registration layer (or the IDE initialization)
390 * finds a device matching our IDE device tables.
393 static int __devinit
svwks_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
395 struct ide_port_info d
;
396 u8 idx
= id
->driver_data
;
398 d
= serverworks_chipsets
[idx
];
401 d
.host_flags
|= IDE_HFLAG_CLEAR_SIMPLEX
;
402 else if (idx
== 2 || idx
== 3) {
403 if ((PCI_FUNC(dev
->devfn
) & 1) == 0) {
404 if (pci_resource_start(dev
, 0) != 0x01f1)
405 d
.host_flags
|= IDE_HFLAG_NON_BOOTABLE
;
406 d
.host_flags
|= IDE_HFLAG_SINGLE
;
408 d
.host_flags
&= ~IDE_HFLAG_SINGLE
;
411 return ide_pci_init_one(dev
, &d
, NULL
);
414 static const struct pci_device_id svwks_pci_tbl
[] = {
415 { PCI_VDEVICE(SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
), 0 },
416 { PCI_VDEVICE(SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
), 1 },
417 { PCI_VDEVICE(SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
), 2 },
418 { PCI_VDEVICE(SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
), 3 },
419 { PCI_VDEVICE(SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
), 4 },
422 MODULE_DEVICE_TABLE(pci
, svwks_pci_tbl
);
424 static struct pci_driver svwks_pci_driver
= {
425 .name
= "Serverworks_IDE",
426 .id_table
= svwks_pci_tbl
,
427 .probe
= svwks_init_one
,
428 .remove
= ide_pci_remove
,
429 .suspend
= ide_pci_suspend
,
430 .resume
= ide_pci_resume
,
433 static int __init
svwks_ide_init(void)
435 return ide_pci_register_driver(&svwks_pci_driver
);
438 static void __exit
svwks_ide_exit(void)
440 pci_unregister_driver(&svwks_pci_driver
);
443 module_init(svwks_ide_init
);
444 module_exit(svwks_ide_exit
);
446 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
447 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
448 MODULE_LICENSE("GPL");