2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2013, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <trace/events/power.h>
60 #include <linux/sched.h>
61 #include <linux/notifier.h>
62 #include <linux/cpu.h>
63 #include <linux/module.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/mwait.h>
68 #define INTEL_IDLE_VERSION "0.4"
69 #define PREFIX "intel_idle: "
71 static struct cpuidle_driver intel_idle_driver
= {
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate
= CPUIDLE_STATE_MAX
- 1;
78 static unsigned int mwait_substates
;
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states
= (1 << 1); /* Default to only C1 */
85 struct cpuidle_state
*state_table
;
88 * Hardware C-state auto-demotion may not always be optimal.
89 * Indicate which enable bits to clear here.
91 unsigned long auto_demotion_disable_flags
;
92 bool disable_promotion_to_c1e
;
95 static const struct idle_cpu
*icpu
;
96 static struct cpuidle_device __percpu
*intel_idle_cpuidle_devices
;
97 static int intel_idle(struct cpuidle_device
*dev
,
98 struct cpuidle_driver
*drv
, int index
);
99 static int intel_idle_cpu_init(int cpu
);
101 static struct cpuidle_state
*cpuidle_state_table
;
104 * Set this flag for states where the HW flushes the TLB for us
105 * and so we don't need cross-calls to keep it consistent.
106 * If this flag is set, SW flushes the TLB, so even if the
107 * HW doesn't do the flushing, this flag is safe to use.
109 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
112 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
113 * the C-state (top nibble) and sub-state (bottom nibble)
114 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
116 * We store the hint at the top of our "flags" for each state.
118 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
119 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
122 * States are indexed by the cstate number,
123 * which is also the index into the MWAIT hint array.
124 * Thus C0 is a dummy.
126 static struct cpuidle_state nehalem_cstates
[] __initdata
= {
129 .desc
= "MWAIT 0x00",
130 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
132 .target_residency
= 6,
133 .enter
= &intel_idle
},
136 .desc
= "MWAIT 0x01",
137 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
139 .target_residency
= 20,
140 .enter
= &intel_idle
},
143 .desc
= "MWAIT 0x10",
144 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
146 .target_residency
= 80,
147 .enter
= &intel_idle
},
150 .desc
= "MWAIT 0x20",
151 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
153 .target_residency
= 800,
154 .enter
= &intel_idle
},
159 static struct cpuidle_state snb_cstates
[] __initdata
= {
162 .desc
= "MWAIT 0x00",
163 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
165 .target_residency
= 2,
166 .enter
= &intel_idle
},
169 .desc
= "MWAIT 0x01",
170 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
172 .target_residency
= 20,
173 .enter
= &intel_idle
},
176 .desc
= "MWAIT 0x10",
177 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
179 .target_residency
= 211,
180 .enter
= &intel_idle
},
183 .desc
= "MWAIT 0x20",
184 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
186 .target_residency
= 345,
187 .enter
= &intel_idle
},
190 .desc
= "MWAIT 0x30",
191 .flags
= MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
193 .target_residency
= 345,
194 .enter
= &intel_idle
},
199 static struct cpuidle_state ivb_cstates
[] __initdata
= {
202 .desc
= "MWAIT 0x00",
203 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
205 .target_residency
= 1,
206 .enter
= &intel_idle
},
209 .desc
= "MWAIT 0x01",
210 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
212 .target_residency
= 20,
213 .enter
= &intel_idle
},
216 .desc
= "MWAIT 0x10",
217 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
219 .target_residency
= 156,
220 .enter
= &intel_idle
},
223 .desc
= "MWAIT 0x20",
224 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
226 .target_residency
= 300,
227 .enter
= &intel_idle
},
230 .desc
= "MWAIT 0x30",
231 .flags
= MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
233 .target_residency
= 300,
234 .enter
= &intel_idle
},
239 static struct cpuidle_state hsw_cstates
[] __initdata
= {
242 .desc
= "MWAIT 0x00",
243 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
245 .target_residency
= 2,
246 .enter
= &intel_idle
},
249 .desc
= "MWAIT 0x01",
250 .flags
= MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID
,
252 .target_residency
= 20,
253 .enter
= &intel_idle
},
256 .desc
= "MWAIT 0x10",
257 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
259 .target_residency
= 100,
260 .enter
= &intel_idle
},
263 .desc
= "MWAIT 0x20",
264 .flags
= MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
266 .target_residency
= 400,
267 .enter
= &intel_idle
},
270 .desc
= "MWAIT 0x32",
271 .flags
= MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
273 .target_residency
= 500,
274 .enter
= &intel_idle
},
277 .desc
= "MWAIT 0x40",
278 .flags
= MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
280 .target_residency
= 900,
281 .enter
= &intel_idle
},
284 .desc
= "MWAIT 0x50",
285 .flags
= MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
287 .target_residency
= 1800,
288 .enter
= &intel_idle
},
291 .desc
= "MWAIT 0x60",
292 .flags
= MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
293 .exit_latency
= 2600,
294 .target_residency
= 7700,
295 .enter
= &intel_idle
},
300 static struct cpuidle_state atom_cstates
[] __initdata
= {
303 .desc
= "MWAIT 0x00",
304 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
306 .target_residency
= 20,
307 .enter
= &intel_idle
},
310 .desc
= "MWAIT 0x10",
311 .flags
= MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID
,
313 .target_residency
= 80,
314 .enter
= &intel_idle
},
317 .desc
= "MWAIT 0x30",
318 .flags
= MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
320 .target_residency
= 400,
321 .enter
= &intel_idle
},
324 .desc
= "MWAIT 0x52",
325 .flags
= MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
327 .target_residency
= 560,
328 .enter
= &intel_idle
},
332 static struct cpuidle_state avn_cstates
[] __initdata
= {
335 .desc
= "MWAIT 0x00",
336 .flags
= MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID
,
338 .target_residency
= 2,
339 .enter
= &intel_idle
},
342 .desc
= "MWAIT 0x51",
343 .flags
= MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
345 .target_residency
= 45,
346 .enter
= &intel_idle
},
351 * @dev: cpuidle_device
352 * @drv: cpuidle driver
353 * @index: index of cpuidle state
355 * Must be called under local_irq_disable().
357 static int intel_idle(struct cpuidle_device
*dev
,
358 struct cpuidle_driver
*drv
, int index
)
360 unsigned long ecx
= 1; /* break on interrupt flag */
361 struct cpuidle_state
*state
= &drv
->states
[index
];
362 unsigned long eax
= flg2MWAIT(state
->flags
);
364 int cpu
= smp_processor_id();
366 cstate
= (((eax
) >> MWAIT_SUBSTATE_SIZE
) & MWAIT_CSTATE_MASK
) + 1;
369 * leave_mm() to avoid costly and often unnecessary wakeups
370 * for flushing the user TLB's associated with the active mm.
372 if (state
->flags
& CPUIDLE_FLAG_TLB_FLUSHED
)
375 if (!(lapic_timer_reliable_states
& (1 << (cstate
))))
376 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
378 if (!current_set_polling_and_test()) {
380 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR
))
381 clflush((void *)¤t_thread_info()->flags
);
383 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
389 if (!(lapic_timer_reliable_states
& (1 << (cstate
))))
390 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
395 static void __setup_broadcast_timer(void *arg
)
397 unsigned long reason
= (unsigned long)arg
;
398 int cpu
= smp_processor_id();
401 CLOCK_EVT_NOTIFY_BROADCAST_ON
: CLOCK_EVT_NOTIFY_BROADCAST_OFF
;
403 clockevents_notify(reason
, &cpu
);
406 static int cpu_hotplug_notify(struct notifier_block
*n
,
407 unsigned long action
, void *hcpu
)
409 int hotcpu
= (unsigned long)hcpu
;
410 struct cpuidle_device
*dev
;
412 switch (action
& ~CPU_TASKS_FROZEN
) {
415 if (lapic_timer_reliable_states
!= LAPIC_TIMER_ALWAYS_RELIABLE
)
416 smp_call_function_single(hotcpu
, __setup_broadcast_timer
,
420 * Some systems can hotplug a cpu at runtime after
421 * the kernel has booted, we have to initialize the
422 * driver in this case
424 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, hotcpu
);
425 if (!dev
->registered
)
426 intel_idle_cpu_init(hotcpu
);
433 static struct notifier_block cpu_hotplug_notifier
= {
434 .notifier_call
= cpu_hotplug_notify
,
437 static void auto_demotion_disable(void *dummy
)
439 unsigned long long msr_bits
;
441 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL
, msr_bits
);
442 msr_bits
&= ~(icpu
->auto_demotion_disable_flags
);
443 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL
, msr_bits
);
445 static void c1e_promotion_disable(void *dummy
)
447 unsigned long long msr_bits
;
449 rdmsrl(MSR_IA32_POWER_CTL
, msr_bits
);
451 wrmsrl(MSR_IA32_POWER_CTL
, msr_bits
);
454 static const struct idle_cpu idle_cpu_nehalem
= {
455 .state_table
= nehalem_cstates
,
456 .auto_demotion_disable_flags
= NHM_C1_AUTO_DEMOTE
| NHM_C3_AUTO_DEMOTE
,
457 .disable_promotion_to_c1e
= true,
460 static const struct idle_cpu idle_cpu_atom
= {
461 .state_table
= atom_cstates
,
464 static const struct idle_cpu idle_cpu_lincroft
= {
465 .state_table
= atom_cstates
,
466 .auto_demotion_disable_flags
= ATM_LNC_C6_AUTO_DEMOTE
,
469 static const struct idle_cpu idle_cpu_snb
= {
470 .state_table
= snb_cstates
,
471 .disable_promotion_to_c1e
= true,
474 static const struct idle_cpu idle_cpu_ivb
= {
475 .state_table
= ivb_cstates
,
476 .disable_promotion_to_c1e
= true,
479 static const struct idle_cpu idle_cpu_hsw
= {
480 .state_table
= hsw_cstates
,
481 .disable_promotion_to_c1e
= true,
484 static const struct idle_cpu idle_cpu_avn
= {
485 .state_table
= avn_cstates
,
486 .disable_promotion_to_c1e
= true,
489 #define ICPU(model, cpu) \
490 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
492 static const struct x86_cpu_id intel_idle_ids
[] = {
493 ICPU(0x1a, idle_cpu_nehalem
),
494 ICPU(0x1e, idle_cpu_nehalem
),
495 ICPU(0x1f, idle_cpu_nehalem
),
496 ICPU(0x25, idle_cpu_nehalem
),
497 ICPU(0x2c, idle_cpu_nehalem
),
498 ICPU(0x2e, idle_cpu_nehalem
),
499 ICPU(0x1c, idle_cpu_atom
),
500 ICPU(0x26, idle_cpu_lincroft
),
501 ICPU(0x2f, idle_cpu_nehalem
),
502 ICPU(0x2a, idle_cpu_snb
),
503 ICPU(0x2d, idle_cpu_snb
),
504 ICPU(0x3a, idle_cpu_ivb
),
505 ICPU(0x3e, idle_cpu_ivb
),
506 ICPU(0x3c, idle_cpu_hsw
),
507 ICPU(0x3f, idle_cpu_hsw
),
508 ICPU(0x45, idle_cpu_hsw
),
509 ICPU(0x46, idle_cpu_hsw
),
510 ICPU(0x4D, idle_cpu_avn
),
513 MODULE_DEVICE_TABLE(x86cpu
, intel_idle_ids
);
518 static int __init
intel_idle_probe(void)
520 unsigned int eax
, ebx
, ecx
;
521 const struct x86_cpu_id
*id
;
523 if (max_cstate
== 0) {
524 pr_debug(PREFIX
"disabled\n");
528 id
= x86_match_cpu(intel_idle_ids
);
530 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
531 boot_cpu_data
.x86
== 6)
532 pr_debug(PREFIX
"does not run on family %d model %d\n",
533 boot_cpu_data
.x86
, boot_cpu_data
.x86_model
);
537 if (boot_cpu_data
.cpuid_level
< CPUID_MWAIT_LEAF
)
540 cpuid(CPUID_MWAIT_LEAF
, &eax
, &ebx
, &ecx
, &mwait_substates
);
542 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
) ||
543 !(ecx
& CPUID5_ECX_INTERRUPT_BREAK
) ||
547 pr_debug(PREFIX
"MWAIT substates: 0x%x\n", mwait_substates
);
549 icpu
= (const struct idle_cpu
*)id
->driver_data
;
550 cpuidle_state_table
= icpu
->state_table
;
552 if (boot_cpu_has(X86_FEATURE_ARAT
)) /* Always Reliable APIC Timer */
553 lapic_timer_reliable_states
= LAPIC_TIMER_ALWAYS_RELIABLE
;
555 on_each_cpu(__setup_broadcast_timer
, (void *)true, 1);
557 pr_debug(PREFIX
"v" INTEL_IDLE_VERSION
558 " model 0x%X\n", boot_cpu_data
.x86_model
);
560 pr_debug(PREFIX
"lapic_timer_reliable_states 0x%x\n",
561 lapic_timer_reliable_states
);
566 * intel_idle_cpuidle_devices_uninit()
567 * unregister, free cpuidle_devices
569 static void intel_idle_cpuidle_devices_uninit(void)
572 struct cpuidle_device
*dev
;
574 for_each_online_cpu(i
) {
575 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, i
);
576 cpuidle_unregister_device(dev
);
579 free_percpu(intel_idle_cpuidle_devices
);
583 * intel_idle_cpuidle_driver_init()
584 * allocate, initialize cpuidle_states
586 static int __init
intel_idle_cpuidle_driver_init(void)
589 struct cpuidle_driver
*drv
= &intel_idle_driver
;
591 drv
->state_count
= 1;
593 for (cstate
= 0; cstate
< CPUIDLE_STATE_MAX
; ++cstate
) {
594 int num_substates
, mwait_hint
, mwait_cstate
, mwait_substate
;
596 if (cpuidle_state_table
[cstate
].enter
== NULL
)
599 if (cstate
+ 1 > max_cstate
) {
600 printk(PREFIX
"max_cstate %d reached\n",
605 mwait_hint
= flg2MWAIT(cpuidle_state_table
[cstate
].flags
);
606 mwait_cstate
= MWAIT_HINT2CSTATE(mwait_hint
);
607 mwait_substate
= MWAIT_HINT2SUBSTATE(mwait_hint
);
609 /* does the state exist in CPUID.MWAIT? */
610 num_substates
= (mwait_substates
>> ((mwait_cstate
+ 1) * 4))
611 & MWAIT_SUBSTATE_MASK
;
613 /* if sub-state in table is not enumerated by CPUID */
614 if ((mwait_substate
+ 1) > num_substates
)
617 if (((mwait_cstate
+ 1) > 2) &&
618 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
619 mark_tsc_unstable("TSC halts in idle"
620 " states deeper than C2");
622 drv
->states
[drv
->state_count
] = /* structure copy */
623 cpuidle_state_table
[cstate
];
625 drv
->state_count
+= 1;
628 if (icpu
->auto_demotion_disable_flags
)
629 on_each_cpu(auto_demotion_disable
, NULL
, 1);
631 if (icpu
->disable_promotion_to_c1e
) /* each-cpu is redundant */
632 on_each_cpu(c1e_promotion_disable
, NULL
, 1);
639 * intel_idle_cpu_init()
640 * allocate, initialize, register cpuidle_devices
641 * @cpu: cpu/core to initialize
643 static int intel_idle_cpu_init(int cpu
)
646 struct cpuidle_device
*dev
;
648 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, cpu
);
650 dev
->state_count
= 1;
652 for (cstate
= 0; cstate
< CPUIDLE_STATE_MAX
; ++cstate
) {
653 int num_substates
, mwait_hint
, mwait_cstate
, mwait_substate
;
655 if (cpuidle_state_table
[cstate
].enter
== NULL
)
658 if (cstate
+ 1 > max_cstate
) {
659 printk(PREFIX
"max_cstate %d reached\n", max_cstate
);
663 mwait_hint
= flg2MWAIT(cpuidle_state_table
[cstate
].flags
);
664 mwait_cstate
= MWAIT_HINT2CSTATE(mwait_hint
);
665 mwait_substate
= MWAIT_HINT2SUBSTATE(mwait_hint
);
667 /* does the state exist in CPUID.MWAIT? */
668 num_substates
= (mwait_substates
>> ((mwait_cstate
+ 1) * 4))
669 & MWAIT_SUBSTATE_MASK
;
671 /* if sub-state in table is not enumerated by CPUID */
672 if ((mwait_substate
+ 1) > num_substates
)
675 dev
->state_count
+= 1;
680 if (cpuidle_register_device(dev
)) {
681 pr_debug(PREFIX
"cpuidle_register_device %d failed!\n", cpu
);
682 intel_idle_cpuidle_devices_uninit();
686 if (icpu
->auto_demotion_disable_flags
)
687 smp_call_function_single(cpu
, auto_demotion_disable
, NULL
, 1);
692 static int __init
intel_idle_init(void)
696 /* Do not load intel_idle at all for now if idle= is passed */
697 if (boot_option_idle_override
!= IDLE_NO_OVERRIDE
)
700 retval
= intel_idle_probe();
704 intel_idle_cpuidle_driver_init();
705 retval
= cpuidle_register_driver(&intel_idle_driver
);
707 struct cpuidle_driver
*drv
= cpuidle_get_driver();
708 printk(KERN_DEBUG PREFIX
"intel_idle yielding to %s",
709 drv
? drv
->name
: "none");
713 intel_idle_cpuidle_devices
= alloc_percpu(struct cpuidle_device
);
714 if (intel_idle_cpuidle_devices
== NULL
)
717 for_each_online_cpu(i
) {
718 retval
= intel_idle_cpu_init(i
);
720 cpuidle_unregister_driver(&intel_idle_driver
);
724 register_cpu_notifier(&cpu_hotplug_notifier
);
729 static void __exit
intel_idle_exit(void)
731 intel_idle_cpuidle_devices_uninit();
732 cpuidle_unregister_driver(&intel_idle_driver
);
735 if (lapic_timer_reliable_states
!= LAPIC_TIMER_ALWAYS_RELIABLE
)
736 on_each_cpu(__setup_broadcast_timer
, (void *)false, 1);
737 unregister_cpu_notifier(&cpu_hotplug_notifier
);
742 module_init(intel_idle_init
);
743 module_exit(intel_idle_exit
);
745 module_param(max_cstate
, int, 0444);
747 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
748 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION
);
749 MODULE_LICENSE("GPL");