2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
4 * Copyright 2011 Free Electrons
6 * Licensed under the GPLv2 or later.
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
26 #include <linux/platform_data/at91_adc.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
35 #define AT91_ADC_CR 0x00 /* Control Register */
36 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
37 #define AT91_ADC_START (1 << 1) /* Start Conversion */
39 #define AT91_ADC_MR 0x04 /* Mode Register */
40 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
41 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
42 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
43 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
44 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
45 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
46 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
47 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
48 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
49 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
50 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
51 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
52 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
53 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
54 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
55 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
56 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
57 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
58 #define AT91_ADC_STARTUP_(x) ((x) << 16)
59 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
60 #define AT91_ADC_SHTIM_(x) ((x) << 24)
61 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
62 #define AT91_ADC_PENDBC_(x) ((x) << 28)
64 #define AT91_ADC_TSR 0x0C
65 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
66 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
68 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
69 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
70 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
71 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
73 #define AT91_ADC_SR 0x1C /* Status Register */
74 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
75 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
76 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
77 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
78 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
79 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
81 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
82 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
84 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
85 #define AT91_ADC_LDATA (0x3ff)
87 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
88 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
89 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
90 #define AT91RL_ADC_IER_PEN (1 << 20)
91 #define AT91RL_ADC_IER_NOPEN (1 << 21)
92 #define AT91_ADC_IER_PEN (1 << 29)
93 #define AT91_ADC_IER_NOPEN (1 << 30)
94 #define AT91_ADC_IER_XRDY (1 << 20)
95 #define AT91_ADC_IER_YRDY (1 << 21)
96 #define AT91_ADC_IER_PRDY (1 << 22)
97 #define AT91_ADC_ISR_PENS (1 << 31)
99 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
100 #define AT91_ADC_DATA (0x3ff)
102 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
104 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
105 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
107 #define AT91_ADC_TSMR 0xB0
108 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
109 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
110 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
111 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
112 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
113 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
114 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
115 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
116 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
117 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
118 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
119 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
120 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
122 #define AT91_ADC_TSXPOSR 0xB4
123 #define AT91_ADC_TSYPOSR 0xB8
124 #define AT91_ADC_TSPRESSR 0xBC
126 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
127 #define AT91_ADC_TRGR_9G45 0x08
128 #define AT91_ADC_TRGR_9X5 0xC0
130 /* Trigger Register bit field */
131 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
132 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
133 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
134 #define AT91_ADC_TRGR_NONE (0 << 0)
135 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
137 #define AT91_ADC_CHAN(st, ch) \
138 (st->registers->channel_base + (ch * 4))
139 #define at91_adc_readl(st, reg) \
140 (readl_relaxed(st->reg_base + reg))
141 #define at91_adc_writel(st, reg, val) \
142 (writel_relaxed(val, st->reg_base + reg))
144 #define DRIVER_NAME "at91_adc"
145 #define MAX_POS_BITS 12
147 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
148 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
150 #define MAX_RLPOS_BITS 10
151 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
152 #define TOUCH_SHTIM 0xa
155 * struct at91_adc_reg_desc - Various informations relative to registers
156 * @channel_base: Base offset for the channel data registers
157 * @drdy_mask: Mask of the DRDY field in the relevant registers
158 (Interruptions registers mostly)
159 * @status_register: Offset of the Interrupt Status Register
160 * @trigger_register: Offset of the Trigger setup register
161 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
162 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
164 struct at91_adc_reg_desc
{
173 struct at91_adc_caps
{
174 bool has_ts
; /* Support touch screen */
175 bool has_tsmr
; /* only at91sam9x5, sama5d3 have TSMR reg */
177 * Numbers of sampling data will be averaged. Can be 0~3.
178 * Hardware can average (2 ^ ts_filter_average) sample data.
180 u8 ts_filter_average
;
181 /* Pen Detection input pull-up resistor, can be 0~3 */
182 u8 ts_pen_detect_sensitivity
;
184 /* startup time calculate function */
185 u32 (*calc_startup_ticks
)(u8 startup_time
, u32 adc_clk_khz
);
188 struct at91_adc_reg_desc registers
;
191 struct at91_adc_state
{
194 unsigned long channels_mask
;
201 void __iomem
*reg_base
;
202 struct at91_adc_reg_desc
*registers
;
206 struct iio_trigger
**trig
;
207 struct at91_adc_trigger
*trigger_list
;
211 u32 res
; /* resolution used for convertions */
212 bool low_res
; /* the resolution corresponds to the lowest one */
213 wait_queue_head_t wq_data_avail
;
214 struct at91_adc_caps
*caps
;
217 * Following ADC channels are shared by touchscreen:
219 * CH0 -- Touch screen XP/UL
220 * CH1 -- Touch screen XM/UR
221 * CH2 -- Touch screen YP/LL
222 * CH3 -- Touch screen YM/Sense
223 * CH4 -- Touch screen LR(5-wire only)
225 * The bitfields below represents the reserved channel in the
228 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
229 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
230 enum atmel_adc_ts_type touchscreen_type
;
231 struct input_dev
*ts_input
;
233 u16 ts_sample_period_val
;
234 u32 ts_pressure_threshold
;
237 bool ts_bufferedmeasure
;
242 static irqreturn_t
at91_adc_trigger_handler(int irq
, void *p
)
244 struct iio_poll_func
*pf
= p
;
245 struct iio_dev
*idev
= pf
->indio_dev
;
246 struct at91_adc_state
*st
= iio_priv(idev
);
249 for (i
= 0; i
< idev
->masklength
; i
++) {
250 if (!test_bit(i
, idev
->active_scan_mask
))
252 st
->buffer
[j
] = at91_adc_readl(st
, AT91_ADC_CHAN(st
, i
));
256 iio_push_to_buffers_with_timestamp(idev
, st
->buffer
, pf
->timestamp
);
258 iio_trigger_notify_done(idev
->trig
);
260 /* Needed to ACK the DRDY interruption */
261 at91_adc_readl(st
, AT91_ADC_LCDR
);
268 /* Handler for classic adc channel eoc trigger */
269 void handle_adc_eoc_trigger(int irq
, struct iio_dev
*idev
)
271 struct at91_adc_state
*st
= iio_priv(idev
);
273 if (iio_buffer_enabled(idev
)) {
274 disable_irq_nosync(irq
);
275 iio_trigger_poll(idev
->trig
, iio_get_time_ns());
277 st
->last_value
= at91_adc_readl(st
, AT91_ADC_LCDR
);
279 wake_up_interruptible(&st
->wq_data_avail
);
283 static int at91_ts_sample(struct at91_adc_state
*st
)
285 unsigned int xscale
, yscale
, reg
, z1
, z2
;
286 unsigned int x
, y
, pres
, xpos
, ypos
;
287 unsigned int rxp
= 1;
288 unsigned int factor
= 1000;
289 struct iio_dev
*idev
= iio_priv_to_dev(st
);
291 unsigned int xyz_mask_bits
= st
->res
;
292 unsigned int xyz_mask
= (1 << xyz_mask_bits
) - 1;
294 /* calculate position */
295 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
296 reg
= at91_adc_readl(st
, AT91_ADC_TSXPOSR
);
297 xpos
= reg
& xyz_mask
;
298 x
= (xpos
<< MAX_POS_BITS
) - xpos
;
299 xscale
= (reg
>> 16) & xyz_mask
;
301 dev_err(&idev
->dev
, "Error: xscale == 0!\n");
306 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
307 reg
= at91_adc_readl(st
, AT91_ADC_TSYPOSR
);
308 ypos
= reg
& xyz_mask
;
309 y
= (ypos
<< MAX_POS_BITS
) - ypos
;
310 yscale
= (reg
>> 16) & xyz_mask
;
312 dev_err(&idev
->dev
, "Error: yscale == 0!\n");
317 /* calculate the pressure */
318 reg
= at91_adc_readl(st
, AT91_ADC_TSPRESSR
);
320 z2
= (reg
>> 16) & xyz_mask
;
323 pres
= rxp
* (x
* factor
/ 1024) * (z2
* factor
/ z1
- factor
)
326 pres
= st
->ts_pressure_threshold
; /* no pen contacted */
328 dev_dbg(&idev
->dev
, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
329 xpos
, xscale
, ypos
, yscale
, z1
, z2
, pres
);
331 if (pres
< st
->ts_pressure_threshold
) {
332 dev_dbg(&idev
->dev
, "x = %d, y = %d, pressure = %d\n",
333 x
, y
, pres
/ factor
);
334 input_report_abs(st
->ts_input
, ABS_X
, x
);
335 input_report_abs(st
->ts_input
, ABS_Y
, y
);
336 input_report_abs(st
->ts_input
, ABS_PRESSURE
, pres
);
337 input_report_key(st
->ts_input
, BTN_TOUCH
, 1);
338 input_sync(st
->ts_input
);
340 dev_dbg(&idev
->dev
, "pressure too low: not reporting\n");
346 static irqreturn_t
at91_adc_rl_interrupt(int irq
, void *private)
348 struct iio_dev
*idev
= private;
349 struct at91_adc_state
*st
= iio_priv(idev
);
350 u32 status
= at91_adc_readl(st
, st
->registers
->status_register
);
353 status
&= at91_adc_readl(st
, AT91_ADC_IMR
);
354 if (status
& st
->registers
->drdy_mask
)
355 handle_adc_eoc_trigger(irq
, idev
);
357 if (status
& AT91RL_ADC_IER_PEN
) {
358 /* Disabling pen debounce is required to get a NOPEN irq */
359 reg
= at91_adc_readl(st
, AT91_ADC_MR
);
360 reg
&= ~AT91_ADC_PENDBC
;
361 at91_adc_writel(st
, AT91_ADC_MR
, reg
);
363 at91_adc_writel(st
, AT91_ADC_IDR
, AT91RL_ADC_IER_PEN
);
364 at91_adc_writel(st
, AT91_ADC_IER
, AT91RL_ADC_IER_NOPEN
366 /* Set up period trigger for sampling */
367 at91_adc_writel(st
, st
->registers
->trigger_register
,
368 AT91_ADC_TRGR_MOD_PERIOD_TRIG
|
369 AT91_ADC_TRGR_TRGPER_(st
->ts_sample_period_val
));
370 } else if (status
& AT91RL_ADC_IER_NOPEN
) {
371 reg
= at91_adc_readl(st
, AT91_ADC_MR
);
372 reg
|= AT91_ADC_PENDBC_(st
->ts_pendbc
) & AT91_ADC_PENDBC
;
373 at91_adc_writel(st
, AT91_ADC_MR
, reg
);
374 at91_adc_writel(st
, st
->registers
->trigger_register
,
377 at91_adc_writel(st
, AT91_ADC_IDR
, AT91RL_ADC_IER_NOPEN
379 at91_adc_writel(st
, AT91_ADC_IER
, AT91RL_ADC_IER_PEN
);
380 st
->ts_bufferedmeasure
= false;
381 input_report_key(st
->ts_input
, BTN_TOUCH
, 0);
382 input_sync(st
->ts_input
);
383 } else if (status
& AT91_ADC_EOC(3)) {
384 /* Conversion finished */
385 if (st
->ts_bufferedmeasure
) {
387 * Last measurement is always discarded, since it can
389 * Always report previous measurement
391 input_report_abs(st
->ts_input
, ABS_X
, st
->ts_prev_absx
);
392 input_report_abs(st
->ts_input
, ABS_Y
, st
->ts_prev_absy
);
393 input_report_key(st
->ts_input
, BTN_TOUCH
, 1);
394 input_sync(st
->ts_input
);
396 st
->ts_bufferedmeasure
= true;
398 /* Now make new measurement */
399 st
->ts_prev_absx
= at91_adc_readl(st
, AT91_ADC_CHAN(st
, 3))
401 st
->ts_prev_absx
/= at91_adc_readl(st
, AT91_ADC_CHAN(st
, 2));
403 st
->ts_prev_absy
= at91_adc_readl(st
, AT91_ADC_CHAN(st
, 1))
405 st
->ts_prev_absy
/= at91_adc_readl(st
, AT91_ADC_CHAN(st
, 0));
411 static irqreturn_t
at91_adc_9x5_interrupt(int irq
, void *private)
413 struct iio_dev
*idev
= private;
414 struct at91_adc_state
*st
= iio_priv(idev
);
415 u32 status
= at91_adc_readl(st
, st
->registers
->status_register
);
416 const uint32_t ts_data_irq_mask
=
421 if (status
& st
->registers
->drdy_mask
)
422 handle_adc_eoc_trigger(irq
, idev
);
424 if (status
& AT91_ADC_IER_PEN
) {
425 at91_adc_writel(st
, AT91_ADC_IDR
, AT91_ADC_IER_PEN
);
426 at91_adc_writel(st
, AT91_ADC_IER
, AT91_ADC_IER_NOPEN
|
428 /* Set up period trigger for sampling */
429 at91_adc_writel(st
, st
->registers
->trigger_register
,
430 AT91_ADC_TRGR_MOD_PERIOD_TRIG
|
431 AT91_ADC_TRGR_TRGPER_(st
->ts_sample_period_val
));
432 } else if (status
& AT91_ADC_IER_NOPEN
) {
433 at91_adc_writel(st
, st
->registers
->trigger_register
, 0);
434 at91_adc_writel(st
, AT91_ADC_IDR
, AT91_ADC_IER_NOPEN
|
436 at91_adc_writel(st
, AT91_ADC_IER
, AT91_ADC_IER_PEN
);
438 input_report_key(st
->ts_input
, BTN_TOUCH
, 0);
439 input_sync(st
->ts_input
);
440 } else if ((status
& ts_data_irq_mask
) == ts_data_irq_mask
) {
441 /* Now all touchscreen data is ready */
443 if (status
& AT91_ADC_ISR_PENS
) {
444 /* validate data by pen contact */
447 /* triggered by event that is no pen contact, just read
448 * them to clean the interrupt and discard all.
450 at91_adc_readl(st
, AT91_ADC_TSXPOSR
);
451 at91_adc_readl(st
, AT91_ADC_TSYPOSR
);
452 at91_adc_readl(st
, AT91_ADC_TSPRESSR
);
459 static int at91_adc_channel_init(struct iio_dev
*idev
)
461 struct at91_adc_state
*st
= iio_priv(idev
);
462 struct iio_chan_spec
*chan_array
, *timestamp
;
464 unsigned long rsvd_mask
= 0;
466 /* If touchscreen is enable, then reserve the adc channels */
467 if (st
->touchscreen_type
== ATMEL_ADC_TOUCHSCREEN_4WIRE
)
468 rsvd_mask
= CHAN_MASK_TOUCHSCREEN_4WIRE
;
469 else if (st
->touchscreen_type
== ATMEL_ADC_TOUCHSCREEN_5WIRE
)
470 rsvd_mask
= CHAN_MASK_TOUCHSCREEN_5WIRE
;
472 /* set up the channel mask to reserve touchscreen channels */
473 st
->channels_mask
&= ~rsvd_mask
;
475 idev
->num_channels
= bitmap_weight(&st
->channels_mask
,
476 st
->num_channels
) + 1;
478 chan_array
= devm_kzalloc(&idev
->dev
,
479 ((idev
->num_channels
+ 1) *
480 sizeof(struct iio_chan_spec
)),
486 for_each_set_bit(bit
, &st
->channels_mask
, st
->num_channels
) {
487 struct iio_chan_spec
*chan
= chan_array
+ idx
;
489 chan
->type
= IIO_VOLTAGE
;
492 chan
->scan_index
= idx
;
493 chan
->scan_type
.sign
= 'u';
494 chan
->scan_type
.realbits
= st
->res
;
495 chan
->scan_type
.storagebits
= 16;
496 chan
->info_mask_shared_by_type
= BIT(IIO_CHAN_INFO_SCALE
);
497 chan
->info_mask_separate
= BIT(IIO_CHAN_INFO_RAW
);
500 timestamp
= chan_array
+ idx
;
502 timestamp
->type
= IIO_TIMESTAMP
;
503 timestamp
->channel
= -1;
504 timestamp
->scan_index
= idx
;
505 timestamp
->scan_type
.sign
= 's';
506 timestamp
->scan_type
.realbits
= 64;
507 timestamp
->scan_type
.storagebits
= 64;
509 idev
->channels
= chan_array
;
510 return idev
->num_channels
;
513 static u8
at91_adc_get_trigger_value_by_name(struct iio_dev
*idev
,
514 struct at91_adc_trigger
*triggers
,
515 const char *trigger_name
)
517 struct at91_adc_state
*st
= iio_priv(idev
);
521 for (i
= 0; i
< st
->trigger_number
; i
++) {
522 char *name
= kasprintf(GFP_KERNEL
,
530 if (strcmp(trigger_name
, name
) == 0) {
531 value
= triggers
[i
].value
;
542 static int at91_adc_configure_trigger(struct iio_trigger
*trig
, bool state
)
544 struct iio_dev
*idev
= iio_trigger_get_drvdata(trig
);
545 struct at91_adc_state
*st
= iio_priv(idev
);
546 struct iio_buffer
*buffer
= idev
->buffer
;
547 struct at91_adc_reg_desc
*reg
= st
->registers
;
548 u32 status
= at91_adc_readl(st
, reg
->trigger_register
);
552 value
= at91_adc_get_trigger_value_by_name(idev
,
559 st
->buffer
= kmalloc(idev
->scan_bytes
, GFP_KERNEL
);
560 if (st
->buffer
== NULL
)
563 at91_adc_writel(st
, reg
->trigger_register
,
566 for_each_set_bit(bit
, buffer
->scan_mask
,
568 struct iio_chan_spec
const *chan
= idev
->channels
+ bit
;
569 at91_adc_writel(st
, AT91_ADC_CHER
,
570 AT91_ADC_CH(chan
->channel
));
573 at91_adc_writel(st
, AT91_ADC_IER
, reg
->drdy_mask
);
576 at91_adc_writel(st
, AT91_ADC_IDR
, reg
->drdy_mask
);
578 at91_adc_writel(st
, reg
->trigger_register
,
581 for_each_set_bit(bit
, buffer
->scan_mask
,
583 struct iio_chan_spec
const *chan
= idev
->channels
+ bit
;
584 at91_adc_writel(st
, AT91_ADC_CHDR
,
585 AT91_ADC_CH(chan
->channel
));
593 static const struct iio_trigger_ops at91_adc_trigger_ops
= {
594 .owner
= THIS_MODULE
,
595 .set_trigger_state
= &at91_adc_configure_trigger
,
598 static struct iio_trigger
*at91_adc_allocate_trigger(struct iio_dev
*idev
,
599 struct at91_adc_trigger
*trigger
)
601 struct iio_trigger
*trig
;
604 trig
= iio_trigger_alloc("%s-dev%d-%s", idev
->name
,
605 idev
->id
, trigger
->name
);
609 trig
->dev
.parent
= idev
->dev
.parent
;
610 iio_trigger_set_drvdata(trig
, idev
);
611 trig
->ops
= &at91_adc_trigger_ops
;
613 ret
= iio_trigger_register(trig
);
620 static int at91_adc_trigger_init(struct iio_dev
*idev
)
622 struct at91_adc_state
*st
= iio_priv(idev
);
625 st
->trig
= devm_kzalloc(&idev
->dev
,
626 st
->trigger_number
* sizeof(*st
->trig
),
629 if (st
->trig
== NULL
) {
634 for (i
= 0; i
< st
->trigger_number
; i
++) {
635 if (st
->trigger_list
[i
].is_external
&& !(st
->use_external
))
638 st
->trig
[i
] = at91_adc_allocate_trigger(idev
,
639 st
->trigger_list
+ i
);
640 if (st
->trig
[i
] == NULL
) {
642 "Could not allocate trigger %d\n", i
);
651 for (i
--; i
>= 0; i
--) {
652 iio_trigger_unregister(st
->trig
[i
]);
653 iio_trigger_free(st
->trig
[i
]);
659 static void at91_adc_trigger_remove(struct iio_dev
*idev
)
661 struct at91_adc_state
*st
= iio_priv(idev
);
664 for (i
= 0; i
< st
->trigger_number
; i
++) {
665 iio_trigger_unregister(st
->trig
[i
]);
666 iio_trigger_free(st
->trig
[i
]);
670 static int at91_adc_buffer_init(struct iio_dev
*idev
)
672 return iio_triggered_buffer_setup(idev
, &iio_pollfunc_store_time
,
673 &at91_adc_trigger_handler
, NULL
);
676 static void at91_adc_buffer_remove(struct iio_dev
*idev
)
678 iio_triggered_buffer_cleanup(idev
);
681 static int at91_adc_read_raw(struct iio_dev
*idev
,
682 struct iio_chan_spec
const *chan
,
683 int *val
, int *val2
, long mask
)
685 struct at91_adc_state
*st
= iio_priv(idev
);
689 case IIO_CHAN_INFO_RAW
:
690 mutex_lock(&st
->lock
);
692 at91_adc_writel(st
, AT91_ADC_CHER
,
693 AT91_ADC_CH(chan
->channel
));
694 at91_adc_writel(st
, AT91_ADC_IER
, st
->registers
->drdy_mask
);
695 at91_adc_writel(st
, AT91_ADC_CR
, AT91_ADC_START
);
697 ret
= wait_event_interruptible_timeout(st
->wq_data_avail
,
699 msecs_to_jiffies(1000));
703 mutex_unlock(&st
->lock
);
707 *val
= st
->last_value
;
709 at91_adc_writel(st
, AT91_ADC_CHDR
,
710 AT91_ADC_CH(chan
->channel
));
711 at91_adc_writel(st
, AT91_ADC_IDR
, st
->registers
->drdy_mask
);
715 mutex_unlock(&st
->lock
);
718 case IIO_CHAN_INFO_SCALE
:
720 *val2
= chan
->scan_type
.realbits
;
721 return IIO_VAL_FRACTIONAL_LOG2
;
728 static int at91_adc_of_get_resolution(struct at91_adc_state
*st
,
729 struct platform_device
*pdev
)
731 struct iio_dev
*idev
= iio_priv_to_dev(st
);
732 struct device_node
*np
= pdev
->dev
.of_node
;
733 int count
, i
, ret
= 0;
737 count
= of_property_count_strings(np
, "atmel,adc-res-names");
739 dev_err(&idev
->dev
, "You must specified at least two resolution names for "
740 "adc-res-names property in the DT\n");
744 resolutions
= kmalloc(count
* sizeof(*resolutions
), GFP_KERNEL
);
748 if (of_property_read_u32_array(np
, "atmel,adc-res", resolutions
, count
)) {
749 dev_err(&idev
->dev
, "Missing adc-res property in the DT.\n");
754 if (of_property_read_string(np
, "atmel,adc-use-res", (const char **)&res_name
))
755 res_name
= "highres";
757 for (i
= 0; i
< count
; i
++) {
758 if (of_property_read_string_index(np
, "atmel,adc-res-names", i
, (const char **)&s
))
761 if (strcmp(res_name
, s
))
764 st
->res
= resolutions
[i
];
765 if (!strcmp(res_name
, "lowres"))
770 dev_info(&idev
->dev
, "Resolution used: %u bits\n", st
->res
);
774 dev_err(&idev
->dev
, "There is no resolution for %s\n", res_name
);
781 static u32
calc_startup_ticks_9260(u8 startup_time
, u32 adc_clk_khz
)
784 * Number of ticks needed to cover the startup time of the ADC
785 * as defined in the electrical characteristics of the board,
786 * divided by 8. The formula thus is :
787 * Startup Time = (ticks + 1) * 8 / ADC Clock
789 return round_up((startup_time
* adc_clk_khz
/ 1000) - 1, 8) / 8;
792 static u32
calc_startup_ticks_9x5(u8 startup_time
, u32 adc_clk_khz
)
795 * For sama5d3x and at91sam9x5, the formula changes to:
796 * Startup Time = <lookup_table_value> / ADC Clock
798 const int startup_lookup
[] = {
804 int i
, size
= ARRAY_SIZE(startup_lookup
);
807 ticks
= startup_time
* adc_clk_khz
/ 1000;
808 for (i
= 0; i
< size
; i
++)
809 if (ticks
< startup_lookup
[i
])
814 /* Reach the end of lookup table */
820 static const struct of_device_id at91_adc_dt_ids
[];
822 static int at91_adc_probe_dt_ts(struct device_node
*node
,
823 struct at91_adc_state
*st
, struct device
*dev
)
828 ret
= of_property_read_u32(node
, "atmel,adc-ts-wires", &prop
);
830 dev_info(dev
, "ADC Touch screen is disabled.\n");
837 st
->touchscreen_type
= prop
;
840 dev_err(dev
, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop
);
844 if (!st
->caps
->has_tsmr
)
847 of_property_read_u32(node
, "atmel,adc-ts-pressure-threshold", &prop
);
848 st
->ts_pressure_threshold
= prop
;
849 if (st
->ts_pressure_threshold
) {
852 dev_err(dev
, "Invalid pressure threshold for the touchscreen\n");
857 static int at91_adc_probe_dt(struct at91_adc_state
*st
,
858 struct platform_device
*pdev
)
860 struct iio_dev
*idev
= iio_priv_to_dev(st
);
861 struct device_node
*node
= pdev
->dev
.of_node
;
862 struct device_node
*trig_node
;
869 st
->caps
= (struct at91_adc_caps
*)
870 of_match_device(at91_adc_dt_ids
, &pdev
->dev
)->data
;
872 st
->use_external
= of_property_read_bool(node
, "atmel,adc-use-external-triggers");
874 if (of_property_read_u32(node
, "atmel,adc-channels-used", &prop
)) {
875 dev_err(&idev
->dev
, "Missing adc-channels-used property in the DT.\n");
879 st
->channels_mask
= prop
;
881 st
->sleep_mode
= of_property_read_bool(node
, "atmel,adc-sleep-mode");
883 if (of_property_read_u32(node
, "atmel,adc-startup-time", &prop
)) {
884 dev_err(&idev
->dev
, "Missing adc-startup-time property in the DT.\n");
888 st
->startup_time
= prop
;
891 of_property_read_u32(node
, "atmel,adc-sample-hold-time", &prop
);
892 st
->sample_hold_time
= prop
;
894 if (of_property_read_u32(node
, "atmel,adc-vref", &prop
)) {
895 dev_err(&idev
->dev
, "Missing adc-vref property in the DT.\n");
901 ret
= at91_adc_of_get_resolution(st
, pdev
);
905 st
->registers
= &st
->caps
->registers
;
906 st
->num_channels
= st
->caps
->num_channels
;
907 st
->trigger_number
= of_get_child_count(node
);
908 st
->trigger_list
= devm_kzalloc(&idev
->dev
, st
->trigger_number
*
909 sizeof(struct at91_adc_trigger
),
911 if (!st
->trigger_list
) {
912 dev_err(&idev
->dev
, "Could not allocate trigger list memory.\n");
917 for_each_child_of_node(node
, trig_node
) {
918 struct at91_adc_trigger
*trig
= st
->trigger_list
+ i
;
921 if (of_property_read_string(trig_node
, "trigger-name", &name
)) {
922 dev_err(&idev
->dev
, "Missing trigger-name property in the DT.\n");
928 if (of_property_read_u32(trig_node
, "trigger-value", &prop
)) {
929 dev_err(&idev
->dev
, "Missing trigger-value property in the DT.\n");
934 trig
->is_external
= of_property_read_bool(trig_node
, "trigger-external");
938 /* Check if touchscreen is supported. */
939 if (st
->caps
->has_ts
)
940 return at91_adc_probe_dt_ts(node
, st
, &idev
->dev
);
942 dev_info(&idev
->dev
, "not support touchscreen in the adc compatible string.\n");
950 static int at91_adc_probe_pdata(struct at91_adc_state
*st
,
951 struct platform_device
*pdev
)
953 struct at91_adc_data
*pdata
= pdev
->dev
.platform_data
;
958 st
->caps
= (struct at91_adc_caps
*)
959 platform_get_device_id(pdev
)->driver_data
;
961 st
->use_external
= pdata
->use_external_triggers
;
962 st
->vref_mv
= pdata
->vref
;
963 st
->channels_mask
= pdata
->channels_used
;
964 st
->num_channels
= st
->caps
->num_channels
;
965 st
->startup_time
= pdata
->startup_time
;
966 st
->trigger_number
= pdata
->trigger_number
;
967 st
->trigger_list
= pdata
->trigger_list
;
968 st
->registers
= &st
->caps
->registers
;
969 st
->touchscreen_type
= pdata
->touchscreen_type
;
974 static const struct iio_info at91_adc_info
= {
975 .driver_module
= THIS_MODULE
,
976 .read_raw
= &at91_adc_read_raw
,
979 /* Touchscreen related functions */
980 static int atmel_ts_open(struct input_dev
*dev
)
982 struct at91_adc_state
*st
= input_get_drvdata(dev
);
984 if (st
->caps
->has_tsmr
)
985 at91_adc_writel(st
, AT91_ADC_IER
, AT91_ADC_IER_PEN
);
987 at91_adc_writel(st
, AT91_ADC_IER
, AT91RL_ADC_IER_PEN
);
991 static void atmel_ts_close(struct input_dev
*dev
)
993 struct at91_adc_state
*st
= input_get_drvdata(dev
);
995 if (st
->caps
->has_tsmr
)
996 at91_adc_writel(st
, AT91_ADC_IDR
, AT91_ADC_IER_PEN
);
998 at91_adc_writel(st
, AT91_ADC_IDR
, AT91RL_ADC_IER_PEN
);
1001 static int at91_ts_hw_init(struct at91_adc_state
*st
, u32 adc_clk_khz
)
1006 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1008 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1010 st
->ts_pendbc
= round_up(TOUCH_PEN_DETECT_DEBOUNCE_US
* adc_clk_khz
/
1013 while (st
->ts_pendbc
>> ++i
)
1014 ; /* Empty! Find the shift offset */
1015 if (abs(st
->ts_pendbc
- (1 << i
)) < abs(st
->ts_pendbc
- (1 << (i
- 1))))
1018 st
->ts_pendbc
= i
- 1;
1020 if (!st
->caps
->has_tsmr
) {
1021 reg
= at91_adc_readl(st
, AT91_ADC_MR
);
1022 reg
|= AT91_ADC_TSAMOD_TS_ONLY_MODE
| AT91_ADC_PENDET
;
1024 reg
|= AT91_ADC_PENDBC_(st
->ts_pendbc
) & AT91_ADC_PENDBC
;
1025 at91_adc_writel(st
, AT91_ADC_MR
, reg
);
1027 reg
= AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM
) & AT91_ADC_TSR_SHTIM
;
1028 at91_adc_writel(st
, AT91_ADC_TSR
, reg
);
1030 st
->ts_sample_period_val
= round_up((TOUCH_SAMPLE_PERIOD_US_RL
*
1031 adc_clk_khz
/ 1000) - 1, 1);
1036 if (st
->touchscreen_type
== ATMEL_ADC_TOUCHSCREEN_4WIRE
)
1037 reg
= AT91_ADC_TSMR_TSMODE_4WIRE_PRESS
;
1039 reg
= AT91_ADC_TSMR_TSMODE_5WIRE
;
1041 reg
|= AT91_ADC_TSMR_TSAV_(st
->caps
->ts_filter_average
)
1042 & AT91_ADC_TSMR_TSAV
;
1043 reg
|= AT91_ADC_TSMR_PENDBC_(st
->ts_pendbc
) & AT91_ADC_TSMR_PENDBC
;
1044 reg
|= AT91_ADC_TSMR_NOTSDMA
;
1045 reg
|= AT91_ADC_TSMR_PENDET_ENA
;
1046 reg
|= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1048 at91_adc_writel(st
, AT91_ADC_TSMR
, reg
);
1050 /* Change adc internal resistor value for better pen detection,
1051 * default value is 100 kOhm.
1052 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1053 * option only available on ES2 and higher
1055 at91_adc_writel(st
, AT91_ADC_ACR
, st
->caps
->ts_pen_detect_sensitivity
1056 & AT91_ADC_ACR_PENDETSENS
);
1058 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1059 st
->ts_sample_period_val
= round_up((TOUCH_SAMPLE_PERIOD_US
*
1060 adc_clk_khz
/ 1000) - 1, 1);
1065 static int at91_ts_register(struct at91_adc_state
*st
,
1066 struct platform_device
*pdev
)
1068 struct input_dev
*input
;
1069 struct iio_dev
*idev
= iio_priv_to_dev(st
);
1072 input
= input_allocate_device();
1074 dev_err(&idev
->dev
, "Failed to allocate TS device!\n");
1078 input
->name
= DRIVER_NAME
;
1079 input
->id
.bustype
= BUS_HOST
;
1080 input
->dev
.parent
= &pdev
->dev
;
1081 input
->open
= atmel_ts_open
;
1082 input
->close
= atmel_ts_close
;
1084 __set_bit(EV_ABS
, input
->evbit
);
1085 __set_bit(EV_KEY
, input
->evbit
);
1086 __set_bit(BTN_TOUCH
, input
->keybit
);
1087 if (st
->caps
->has_tsmr
) {
1088 input_set_abs_params(input
, ABS_X
, 0, (1 << MAX_POS_BITS
) - 1,
1090 input_set_abs_params(input
, ABS_Y
, 0, (1 << MAX_POS_BITS
) - 1,
1092 input_set_abs_params(input
, ABS_PRESSURE
, 0, 0xffffff, 0, 0);
1094 if (st
->touchscreen_type
!= ATMEL_ADC_TOUCHSCREEN_4WIRE
) {
1096 "This touchscreen controller only support 4 wires\n");
1101 input_set_abs_params(input
, ABS_X
, 0, (1 << MAX_RLPOS_BITS
) - 1,
1103 input_set_abs_params(input
, ABS_Y
, 0, (1 << MAX_RLPOS_BITS
) - 1,
1107 st
->ts_input
= input
;
1108 input_set_drvdata(input
, st
);
1110 ret
= input_register_device(input
);
1117 input_free_device(st
->ts_input
);
1121 static void at91_ts_unregister(struct at91_adc_state
*st
)
1123 input_unregister_device(st
->ts_input
);
1126 static int at91_adc_probe(struct platform_device
*pdev
)
1128 unsigned int prsc
, mstrclk
, ticks
, adc_clk
, adc_clk_khz
, shtim
;
1130 struct iio_dev
*idev
;
1131 struct at91_adc_state
*st
;
1132 struct resource
*res
;
1135 idev
= devm_iio_device_alloc(&pdev
->dev
, sizeof(struct at91_adc_state
));
1139 st
= iio_priv(idev
);
1141 if (pdev
->dev
.of_node
)
1142 ret
= at91_adc_probe_dt(st
, pdev
);
1144 ret
= at91_adc_probe_pdata(st
, pdev
);
1147 dev_err(&pdev
->dev
, "No platform data available.\n");
1151 platform_set_drvdata(pdev
, idev
);
1153 idev
->dev
.parent
= &pdev
->dev
;
1154 idev
->name
= dev_name(&pdev
->dev
);
1155 idev
->modes
= INDIO_DIRECT_MODE
;
1156 idev
->info
= &at91_adc_info
;
1158 st
->irq
= platform_get_irq(pdev
, 0);
1160 dev_err(&pdev
->dev
, "No IRQ ID is designated\n");
1164 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1166 st
->reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1167 if (IS_ERR(st
->reg_base
)) {
1168 return PTR_ERR(st
->reg_base
);
1172 * Disable all IRQs before setting up the handler
1174 at91_adc_writel(st
, AT91_ADC_CR
, AT91_ADC_SWRST
);
1175 at91_adc_writel(st
, AT91_ADC_IDR
, 0xFFFFFFFF);
1177 if (st
->caps
->has_tsmr
)
1178 ret
= request_irq(st
->irq
, at91_adc_9x5_interrupt
, 0,
1179 pdev
->dev
.driver
->name
, idev
);
1181 ret
= request_irq(st
->irq
, at91_adc_rl_interrupt
, 0,
1182 pdev
->dev
.driver
->name
, idev
);
1184 dev_err(&pdev
->dev
, "Failed to allocate IRQ.\n");
1188 st
->clk
= devm_clk_get(&pdev
->dev
, "adc_clk");
1189 if (IS_ERR(st
->clk
)) {
1190 dev_err(&pdev
->dev
, "Failed to get the clock.\n");
1191 ret
= PTR_ERR(st
->clk
);
1192 goto error_free_irq
;
1195 ret
= clk_prepare_enable(st
->clk
);
1198 "Could not prepare or enable the clock.\n");
1199 goto error_free_irq
;
1202 st
->adc_clk
= devm_clk_get(&pdev
->dev
, "adc_op_clk");
1203 if (IS_ERR(st
->adc_clk
)) {
1204 dev_err(&pdev
->dev
, "Failed to get the ADC clock.\n");
1205 ret
= PTR_ERR(st
->adc_clk
);
1206 goto error_disable_clk
;
1209 ret
= clk_prepare_enable(st
->adc_clk
);
1212 "Could not prepare or enable the ADC clock.\n");
1213 goto error_disable_clk
;
1217 * Prescaler rate computation using the formula from the Atmel's
1218 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1219 * specified by the electrical characteristics of the board.
1221 mstrclk
= clk_get_rate(st
->clk
);
1222 adc_clk
= clk_get_rate(st
->adc_clk
);
1223 adc_clk_khz
= adc_clk
/ 1000;
1225 dev_dbg(&pdev
->dev
, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1228 prsc
= (mstrclk
/ (2 * adc_clk
)) - 1;
1230 if (!st
->startup_time
) {
1231 dev_err(&pdev
->dev
, "No startup time available.\n");
1233 goto error_disable_adc_clk
;
1235 ticks
= (*st
->caps
->calc_startup_ticks
)(st
->startup_time
, adc_clk_khz
);
1238 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1239 * the best converted final value between two channels selection
1240 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1242 if (st
->sample_hold_time
> 0)
1243 shtim
= round_up((st
->sample_hold_time
* adc_clk_khz
/ 1000)
1248 reg
= AT91_ADC_PRESCAL_(prsc
) & st
->registers
->mr_prescal_mask
;
1249 reg
|= AT91_ADC_STARTUP_(ticks
) & st
->registers
->mr_startup_mask
;
1251 reg
|= AT91_ADC_LOWRES
;
1253 reg
|= AT91_ADC_SLEEP
;
1254 reg
|= AT91_ADC_SHTIM_(shtim
) & AT91_ADC_SHTIM
;
1255 at91_adc_writel(st
, AT91_ADC_MR
, reg
);
1257 /* Setup the ADC channels available on the board */
1258 ret
= at91_adc_channel_init(idev
);
1260 dev_err(&pdev
->dev
, "Couldn't initialize the channels.\n");
1261 goto error_disable_adc_clk
;
1264 init_waitqueue_head(&st
->wq_data_avail
);
1265 mutex_init(&st
->lock
);
1268 * Since touch screen will set trigger register as period trigger. So
1269 * when touch screen is enabled, then we have to disable hardware
1270 * trigger for classic adc.
1272 if (!st
->touchscreen_type
) {
1273 ret
= at91_adc_buffer_init(idev
);
1275 dev_err(&pdev
->dev
, "Couldn't initialize the buffer.\n");
1276 goto error_disable_adc_clk
;
1279 ret
= at91_adc_trigger_init(idev
);
1281 dev_err(&pdev
->dev
, "Couldn't setup the triggers.\n");
1282 at91_adc_buffer_remove(idev
);
1283 goto error_disable_adc_clk
;
1286 ret
= at91_ts_register(st
, pdev
);
1288 goto error_disable_adc_clk
;
1290 at91_ts_hw_init(st
, adc_clk_khz
);
1293 ret
= iio_device_register(idev
);
1295 dev_err(&pdev
->dev
, "Couldn't register the device.\n");
1296 goto error_iio_device_register
;
1301 error_iio_device_register
:
1302 if (!st
->touchscreen_type
) {
1303 at91_adc_trigger_remove(idev
);
1304 at91_adc_buffer_remove(idev
);
1306 at91_ts_unregister(st
);
1308 error_disable_adc_clk
:
1309 clk_disable_unprepare(st
->adc_clk
);
1311 clk_disable_unprepare(st
->clk
);
1313 free_irq(st
->irq
, idev
);
1317 static int at91_adc_remove(struct platform_device
*pdev
)
1319 struct iio_dev
*idev
= platform_get_drvdata(pdev
);
1320 struct at91_adc_state
*st
= iio_priv(idev
);
1322 iio_device_unregister(idev
);
1323 if (!st
->touchscreen_type
) {
1324 at91_adc_trigger_remove(idev
);
1325 at91_adc_buffer_remove(idev
);
1327 at91_ts_unregister(st
);
1329 clk_disable_unprepare(st
->adc_clk
);
1330 clk_disable_unprepare(st
->clk
);
1331 free_irq(st
->irq
, idev
);
1336 static struct at91_adc_caps at91sam9260_caps
= {
1337 .calc_startup_ticks
= calc_startup_ticks_9260
,
1340 .channel_base
= AT91_ADC_CHR(0),
1341 .drdy_mask
= AT91_ADC_DRDY
,
1342 .status_register
= AT91_ADC_SR
,
1343 .trigger_register
= AT91_ADC_TRGR_9260
,
1344 .mr_prescal_mask
= AT91_ADC_PRESCAL_9260
,
1345 .mr_startup_mask
= AT91_ADC_STARTUP_9260
,
1349 static struct at91_adc_caps at91sam9rl_caps
= {
1351 .calc_startup_ticks
= calc_startup_ticks_9260
, /* same as 9260 */
1354 .channel_base
= AT91_ADC_CHR(0),
1355 .drdy_mask
= AT91_ADC_DRDY
,
1356 .status_register
= AT91_ADC_SR
,
1357 .trigger_register
= AT91_ADC_TRGR_9G45
,
1358 .mr_prescal_mask
= AT91_ADC_PRESCAL_9260
,
1359 .mr_startup_mask
= AT91_ADC_STARTUP_9G45
,
1363 static struct at91_adc_caps at91sam9g45_caps
= {
1365 .calc_startup_ticks
= calc_startup_ticks_9260
, /* same as 9260 */
1368 .channel_base
= AT91_ADC_CHR(0),
1369 .drdy_mask
= AT91_ADC_DRDY
,
1370 .status_register
= AT91_ADC_SR
,
1371 .trigger_register
= AT91_ADC_TRGR_9G45
,
1372 .mr_prescal_mask
= AT91_ADC_PRESCAL_9G45
,
1373 .mr_startup_mask
= AT91_ADC_STARTUP_9G45
,
1377 static struct at91_adc_caps at91sam9x5_caps
= {
1380 .ts_filter_average
= 3,
1381 .ts_pen_detect_sensitivity
= 2,
1382 .calc_startup_ticks
= calc_startup_ticks_9x5
,
1385 .channel_base
= AT91_ADC_CDR0_9X5
,
1386 .drdy_mask
= AT91_ADC_SR_DRDY_9X5
,
1387 .status_register
= AT91_ADC_SR_9X5
,
1388 .trigger_register
= AT91_ADC_TRGR_9X5
,
1389 /* prescal mask is same as 9G45 */
1390 .mr_prescal_mask
= AT91_ADC_PRESCAL_9G45
,
1391 .mr_startup_mask
= AT91_ADC_STARTUP_9X5
,
1395 static const struct of_device_id at91_adc_dt_ids
[] = {
1396 { .compatible
= "atmel,at91sam9260-adc", .data
= &at91sam9260_caps
},
1397 { .compatible
= "atmel,at91sam9rl-adc", .data
= &at91sam9rl_caps
},
1398 { .compatible
= "atmel,at91sam9g45-adc", .data
= &at91sam9g45_caps
},
1399 { .compatible
= "atmel,at91sam9x5-adc", .data
= &at91sam9x5_caps
},
1402 MODULE_DEVICE_TABLE(of
, at91_adc_dt_ids
);
1404 static const struct platform_device_id at91_adc_ids
[] = {
1406 .name
= "at91sam9260-adc",
1407 .driver_data
= (unsigned long)&at91sam9260_caps
,
1409 .name
= "at91sam9rl-adc",
1410 .driver_data
= (unsigned long)&at91sam9rl_caps
,
1412 .name
= "at91sam9g45-adc",
1413 .driver_data
= (unsigned long)&at91sam9g45_caps
,
1415 .name
= "at91sam9x5-adc",
1416 .driver_data
= (unsigned long)&at91sam9x5_caps
,
1421 MODULE_DEVICE_TABLE(platform
, at91_adc_ids
);
1423 static struct platform_driver at91_adc_driver
= {
1424 .probe
= at91_adc_probe
,
1425 .remove
= at91_adc_remove
,
1426 .id_table
= at91_adc_ids
,
1428 .name
= DRIVER_NAME
,
1429 .of_match_table
= of_match_ptr(at91_adc_dt_ids
),
1433 module_platform_driver(at91_adc_driver
);
1435 MODULE_LICENSE("GPL");
1436 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1437 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");