drivers/iio/adc/exynos_adc.c

   1 /*
   2  *  exynos_adc.c - Support for ADC in EXYNOS SoCs
   3  *
   4  *  8 ~ 10 channel, 10/12-bit ADC
   5  *
   6  *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/clk.h>
  31 #include <linux/completion.h>
  32 #include <linux/of.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/err.h>
  37
  38 #include <linux/iio/iio.h>
  39 #include <linux/iio/machine.h>
  40 #include <linux/iio/driver.h>
  41
  42 enum adc_version {
  43         ADC_V1,
  44         ADC_V2
  45 };
  46
  47 /* EXYNOS4412/5250 ADC_V1 registers definitions */
  48 #define ADC_V1_CON(x)           ((x) + 0x00)
  49 #define ADC_V1_DLY(x)           ((x) + 0x08)
  50 #define ADC_V1_DATX(x)          ((x) + 0x0C)
  51 #define ADC_V1_INTCLR(x)        ((x) + 0x18)
  52 #define ADC_V1_MUX(x)           ((x) + 0x1c)
  53
  54 /* Future ADC_V2 registers definitions */
  55 #define ADC_V2_CON1(x)          ((x) + 0x00)
  56 #define ADC_V2_CON2(x)          ((x) + 0x04)
  57 #define ADC_V2_STAT(x)          ((x) + 0x08)
  58 #define ADC_V2_INT_EN(x)        ((x) + 0x10)
  59 #define ADC_V2_INT_ST(x)        ((x) + 0x14)
  60 #define ADC_V2_VER(x)           ((x) + 0x20)
  61
  62 /* Bit definitions for ADC_V1 */
  63 #define ADC_V1_CON_RES          (1u << 16)
  64 #define ADC_V1_CON_PRSCEN       (1u << 14)
  65 #define ADC_V1_CON_PRSCLV(x)    (((x) & 0xFF) << 6)
  66 #define ADC_V1_CON_STANDBY      (1u << 2)
  67
  68 /* Bit definitions for ADC_V2 */
  69 #define ADC_V2_CON1_SOFT_RESET  (1u << 2)
  70
  71 #define ADC_V2_CON2_OSEL        (1u << 10)
  72 #define ADC_V2_CON2_ESEL        (1u << 9)
  73 #define ADC_V2_CON2_HIGHF       (1u << 8)
  74 #define ADC_V2_CON2_C_TIME(x)   (((x) & 7) << 4)
  75 #define ADC_V2_CON2_ACH_SEL(x)  (((x) & 0xF) << 0)
  76 #define ADC_V2_CON2_ACH_MASK    0xF
  77
  78 #define MAX_ADC_V2_CHANNELS     10
  79 #define MAX_ADC_V1_CHANNELS     8
  80
  81 /* Bit definitions common for ADC_V1 and ADC_V2 */
  82 #define ADC_CON_EN_START        (1u << 0)
  83 #define ADC_DATX_MASK           0xFFF
  84
  85 #define EXYNOS_ADC_TIMEOUT      (msecs_to_jiffies(100))
  86
  87 struct exynos_adc {
  88         void __iomem            *regs;
  89         void __iomem            *enable_reg;
  90         struct clk              *clk;
  91         unsigned int            irq;
  92         struct regulator        *vdd;
  93
  94         struct completion       completion;
  95
  96         u32                     value;
  97         unsigned int            version;
  98 };
  99
 100 static const struct of_device_id exynos_adc_match[] = {
 101         { .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 },
 102         { .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 },
 103         {},
 104 };
 105 MODULE_DEVICE_TABLE(of, exynos_adc_match);
 106
 107 static inline unsigned int exynos_adc_get_version(struct platform_device *pdev)
 108 {
 109         const struct of_device_id *match;
 110
 111         match = of_match_node(exynos_adc_match, pdev->dev.of_node);
 112         return (unsigned int)match->data;
 113 }
 114
 115 static void exynos_adc_hw_init(struct exynos_adc *info)
 116 {
 117         u32 con1, con2;
 118
 119         if (info->version == ADC_V2) {
 120                 con1 = ADC_V2_CON1_SOFT_RESET;
 121                 writel(con1, ADC_V2_CON1(info->regs));
 122
 123                 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 124                         ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 125                 writel(con2, ADC_V2_CON2(info->regs));
 126
 127                 /* Enable interrupts */
 128                 writel(1, ADC_V2_INT_EN(info->regs));
 129         } else {
 130                 /* set default prescaler values and Enable prescaler */
 131                 con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 132
 133                 /* Enable 12-bit ADC resolution */
 134                 con1 |= ADC_V1_CON_RES;
 135                 writel(con1, ADC_V1_CON(info->regs));
 136         }
 137 }
 138
 139 static int exynos_read_raw(struct iio_dev *indio_dev,
 140                                 struct iio_chan_spec const *chan,
 141                                 int *val,
 142                                 int *val2,
 143                                 long mask)
 144 {
 145         struct exynos_adc *info = iio_priv(indio_dev);
 146         unsigned long timeout;
 147         u32 con1, con2;
 148         int ret;
 149
 150         if (mask != IIO_CHAN_INFO_RAW)
 151                 return -EINVAL;
 152
 153         mutex_lock(&indio_dev->mlock);
 154
 155         /* Select the channel to be used and Trigger conversion */
 156         if (info->version == ADC_V2) {
 157                 con2 = readl(ADC_V2_CON2(info->regs));
 158                 con2 &= ~ADC_V2_CON2_ACH_MASK;
 159                 con2 |= ADC_V2_CON2_ACH_SEL(chan->address);
 160                 writel(con2, ADC_V2_CON2(info->regs));
 161
 162                 con1 = readl(ADC_V2_CON1(info->regs));
 163                 writel(con1 | ADC_CON_EN_START,
 164                                 ADC_V2_CON1(info->regs));
 165         } else {
 166                 writel(chan->address, ADC_V1_MUX(info->regs));
 167
 168                 con1 = readl(ADC_V1_CON(info->regs));
 169                 writel(con1 | ADC_CON_EN_START,
 170                                 ADC_V1_CON(info->regs));
 171         }
 172
 173         timeout = wait_for_completion_timeout
 174                         (&info->completion, EXYNOS_ADC_TIMEOUT);
 175         if (timeout == 0) {
 176                 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
 177                 exynos_adc_hw_init(info);
 178                 ret = -ETIMEDOUT;
 179         } else {
 180                 *val = info->value;
 181                 *val2 = 0;
 182                 ret = IIO_VAL_INT;
 183         }
 184
 185         mutex_unlock(&indio_dev->mlock);
 186
 187         return ret;
 188 }
 189
 190 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
 191 {
 192         struct exynos_adc *info = (struct exynos_adc *)dev_id;
 193
 194         /* Read value */
 195         info->value = readl(ADC_V1_DATX(info->regs)) &
 196                                                 ADC_DATX_MASK;
 197         /* clear irq */
 198         if (info->version == ADC_V2)
 199                 writel(1, ADC_V2_INT_ST(info->regs));
 200         else
 201                 writel(1, ADC_V1_INTCLR(info->regs));
 202
 203         complete(&info->completion);
 204
 205         return IRQ_HANDLED;
 206 }
 207
 208 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
 209                               unsigned reg, unsigned writeval,
 210                               unsigned *readval)
 211 {
 212         struct exynos_adc *info = iio_priv(indio_dev);
 213
 214         if (readval == NULL)
 215                 return -EINVAL;
 216
 217         *readval = readl(info->regs + reg);
 218
 219         return 0;
 220 }
 221
 222 static const struct iio_info exynos_adc_iio_info = {
 223         .read_raw = &exynos_read_raw,
 224         .debugfs_reg_access = &exynos_adc_reg_access,
 225         .driver_module = THIS_MODULE,
 226 };
 227
 228 #define ADC_CHANNEL(_index, _id) {                      \
 229         .type = IIO_VOLTAGE,                            \
 230         .indexed = 1,                                   \
 231         .channel = _index,                              \
 232         .address = _index,                              \
 233         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
 234         .datasheet_name = _id,                          \
 235 }
 236
 237 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
 238         ADC_CHANNEL(0, "adc0"),
 239         ADC_CHANNEL(1, "adc1"),
 240         ADC_CHANNEL(2, "adc2"),
 241         ADC_CHANNEL(3, "adc3"),
 242         ADC_CHANNEL(4, "adc4"),
 243         ADC_CHANNEL(5, "adc5"),
 244         ADC_CHANNEL(6, "adc6"),
 245         ADC_CHANNEL(7, "adc7"),
 246         ADC_CHANNEL(8, "adc8"),
 247         ADC_CHANNEL(9, "adc9"),
 248 };
 249
 250 static int exynos_adc_remove_devices(struct device *dev, void *c)
 251 {
 252         struct platform_device *pdev = to_platform_device(dev);
 253
 254         platform_device_unregister(pdev);
 255
 256         return 0;
 257 }
 258
 259 static int exynos_adc_probe(struct platform_device *pdev)
 260 {
 261         struct exynos_adc *info = NULL;
 262         struct device_node *np = pdev->dev.of_node;
 263         struct iio_dev *indio_dev = NULL;
 264         struct resource *mem;
 265         int ret = -ENODEV;
 266         int irq;
 267
 268         if (!np)
 269                 return ret;
 270
 271         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
 272         if (!indio_dev) {
 273                 dev_err(&pdev->dev, "failed allocating iio device\n");
 274                 return -ENOMEM;
 275         }
 276
 277         info = iio_priv(indio_dev);
 278
 279         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 280         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 281         if (IS_ERR(info->regs))
 282                 return PTR_ERR(info->regs);
 283
 284         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 285         info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
 286         if (IS_ERR(info->enable_reg))
 287                 return PTR_ERR(info->enable_reg);
 288
 289         irq = platform_get_irq(pdev, 0);
 290         if (irq < 0) {
 291                 dev_err(&pdev->dev, "no irq resource?\n");
 292                 return irq;
 293         }
 294
 295         info->irq = irq;
 296
 297         init_completion(&info->completion);
 298
 299         info->clk = devm_clk_get(&pdev->dev, "adc");
 300         if (IS_ERR(info->clk)) {
 301                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 302                                                         PTR_ERR(info->clk));
 303                 return PTR_ERR(info->clk);
 304         }
 305
 306         info->vdd = devm_regulator_get(&pdev->dev, "vdd");
 307         if (IS_ERR(info->vdd)) {
 308                 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
 309                                                         PTR_ERR(info->vdd));
 310                 return PTR_ERR(info->vdd);
 311         }
 312
 313         ret = regulator_enable(info->vdd);
 314         if (ret)
 315                 return ret;
 316
 317         ret = clk_prepare_enable(info->clk);
 318         if (ret)
 319                 goto err_disable_reg;
 320
 321         writel(1, info->enable_reg);
 322
 323         info->version = exynos_adc_get_version(pdev);
 324
 325         platform_set_drvdata(pdev, indio_dev);
 326
 327         indio_dev->name = dev_name(&pdev->dev);
 328         indio_dev->dev.parent = &pdev->dev;
 329         indio_dev->dev.of_node = pdev->dev.of_node;
 330         indio_dev->info = &exynos_adc_iio_info;
 331         indio_dev->modes = INDIO_DIRECT_MODE;
 332         indio_dev->channels = exynos_adc_iio_channels;
 333
 334         if (info->version == ADC_V1)
 335                 indio_dev->num_channels = MAX_ADC_V1_CHANNELS;
 336         else
 337                 indio_dev->num_channels = MAX_ADC_V2_CHANNELS;
 338
 339         ret = request_irq(info->irq, exynos_adc_isr,
 340                                         0, dev_name(&pdev->dev), info);
 341         if (ret < 0) {
 342                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
 343                                                         info->irq);
 344                 goto err_disable_clk;
 345         }
 346
 347         ret = iio_device_register(indio_dev);
 348         if (ret)
 349                 goto err_irq;
 350
 351         exynos_adc_hw_init(info);
 352
 353         ret = of_platform_populate(np, exynos_adc_match, NULL, &pdev->dev);
 354         if (ret < 0) {
 355                 dev_err(&pdev->dev, "failed adding child nodes\n");
 356                 goto err_of_populate;
 357         }
 358
 359         return 0;
 360
 361 err_of_populate:
 362         device_for_each_child(&pdev->dev, NULL,
 363                                 exynos_adc_remove_devices);
 364         iio_device_unregister(indio_dev);
 365 err_irq:
 366         free_irq(info->irq, info);
 367 err_disable_clk:
 368         writel(0, info->enable_reg);
 369         clk_disable_unprepare(info->clk);
 370 err_disable_reg:
 371         regulator_disable(info->vdd);
 372         return ret;
 373 }
 374
 375 static int exynos_adc_remove(struct platform_device *pdev)
 376 {
 377         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 378         struct exynos_adc *info = iio_priv(indio_dev);
 379
 380         device_for_each_child(&pdev->dev, NULL,
 381                                 exynos_adc_remove_devices);
 382         iio_device_unregister(indio_dev);
 383         free_irq(info->irq, info);
 384         writel(0, info->enable_reg);
 385         clk_disable_unprepare(info->clk);
 386         regulator_disable(info->vdd);
 387
 388         return 0;
 389 }
 390
 391 #ifdef CONFIG_PM_SLEEP
 392 static int exynos_adc_suspend(struct device *dev)
 393 {
 394         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 395         struct exynos_adc *info = iio_priv(indio_dev);
 396         u32 con;
 397
 398         if (info->version == ADC_V2) {
 399                 con = readl(ADC_V2_CON1(info->regs));
 400                 con &= ~ADC_CON_EN_START;
 401                 writel(con, ADC_V2_CON1(info->regs));
 402         } else {
 403                 con = readl(ADC_V1_CON(info->regs));
 404                 con |= ADC_V1_CON_STANDBY;
 405                 writel(con, ADC_V1_CON(info->regs));
 406         }
 407
 408         writel(0, info->enable_reg);
 409         clk_disable_unprepare(info->clk);
 410         regulator_disable(info->vdd);
 411
 412         return 0;
 413 }
 414
 415 static int exynos_adc_resume(struct device *dev)
 416 {
 417         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 418         struct exynos_adc *info = iio_priv(indio_dev);
 419         int ret;
 420
 421         ret = regulator_enable(info->vdd);
 422         if (ret)
 423                 return ret;
 424
 425         ret = clk_prepare_enable(info->clk);
 426         if (ret)
 427                 return ret;
 428
 429         writel(1, info->enable_reg);
 430         exynos_adc_hw_init(info);
 431
 432         return 0;
 433 }
 434 #endif
 435
 436 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
 437                         exynos_adc_suspend,
 438                         exynos_adc_resume);
 439
 440 static struct platform_driver exynos_adc_driver = {
 441         .probe          = exynos_adc_probe,
 442         .remove         = exynos_adc_remove,
 443         .driver         = {
 444                 .name   = "exynos-adc",
 445                 .owner  = THIS_MODULE,
 446                 .of_match_table = exynos_adc_match,
 447                 .pm     = &exynos_adc_pm_ops,
 448         },
 449 };
 450
 451 module_platform_driver(exynos_adc_driver);
 452
 453 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
 454 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
 455 MODULE_LICENSE("GPL v2");