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iio:max1363 remove some functions left after merge
[deliverable/linux.git] / drivers / iio / adc / max1363.c
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33 #include <linux/module.h>
34
35 #include <linux/iio/iio.h>
36 #include <linux/iio/sysfs.h>
37 #include <linux/iio/events.h>
38 #include <linux/iio/buffer.h>
39 #include <linux/iio/driver.h>
40 #include <linux/iio/kfifo_buf.h>
41 #include <linux/iio/trigger_consumer.h>
42 #include <linux/iio/triggered_buffer.h>
43
44 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
45
46 /* There is a fair bit more defined here than currently
47 * used, but the intention is to support everything these
48 * chips do in the long run */
49
50 /* see data sheets */
51 /* max1363 and max1236, max1237, max1238, max1239 */
52 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
53 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
54 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
55 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
56 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
57 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
58
59 /* think about including max11600 etc - more settings */
60 #define MAX1363_SETUP_EXT_CLOCK 0x08
61 #define MAX1363_SETUP_INT_CLOCK 0x00
62 #define MAX1363_SETUP_UNIPOLAR 0x00
63 #define MAX1363_SETUP_BIPOLAR 0x04
64 #define MAX1363_SETUP_RESET 0x00
65 #define MAX1363_SETUP_NORESET 0x02
66 /* max1363 only - though don't care on others.
67 * For now monitor modes are not implemented as the relevant
68 * line is not connected on my test board.
69 * The definitions are here as I intend to add this soon.
70 */
71 #define MAX1363_SETUP_MONITOR_SETUP 0x01
72
73 /* Specific to the max1363 */
74 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
75 #define MAX1363_MON_INT_ENABLE 0x01
76
77 /* defined for readability reasons */
78 /* All chips */
79 #define MAX1363_CONFIG_BYTE(a) ((a))
80
81 #define MAX1363_CONFIG_SE 0x01
82 #define MAX1363_CONFIG_DE 0x00
83 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
84 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
85 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
86 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
87 /* max123{6-9} only */
88 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
89
90 /* max1363 only - merely part of channel selects or don't care for others */
91 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
92
93 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
94
95 /* max1363 strictly 0x06 - but doesn't matter */
96 #define MAX1363_CHANNEL_SEL_MASK 0x1E
97 #define MAX1363_SCAN_MASK 0x60
98 #define MAX1363_SE_DE_MASK 0x01
99
100 #define MAX1363_MAX_CHANNELS 25
101 /**
102 * struct max1363_mode - scan mode information
103 * @conf: The corresponding value of the configuration register
104 * @modemask: Bit mask corresponding to channels enabled in this mode
105 */
106 struct max1363_mode {
107 int8_t conf;
108 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
109 };
110
111 /* This must be maintained along side the max1363_mode_table in max1363_core */
112 enum max1363_modes {
113 /* Single read of a single channel */
114 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
115 /* Differential single read */
116 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
117 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
118 /* Scan to channel and mid to channel where overlapping */
119 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
120 s6to7, s0to7, s6to8, s0to8, s6to9,
121 s0to9, s6to10, s0to10, s6to11, s0to11,
122 /* Differential scan to channel and mid to channel where overlapping */
123 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
124 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
125 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
126 d7m6to11m10, d1m0to11m10,
127 };
128
129 /**
130 * struct max1363_chip_info - chip specifc information
131 * @info: iio core function callbacks structure
132 * @channels: channel specification
133 * @num_channels: number of channels
134 * @mode_list: array of available scan modes
135 * @default_mode: the scan mode in which the chip starts up
136 * @int_vref_mv: the internal reference voltage
137 * @num_modes: number of modes
138 * @bits: accuracy of the adc in bits
139 */
140 struct max1363_chip_info {
141 const struct iio_info *info;
142 const struct iio_chan_spec *channels;
143 int num_channels;
144 const enum max1363_modes *mode_list;
145 enum max1363_modes default_mode;
146 u16 int_vref_mv;
147 u8 num_modes;
148 u8 bits;
149 };
150
151 /**
152 * struct max1363_state - driver instance specific data
153 * @client: i2c_client
154 * @setupbyte: cache of current device setup byte
155 * @configbyte: cache of current device config byte
156 * @chip_info: chip model specific constants, available modes, etc.
157 * @current_mode: the scan mode of this chip
158 * @requestedmask: a valid requested set of channels
159 * @reg: supply regulator
160 * @monitor_on: whether monitor mode is enabled
161 * @monitor_speed: parameter corresponding to device monitor speed setting
162 * @mask_high: bitmask for enabled high thresholds
163 * @mask_low: bitmask for enabled low thresholds
164 * @thresh_high: high threshold values
165 * @thresh_low: low threshold values
166 */
167 struct max1363_state {
168 struct i2c_client *client;
169 u8 setupbyte;
170 u8 configbyte;
171 const struct max1363_chip_info *chip_info;
172 const struct max1363_mode *current_mode;
173 u32 requestedmask;
174 struct regulator *reg;
175
176 /* Using monitor modes and buffer at the same time is
177 currently not supported */
178 bool monitor_on;
179 unsigned int monitor_speed:3;
180 u8 mask_high;
181 u8 mask_low;
182 /* 4x unipolar first then the fours bipolar ones */
183 s16 thresh_high[8];
184 s16 thresh_low[8];
185 };
186
187 #define MAX1363_MODE_SINGLE(_num, _mask) { \
188 .conf = MAX1363_CHANNEL_SEL(_num) \
189 | MAX1363_CONFIG_SCAN_SINGLE_1 \
190 | MAX1363_CONFIG_SE, \
191 .modemask[0] = _mask, \
192 }
193
194 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
195 .conf = MAX1363_CHANNEL_SEL(_num) \
196 | MAX1363_CONFIG_SCAN_TO_CS \
197 | MAX1363_CONFIG_SE, \
198 .modemask[0] = _mask, \
199 }
200
201 /* note not available for max1363 hence naming */
202 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
203 .conf = MAX1363_CHANNEL_SEL(_num) \
204 | MAX1236_SCAN_MID_TO_CHANNEL \
205 | MAX1363_CONFIG_SE, \
206 .modemask[0] = _mask \
207 }
208
209 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
210 .conf = MAX1363_CHANNEL_SEL(_nump) \
211 | MAX1363_CONFIG_SCAN_SINGLE_1 \
212 | MAX1363_CONFIG_DE, \
213 .modemask[0] = _mask \
214 }
215
216 /* Can't think how to automate naming so specify for now */
217 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
218 .conf = MAX1363_CHANNEL_SEL(_num) \
219 | MAX1363_CONFIG_SCAN_TO_CS \
220 | MAX1363_CONFIG_DE, \
221 .modemask[0] = _mask \
222 }
223
224 /* note only available for max1363 hence naming */
225 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
226 .conf = MAX1363_CHANNEL_SEL(_num) \
227 | MAX1236_SCAN_MID_TO_CHANNEL \
228 | MAX1363_CONFIG_SE, \
229 .modemask[0] = _mask \
230 }
231
232 static const struct max1363_mode max1363_mode_table[] = {
233 /* All of the single channel options first */
234 MAX1363_MODE_SINGLE(0, 1 << 0),
235 MAX1363_MODE_SINGLE(1, 1 << 1),
236 MAX1363_MODE_SINGLE(2, 1 << 2),
237 MAX1363_MODE_SINGLE(3, 1 << 3),
238 MAX1363_MODE_SINGLE(4, 1 << 4),
239 MAX1363_MODE_SINGLE(5, 1 << 5),
240 MAX1363_MODE_SINGLE(6, 1 << 6),
241 MAX1363_MODE_SINGLE(7, 1 << 7),
242 MAX1363_MODE_SINGLE(8, 1 << 8),
243 MAX1363_MODE_SINGLE(9, 1 << 9),
244 MAX1363_MODE_SINGLE(10, 1 << 10),
245 MAX1363_MODE_SINGLE(11, 1 << 11),
246
247 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
248 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
249 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
250 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
251 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
252 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
253 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
254 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
255 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
256 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
257 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
258 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
259
260 /* The multichannel scans next */
261 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
262 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
263 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
264 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
265 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
266 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
267 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
268 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
269 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
270 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
271 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
273 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
278
279 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
280 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
281 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
282 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
284 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
288 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
289 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
291 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
293 };
294
295 static const struct max1363_mode
296 *max1363_match_mode(const unsigned long *mask,
297 const struct max1363_chip_info *ci)
298 {
299 int i;
300 if (mask)
301 for (i = 0; i < ci->num_modes; i++)
302 if (bitmap_subset(mask,
303 max1363_mode_table[ci->mode_list[i]].
304 modemask,
305 MAX1363_MAX_CHANNELS))
306 return &max1363_mode_table[ci->mode_list[i]];
307 return NULL;
308 }
309
310 static int max1363_write_basic_config(struct i2c_client *client,
311 unsigned char d1,
312 unsigned char d2)
313 {
314 u8 tx_buf[2] = {d1, d2};
315
316 return i2c_master_send(client, tx_buf, 2);
317 }
318
319 static int max1363_set_scan_mode(struct max1363_state *st)
320 {
321 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
322 | MAX1363_SCAN_MASK
323 | MAX1363_SE_DE_MASK);
324 st->configbyte |= st->current_mode->conf;
325
326 return max1363_write_basic_config(st->client,
327 st->setupbyte,
328 st->configbyte);
329 }
330
331 static int max1363_read_single_chan(struct iio_dev *indio_dev,
332 struct iio_chan_spec const *chan,
333 int *val,
334 long m)
335 {
336 int ret = 0;
337 s32 data;
338 char rxbuf[2];
339 struct max1363_state *st = iio_priv(indio_dev);
340 struct i2c_client *client = st->client;
341
342 mutex_lock(&indio_dev->mlock);
343 /*
344 * If monitor mode is enabled, the method for reading a single
345 * channel will have to be rather different and has not yet
346 * been implemented.
347 *
348 * Also, cannot read directly if buffered capture enabled.
349 */
350 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
351 ret = -EBUSY;
352 goto error_ret;
353 }
354
355 /* Check to see if current scan mode is correct */
356 if (st->current_mode != &max1363_mode_table[chan->address]) {
357 /* Update scan mode if needed */
358 st->current_mode = &max1363_mode_table[chan->address];
359 ret = max1363_set_scan_mode(st);
360 if (ret < 0)
361 goto error_ret;
362 }
363 if (st->chip_info->bits != 8) {
364 /* Get reading */
365 data = i2c_master_recv(client, rxbuf, 2);
366 if (data < 0) {
367 ret = data;
368 goto error_ret;
369 }
370 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
371 } else {
372 /* Get reading */
373 data = i2c_master_recv(client, rxbuf, 1);
374 if (data < 0) {
375 ret = data;
376 goto error_ret;
377 }
378 data = rxbuf[0];
379 }
380 *val = data;
381 error_ret:
382 mutex_unlock(&indio_dev->mlock);
383 return ret;
384
385 }
386
387 static int max1363_read_raw(struct iio_dev *indio_dev,
388 struct iio_chan_spec const *chan,
389 int *val,
390 int *val2,
391 long m)
392 {
393 struct max1363_state *st = iio_priv(indio_dev);
394 int ret;
395 switch (m) {
396 case IIO_CHAN_INFO_RAW:
397 ret = max1363_read_single_chan(indio_dev, chan, val, m);
398 if (ret < 0)
399 return ret;
400 return IIO_VAL_INT;
401 case IIO_CHAN_INFO_SCALE:
402 if ((1 << (st->chip_info->bits + 1)) >
403 st->chip_info->int_vref_mv) {
404 *val = 0;
405 *val2 = 500000;
406 return IIO_VAL_INT_PLUS_MICRO;
407 } else {
408 *val = (st->chip_info->int_vref_mv)
409 >> st->chip_info->bits;
410 return IIO_VAL_INT;
411 }
412 default:
413 return -EINVAL;
414 }
415 return 0;
416 }
417
418 /* Applies to max1363 */
419 static const enum max1363_modes max1363_mode_list[] = {
420 _s0, _s1, _s2, _s3,
421 s0to1, s0to2, s0to3,
422 d0m1, d2m3, d1m0, d3m2,
423 d0m1to2m3, d1m0to3m2,
424 };
425
426 #define MAX1363_EV_M \
427 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
428 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
429 #define MAX1363_INFO_MASK (IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
430 IIO_CHAN_INFO_SCALE_SHARED_BIT)
431 #define MAX1363_CHAN_U(num, addr, si, bits, evmask) \
432 { \
433 .type = IIO_VOLTAGE, \
434 .indexed = 1, \
435 .channel = num, \
436 .address = addr, \
437 .info_mask = MAX1363_INFO_MASK, \
438 .datasheet_name = "AIN"#num, \
439 .scan_type = { \
440 .sign = 'u', \
441 .realbits = bits, \
442 .storagebits = (bits > 8) ? 16 : 8, \
443 .endianness = IIO_BE, \
444 }, \
445 .scan_index = si, \
446 .event_mask = evmask, \
447 }
448
449 /* bipolar channel */
450 #define MAX1363_CHAN_B(num, num2, addr, si, bits, evmask) \
451 { \
452 .type = IIO_VOLTAGE, \
453 .differential = 1, \
454 .indexed = 1, \
455 .channel = num, \
456 .channel2 = num2, \
457 .address = addr, \
458 .info_mask = MAX1363_INFO_MASK, \
459 .datasheet_name = "AIN"#num"-AIN"#num2, \
460 .scan_type = { \
461 .sign = 's', \
462 .realbits = bits, \
463 .storagebits = (bits > 8) ? 16 : 8, \
464 .endianness = IIO_BE, \
465 }, \
466 .scan_index = si, \
467 .event_mask = evmask, \
468 }
469
470 #define MAX1363_4X_CHANS(bits, em) { \
471 MAX1363_CHAN_U(0, _s0, 0, bits, em), \
472 MAX1363_CHAN_U(1, _s1, 1, bits, em), \
473 MAX1363_CHAN_U(2, _s2, 2, bits, em), \
474 MAX1363_CHAN_U(3, _s3, 3, bits, em), \
475 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, em), \
476 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, em), \
477 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, em), \
478 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, em), \
479 IIO_CHAN_SOFT_TIMESTAMP(8) \
480 }
481
482 static const struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8, 0);
483 static const struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10, 0);
484 static const struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12, 0);
485 static const struct iio_chan_spec max1361_channels[] =
486 MAX1363_4X_CHANS(10, MAX1363_EV_M);
487 static const struct iio_chan_spec max1363_channels[] =
488 MAX1363_4X_CHANS(12, MAX1363_EV_M);
489
490 /* Applies to max1236, max1237 */
491 static const enum max1363_modes max1236_mode_list[] = {
492 _s0, _s1, _s2, _s3,
493 s0to1, s0to2, s0to3,
494 d0m1, d2m3, d1m0, d3m2,
495 d0m1to2m3, d1m0to3m2,
496 s2to3,
497 };
498
499 /* Applies to max1238, max1239 */
500 static const enum max1363_modes max1238_mode_list[] = {
501 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
502 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
503 s0to7, s0to8, s0to9, s0to10, s0to11,
504 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
505 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
506 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
507 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
508 s6to7, s6to8, s6to9, s6to10, s6to11,
509 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
510 };
511
512 #define MAX1363_12X_CHANS(bits) { \
513 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
514 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
515 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
516 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
517 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
518 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
519 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
520 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
521 MAX1363_CHAN_U(8, _s8, 8, bits, 0), \
522 MAX1363_CHAN_U(9, _s9, 9, bits, 0), \
523 MAX1363_CHAN_U(10, _s10, 10, bits, 0), \
524 MAX1363_CHAN_U(11, _s11, 11, bits, 0), \
525 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, 0), \
526 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, 0), \
527 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, 0), \
528 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, 0), \
529 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, 0), \
530 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, 0), \
531 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, 0), \
532 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, 0), \
533 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, 0), \
534 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, 0), \
535 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, 0), \
536 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, 0), \
537 IIO_CHAN_SOFT_TIMESTAMP(24) \
538 }
539 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
540 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
541 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
542
543 static const enum max1363_modes max11607_mode_list[] = {
544 _s0, _s1, _s2, _s3,
545 s0to1, s0to2, s0to3,
546 s2to3,
547 d0m1, d2m3, d1m0, d3m2,
548 d0m1to2m3, d1m0to3m2,
549 };
550
551 static const enum max1363_modes max11608_mode_list[] = {
552 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
553 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
554 s6to7,
555 d0m1, d2m3, d4m5, d6m7,
556 d1m0, d3m2, d5m4, d7m6,
557 d0m1to2m3, d0m1to4m5, d0m1to6m7,
558 d1m0to3m2, d1m0to5m4, d1m0to7m6,
559 };
560
561 #define MAX1363_8X_CHANS(bits) { \
562 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
563 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
564 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
565 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
566 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
567 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
568 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
569 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
570 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, 0), \
571 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, 0), \
572 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, 0), \
573 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, 0), \
574 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, 0), \
575 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, 0), \
576 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, 0), \
577 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, 0), \
578 IIO_CHAN_SOFT_TIMESTAMP(16) \
579 }
580 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
581 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
582 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
583
584 static const enum max1363_modes max11644_mode_list[] = {
585 _s0, _s1, s0to1, d0m1, d1m0,
586 };
587
588 #define MAX1363_2X_CHANS(bits) { \
589 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
590 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
591 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, 0), \
592 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, 0), \
593 IIO_CHAN_SOFT_TIMESTAMP(4) \
594 }
595
596 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
597 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
598
599 enum { max1361,
600 max1362,
601 max1363,
602 max1364,
603 max1036,
604 max1037,
605 max1038,
606 max1039,
607 max1136,
608 max1137,
609 max1138,
610 max1139,
611 max1236,
612 max1237,
613 max1238,
614 max1239,
615 max11600,
616 max11601,
617 max11602,
618 max11603,
619 max11604,
620 max11605,
621 max11606,
622 max11607,
623 max11608,
624 max11609,
625 max11610,
626 max11611,
627 max11612,
628 max11613,
629 max11614,
630 max11615,
631 max11616,
632 max11617,
633 max11644,
634 max11645,
635 max11646,
636 max11647
637 };
638
639 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
640 8300, 4200, 2000, 1000 };
641
642 static ssize_t max1363_monitor_show_freq(struct device *dev,
643 struct device_attribute *attr,
644 char *buf)
645 {
646 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
647 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
648 }
649
650 static ssize_t max1363_monitor_store_freq(struct device *dev,
651 struct device_attribute *attr,
652 const char *buf,
653 size_t len)
654 {
655 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
656 struct max1363_state *st = iio_priv(indio_dev);
657 int i, ret;
658 unsigned long val;
659 bool found = false;
660
661 ret = strict_strtoul(buf, 10, &val);
662 if (ret)
663 return -EINVAL;
664 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
665 if (val == max1363_monitor_speeds[i]) {
666 found = true;
667 break;
668 }
669 if (!found)
670 return -EINVAL;
671
672 mutex_lock(&indio_dev->mlock);
673 st->monitor_speed = i;
674 mutex_unlock(&indio_dev->mlock);
675
676 return 0;
677 }
678
679 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
680 max1363_monitor_show_freq,
681 max1363_monitor_store_freq);
682
683 static IIO_CONST_ATTR(sampling_frequency_available,
684 "133000 665000 33300 16600 8300 4200 2000 1000");
685
686 static int max1363_read_thresh(struct iio_dev *indio_dev,
687 u64 event_code,
688 int *val)
689 {
690 struct max1363_state *st = iio_priv(indio_dev);
691 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
692 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
693 else
694 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)];
695 return 0;
696 }
697
698 static int max1363_write_thresh(struct iio_dev *indio_dev,
699 u64 event_code,
700 int val)
701 {
702 struct max1363_state *st = iio_priv(indio_dev);
703 /* make it handle signed correctly as well */
704 switch (st->chip_info->bits) {
705 case 10:
706 if (val > 0x3FF)
707 return -EINVAL;
708 break;
709 case 12:
710 if (val > 0xFFF)
711 return -EINVAL;
712 break;
713 }
714
715 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
716 case IIO_EV_DIR_FALLING:
717 st->thresh_low[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
718 break;
719 case IIO_EV_DIR_RISING:
720 st->thresh_high[IIO_EVENT_CODE_EXTRACT_CHAN(event_code)] = val;
721 break;
722 }
723
724 return 0;
725 }
726
727 static const u64 max1363_event_codes[] = {
728 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
729 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
730 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
731 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
732 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
733 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
734 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
735 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
736 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
737 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
738 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
739 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
740 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
741 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
742 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
743 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
744 };
745
746 static irqreturn_t max1363_event_handler(int irq, void *private)
747 {
748 struct iio_dev *indio_dev = private;
749 struct max1363_state *st = iio_priv(indio_dev);
750 s64 timestamp = iio_get_time_ns();
751 unsigned long mask, loc;
752 u8 rx;
753 u8 tx[2] = { st->setupbyte,
754 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
755
756 i2c_master_recv(st->client, &rx, 1);
757 mask = rx;
758 for_each_set_bit(loc, &mask, 8)
759 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
760 i2c_master_send(st->client, tx, 2);
761
762 return IRQ_HANDLED;
763 }
764
765 static int max1363_read_event_config(struct iio_dev *indio_dev,
766 u64 event_code)
767 {
768 struct max1363_state *st = iio_priv(indio_dev);
769 int val;
770 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
771
772 mutex_lock(&indio_dev->mlock);
773 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
774 val = (1 << number) & st->mask_low;
775 else
776 val = (1 << number) & st->mask_high;
777 mutex_unlock(&indio_dev->mlock);
778
779 return val;
780 }
781
782 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
783 {
784 u8 *tx_buf;
785 int ret, i = 3, j;
786 unsigned long numelements;
787 int len;
788 const long *modemask;
789
790 if (!enabled) {
791 /* transition to buffered capture is not currently supported */
792 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
793 st->configbyte &= ~MAX1363_SCAN_MASK;
794 st->monitor_on = false;
795 return max1363_write_basic_config(st->client,
796 st->setupbyte,
797 st->configbyte);
798 }
799
800 /* Ensure we are in the relevant mode */
801 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
802 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
803 | MAX1363_SCAN_MASK
804 | MAX1363_SE_DE_MASK);
805 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
806 if ((st->mask_low | st->mask_high) & 0x0F) {
807 st->configbyte |= max1363_mode_table[s0to3].conf;
808 modemask = max1363_mode_table[s0to3].modemask;
809 } else if ((st->mask_low | st->mask_high) & 0x30) {
810 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
811 modemask = max1363_mode_table[d0m1to2m3].modemask;
812 } else {
813 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
814 modemask = max1363_mode_table[d1m0to3m2].modemask;
815 }
816 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
817 len = 3 * numelements + 3;
818 tx_buf = kmalloc(len, GFP_KERNEL);
819 if (!tx_buf) {
820 ret = -ENOMEM;
821 goto error_ret;
822 }
823 tx_buf[0] = st->configbyte;
824 tx_buf[1] = st->setupbyte;
825 tx_buf[2] = (st->monitor_speed << 1);
826
827 /*
828 * So we need to do yet another bit of nefarious scan mode
829 * setup to match what we need.
830 */
831 for (j = 0; j < 8; j++)
832 if (test_bit(j, modemask)) {
833 /* Establish the mode is in the scan */
834 if (st->mask_low & (1 << j)) {
835 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
836 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
837 } else if (j < 4) {
838 tx_buf[i] = 0;
839 tx_buf[i + 1] = 0;
840 } else {
841 tx_buf[i] = 0x80;
842 tx_buf[i + 1] = 0;
843 }
844 if (st->mask_high & (1 << j)) {
845 tx_buf[i + 1] |=
846 (st->thresh_high[j] >> 8) & 0x0F;
847 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
848 } else if (j < 4) {
849 tx_buf[i + 1] |= 0x0F;
850 tx_buf[i + 2] = 0xFF;
851 } else {
852 tx_buf[i + 1] |= 0x07;
853 tx_buf[i + 2] = 0xFF;
854 }
855 i += 3;
856 }
857
858
859 ret = i2c_master_send(st->client, tx_buf, len);
860 if (ret < 0)
861 goto error_ret;
862 if (ret != len) {
863 ret = -EIO;
864 goto error_ret;
865 }
866
867 /*
868 * Now that we hopefully have sensible thresholds in place it is
869 * time to turn the interrupts on.
870 * It is unclear from the data sheet if this should be necessary
871 * (i.e. whether monitor mode setup is atomic) but it appears to
872 * be in practice.
873 */
874 tx_buf[0] = st->setupbyte;
875 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
876 ret = i2c_master_send(st->client, tx_buf, 2);
877 if (ret < 0)
878 goto error_ret;
879 if (ret != 2) {
880 ret = -EIO;
881 goto error_ret;
882 }
883 ret = 0;
884 st->monitor_on = true;
885 error_ret:
886
887 kfree(tx_buf);
888
889 return ret;
890 }
891
892 /*
893 * To keep this manageable we always use one of 3 scan modes.
894 * Scan 0...3, 0-1,2-3 and 1-0,3-2
895 */
896
897 static inline int __max1363_check_event_mask(int thismask, int checkmask)
898 {
899 int ret = 0;
900 /* Is it unipolar */
901 if (thismask < 4) {
902 if (checkmask & ~0x0F) {
903 ret = -EBUSY;
904 goto error_ret;
905 }
906 } else if (thismask < 6) {
907 if (checkmask & ~0x30) {
908 ret = -EBUSY;
909 goto error_ret;
910 }
911 } else if (checkmask & ~0xC0)
912 ret = -EBUSY;
913 error_ret:
914 return ret;
915 }
916
917 static int max1363_write_event_config(struct iio_dev *indio_dev,
918 u64 event_code,
919 int state)
920 {
921 int ret = 0;
922 struct max1363_state *st = iio_priv(indio_dev);
923 u16 unifiedmask;
924 int number = IIO_EVENT_CODE_EXTRACT_CHAN(event_code);
925
926 mutex_lock(&indio_dev->mlock);
927 unifiedmask = st->mask_low | st->mask_high;
928 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
929
930 if (state == 0)
931 st->mask_low &= ~(1 << number);
932 else {
933 ret = __max1363_check_event_mask((1 << number),
934 unifiedmask);
935 if (ret)
936 goto error_ret;
937 st->mask_low |= (1 << number);
938 }
939 } else {
940 if (state == 0)
941 st->mask_high &= ~(1 << number);
942 else {
943 ret = __max1363_check_event_mask((1 << number),
944 unifiedmask);
945 if (ret)
946 goto error_ret;
947 st->mask_high |= (1 << number);
948 }
949 }
950
951 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
952 error_ret:
953 mutex_unlock(&indio_dev->mlock);
954
955 return ret;
956 }
957
958 /*
959 * As with scan_elements, only certain sets of these can
960 * be combined.
961 */
962 static struct attribute *max1363_event_attributes[] = {
963 &iio_dev_attr_sampling_frequency.dev_attr.attr,
964 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
965 NULL,
966 };
967
968 static struct attribute_group max1363_event_attribute_group = {
969 .attrs = max1363_event_attributes,
970 .name = "events",
971 };
972
973 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
974 const unsigned long *scan_mask)
975 {
976 struct max1363_state *st = iio_priv(indio_dev);
977
978 /*
979 * Need to figure out the current mode based upon the requested
980 * scan mask in iio_dev
981 */
982 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
983 if (!st->current_mode)
984 return -EINVAL;
985 max1363_set_scan_mode(st);
986 return 0;
987 }
988
989 static const struct iio_info max1238_info = {
990 .read_raw = &max1363_read_raw,
991 .driver_module = THIS_MODULE,
992 .update_scan_mode = &max1363_update_scan_mode,
993 };
994
995 static const struct iio_info max1363_info = {
996 .read_event_value = &max1363_read_thresh,
997 .write_event_value = &max1363_write_thresh,
998 .read_event_config = &max1363_read_event_config,
999 .write_event_config = &max1363_write_event_config,
1000 .read_raw = &max1363_read_raw,
1001 .update_scan_mode = &max1363_update_scan_mode,
1002 .driver_module = THIS_MODULE,
1003 .event_attrs = &max1363_event_attribute_group,
1004 };
1005
1006 /* max1363 and max1368 tested - rest from data sheet */
1007 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1008 [max1361] = {
1009 .bits = 10,
1010 .int_vref_mv = 2048,
1011 .mode_list = max1363_mode_list,
1012 .num_modes = ARRAY_SIZE(max1363_mode_list),
1013 .default_mode = s0to3,
1014 .channels = max1361_channels,
1015 .num_channels = ARRAY_SIZE(max1361_channels),
1016 .info = &max1363_info,
1017 },
1018 [max1362] = {
1019 .bits = 10,
1020 .int_vref_mv = 4096,
1021 .mode_list = max1363_mode_list,
1022 .num_modes = ARRAY_SIZE(max1363_mode_list),
1023 .default_mode = s0to3,
1024 .channels = max1361_channels,
1025 .num_channels = ARRAY_SIZE(max1361_channels),
1026 .info = &max1363_info,
1027 },
1028 [max1363] = {
1029 .bits = 12,
1030 .int_vref_mv = 2048,
1031 .mode_list = max1363_mode_list,
1032 .num_modes = ARRAY_SIZE(max1363_mode_list),
1033 .default_mode = s0to3,
1034 .channels = max1363_channels,
1035 .num_channels = ARRAY_SIZE(max1363_channels),
1036 .info = &max1363_info,
1037 },
1038 [max1364] = {
1039 .bits = 12,
1040 .int_vref_mv = 4096,
1041 .mode_list = max1363_mode_list,
1042 .num_modes = ARRAY_SIZE(max1363_mode_list),
1043 .default_mode = s0to3,
1044 .channels = max1363_channels,
1045 .num_channels = ARRAY_SIZE(max1363_channels),
1046 .info = &max1363_info,
1047 },
1048 [max1036] = {
1049 .bits = 8,
1050 .int_vref_mv = 4096,
1051 .mode_list = max1236_mode_list,
1052 .num_modes = ARRAY_SIZE(max1236_mode_list),
1053 .default_mode = s0to3,
1054 .info = &max1238_info,
1055 .channels = max1036_channels,
1056 .num_channels = ARRAY_SIZE(max1036_channels),
1057 },
1058 [max1037] = {
1059 .bits = 8,
1060 .int_vref_mv = 2048,
1061 .mode_list = max1236_mode_list,
1062 .num_modes = ARRAY_SIZE(max1236_mode_list),
1063 .default_mode = s0to3,
1064 .info = &max1238_info,
1065 .channels = max1036_channels,
1066 .num_channels = ARRAY_SIZE(max1036_channels),
1067 },
1068 [max1038] = {
1069 .bits = 8,
1070 .int_vref_mv = 4096,
1071 .mode_list = max1238_mode_list,
1072 .num_modes = ARRAY_SIZE(max1238_mode_list),
1073 .default_mode = s0to11,
1074 .info = &max1238_info,
1075 .channels = max1038_channels,
1076 .num_channels = ARRAY_SIZE(max1038_channels),
1077 },
1078 [max1039] = {
1079 .bits = 8,
1080 .int_vref_mv = 2048,
1081 .mode_list = max1238_mode_list,
1082 .num_modes = ARRAY_SIZE(max1238_mode_list),
1083 .default_mode = s0to11,
1084 .info = &max1238_info,
1085 .channels = max1038_channels,
1086 .num_channels = ARRAY_SIZE(max1038_channels),
1087 },
1088 [max1136] = {
1089 .bits = 10,
1090 .int_vref_mv = 4096,
1091 .mode_list = max1236_mode_list,
1092 .num_modes = ARRAY_SIZE(max1236_mode_list),
1093 .default_mode = s0to3,
1094 .info = &max1238_info,
1095 .channels = max1136_channels,
1096 .num_channels = ARRAY_SIZE(max1136_channels),
1097 },
1098 [max1137] = {
1099 .bits = 10,
1100 .int_vref_mv = 2048,
1101 .mode_list = max1236_mode_list,
1102 .num_modes = ARRAY_SIZE(max1236_mode_list),
1103 .default_mode = s0to3,
1104 .info = &max1238_info,
1105 .channels = max1136_channels,
1106 .num_channels = ARRAY_SIZE(max1136_channels),
1107 },
1108 [max1138] = {
1109 .bits = 10,
1110 .int_vref_mv = 4096,
1111 .mode_list = max1238_mode_list,
1112 .num_modes = ARRAY_SIZE(max1238_mode_list),
1113 .default_mode = s0to11,
1114 .info = &max1238_info,
1115 .channels = max1138_channels,
1116 .num_channels = ARRAY_SIZE(max1138_channels),
1117 },
1118 [max1139] = {
1119 .bits = 10,
1120 .int_vref_mv = 2048,
1121 .mode_list = max1238_mode_list,
1122 .num_modes = ARRAY_SIZE(max1238_mode_list),
1123 .default_mode = s0to11,
1124 .info = &max1238_info,
1125 .channels = max1138_channels,
1126 .num_channels = ARRAY_SIZE(max1138_channels),
1127 },
1128 [max1236] = {
1129 .bits = 12,
1130 .int_vref_mv = 4096,
1131 .mode_list = max1236_mode_list,
1132 .num_modes = ARRAY_SIZE(max1236_mode_list),
1133 .default_mode = s0to3,
1134 .info = &max1238_info,
1135 .channels = max1236_channels,
1136 .num_channels = ARRAY_SIZE(max1236_channels),
1137 },
1138 [max1237] = {
1139 .bits = 12,
1140 .int_vref_mv = 2048,
1141 .mode_list = max1236_mode_list,
1142 .num_modes = ARRAY_SIZE(max1236_mode_list),
1143 .default_mode = s0to3,
1144 .info = &max1238_info,
1145 .channels = max1236_channels,
1146 .num_channels = ARRAY_SIZE(max1236_channels),
1147 },
1148 [max1238] = {
1149 .bits = 12,
1150 .int_vref_mv = 4096,
1151 .mode_list = max1238_mode_list,
1152 .num_modes = ARRAY_SIZE(max1238_mode_list),
1153 .default_mode = s0to11,
1154 .info = &max1238_info,
1155 .channels = max1238_channels,
1156 .num_channels = ARRAY_SIZE(max1238_channels),
1157 },
1158 [max1239] = {
1159 .bits = 12,
1160 .int_vref_mv = 2048,
1161 .mode_list = max1238_mode_list,
1162 .num_modes = ARRAY_SIZE(max1238_mode_list),
1163 .default_mode = s0to11,
1164 .info = &max1238_info,
1165 .channels = max1238_channels,
1166 .num_channels = ARRAY_SIZE(max1238_channels),
1167 },
1168 [max11600] = {
1169 .bits = 8,
1170 .int_vref_mv = 4096,
1171 .mode_list = max11607_mode_list,
1172 .num_modes = ARRAY_SIZE(max11607_mode_list),
1173 .default_mode = s0to3,
1174 .info = &max1238_info,
1175 .channels = max1036_channels,
1176 .num_channels = ARRAY_SIZE(max1036_channels),
1177 },
1178 [max11601] = {
1179 .bits = 8,
1180 .int_vref_mv = 2048,
1181 .mode_list = max11607_mode_list,
1182 .num_modes = ARRAY_SIZE(max11607_mode_list),
1183 .default_mode = s0to3,
1184 .info = &max1238_info,
1185 .channels = max1036_channels,
1186 .num_channels = ARRAY_SIZE(max1036_channels),
1187 },
1188 [max11602] = {
1189 .bits = 8,
1190 .int_vref_mv = 4096,
1191 .mode_list = max11608_mode_list,
1192 .num_modes = ARRAY_SIZE(max11608_mode_list),
1193 .default_mode = s0to7,
1194 .info = &max1238_info,
1195 .channels = max11602_channels,
1196 .num_channels = ARRAY_SIZE(max11602_channels),
1197 },
1198 [max11603] = {
1199 .bits = 8,
1200 .int_vref_mv = 2048,
1201 .mode_list = max11608_mode_list,
1202 .num_modes = ARRAY_SIZE(max11608_mode_list),
1203 .default_mode = s0to7,
1204 .info = &max1238_info,
1205 .channels = max11602_channels,
1206 .num_channels = ARRAY_SIZE(max11602_channels),
1207 },
1208 [max11604] = {
1209 .bits = 8,
1210 .int_vref_mv = 4098,
1211 .mode_list = max1238_mode_list,
1212 .num_modes = ARRAY_SIZE(max1238_mode_list),
1213 .default_mode = s0to11,
1214 .info = &max1238_info,
1215 .channels = max1238_channels,
1216 .num_channels = ARRAY_SIZE(max1238_channels),
1217 },
1218 [max11605] = {
1219 .bits = 8,
1220 .int_vref_mv = 2048,
1221 .mode_list = max1238_mode_list,
1222 .num_modes = ARRAY_SIZE(max1238_mode_list),
1223 .default_mode = s0to11,
1224 .info = &max1238_info,
1225 .channels = max1238_channels,
1226 .num_channels = ARRAY_SIZE(max1238_channels),
1227 },
1228 [max11606] = {
1229 .bits = 10,
1230 .int_vref_mv = 4096,
1231 .mode_list = max11607_mode_list,
1232 .num_modes = ARRAY_SIZE(max11607_mode_list),
1233 .default_mode = s0to3,
1234 .info = &max1238_info,
1235 .channels = max1136_channels,
1236 .num_channels = ARRAY_SIZE(max1136_channels),
1237 },
1238 [max11607] = {
1239 .bits = 10,
1240 .int_vref_mv = 2048,
1241 .mode_list = max11607_mode_list,
1242 .num_modes = ARRAY_SIZE(max11607_mode_list),
1243 .default_mode = s0to3,
1244 .info = &max1238_info,
1245 .channels = max1136_channels,
1246 .num_channels = ARRAY_SIZE(max1136_channels),
1247 },
1248 [max11608] = {
1249 .bits = 10,
1250 .int_vref_mv = 4096,
1251 .mode_list = max11608_mode_list,
1252 .num_modes = ARRAY_SIZE(max11608_mode_list),
1253 .default_mode = s0to7,
1254 .info = &max1238_info,
1255 .channels = max11608_channels,
1256 .num_channels = ARRAY_SIZE(max11608_channels),
1257 },
1258 [max11609] = {
1259 .bits = 10,
1260 .int_vref_mv = 2048,
1261 .mode_list = max11608_mode_list,
1262 .num_modes = ARRAY_SIZE(max11608_mode_list),
1263 .default_mode = s0to7,
1264 .info = &max1238_info,
1265 .channels = max11608_channels,
1266 .num_channels = ARRAY_SIZE(max11608_channels),
1267 },
1268 [max11610] = {
1269 .bits = 10,
1270 .int_vref_mv = 4098,
1271 .mode_list = max1238_mode_list,
1272 .num_modes = ARRAY_SIZE(max1238_mode_list),
1273 .default_mode = s0to11,
1274 .info = &max1238_info,
1275 .channels = max1238_channels,
1276 .num_channels = ARRAY_SIZE(max1238_channels),
1277 },
1278 [max11611] = {
1279 .bits = 10,
1280 .int_vref_mv = 2048,
1281 .mode_list = max1238_mode_list,
1282 .num_modes = ARRAY_SIZE(max1238_mode_list),
1283 .default_mode = s0to11,
1284 .info = &max1238_info,
1285 .channels = max1238_channels,
1286 .num_channels = ARRAY_SIZE(max1238_channels),
1287 },
1288 [max11612] = {
1289 .bits = 12,
1290 .int_vref_mv = 4096,
1291 .mode_list = max11607_mode_list,
1292 .num_modes = ARRAY_SIZE(max11607_mode_list),
1293 .default_mode = s0to3,
1294 .info = &max1238_info,
1295 .channels = max1363_channels,
1296 .num_channels = ARRAY_SIZE(max1363_channels),
1297 },
1298 [max11613] = {
1299 .bits = 12,
1300 .int_vref_mv = 2048,
1301 .mode_list = max11607_mode_list,
1302 .num_modes = ARRAY_SIZE(max11607_mode_list),
1303 .default_mode = s0to3,
1304 .info = &max1238_info,
1305 .channels = max1363_channels,
1306 .num_channels = ARRAY_SIZE(max1363_channels),
1307 },
1308 [max11614] = {
1309 .bits = 12,
1310 .int_vref_mv = 4096,
1311 .mode_list = max11608_mode_list,
1312 .num_modes = ARRAY_SIZE(max11608_mode_list),
1313 .default_mode = s0to7,
1314 .info = &max1238_info,
1315 .channels = max11614_channels,
1316 .num_channels = ARRAY_SIZE(max11614_channels),
1317 },
1318 [max11615] = {
1319 .bits = 12,
1320 .int_vref_mv = 2048,
1321 .mode_list = max11608_mode_list,
1322 .num_modes = ARRAY_SIZE(max11608_mode_list),
1323 .default_mode = s0to7,
1324 .info = &max1238_info,
1325 .channels = max11614_channels,
1326 .num_channels = ARRAY_SIZE(max11614_channels),
1327 },
1328 [max11616] = {
1329 .bits = 12,
1330 .int_vref_mv = 4098,
1331 .mode_list = max1238_mode_list,
1332 .num_modes = ARRAY_SIZE(max1238_mode_list),
1333 .default_mode = s0to11,
1334 .info = &max1238_info,
1335 .channels = max1238_channels,
1336 .num_channels = ARRAY_SIZE(max1238_channels),
1337 },
1338 [max11617] = {
1339 .bits = 12,
1340 .int_vref_mv = 2048,
1341 .mode_list = max1238_mode_list,
1342 .num_modes = ARRAY_SIZE(max1238_mode_list),
1343 .default_mode = s0to11,
1344 .info = &max1238_info,
1345 .channels = max1238_channels,
1346 .num_channels = ARRAY_SIZE(max1238_channels),
1347 },
1348 [max11644] = {
1349 .bits = 12,
1350 .int_vref_mv = 2048,
1351 .mode_list = max11644_mode_list,
1352 .num_modes = ARRAY_SIZE(max11644_mode_list),
1353 .default_mode = s0to1,
1354 .info = &max1238_info,
1355 .channels = max11644_channels,
1356 .num_channels = ARRAY_SIZE(max11644_channels),
1357 },
1358 [max11645] = {
1359 .bits = 12,
1360 .int_vref_mv = 4096,
1361 .mode_list = max11644_mode_list,
1362 .num_modes = ARRAY_SIZE(max11644_mode_list),
1363 .default_mode = s0to1,
1364 .info = &max1238_info,
1365 .channels = max11644_channels,
1366 .num_channels = ARRAY_SIZE(max11644_channels),
1367 },
1368 [max11646] = {
1369 .bits = 10,
1370 .int_vref_mv = 2048,
1371 .mode_list = max11644_mode_list,
1372 .num_modes = ARRAY_SIZE(max11644_mode_list),
1373 .default_mode = s0to1,
1374 .info = &max1238_info,
1375 .channels = max11646_channels,
1376 .num_channels = ARRAY_SIZE(max11646_channels),
1377 },
1378 [max11647] = {
1379 .bits = 10,
1380 .int_vref_mv = 4096,
1381 .mode_list = max11644_mode_list,
1382 .num_modes = ARRAY_SIZE(max11644_mode_list),
1383 .default_mode = s0to1,
1384 .info = &max1238_info,
1385 .channels = max11646_channels,
1386 .num_channels = ARRAY_SIZE(max11646_channels),
1387 },
1388 };
1389
1390 static int max1363_initial_setup(struct max1363_state *st)
1391 {
1392 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1393 | MAX1363_SETUP_POWER_UP_INT_REF
1394 | MAX1363_SETUP_INT_CLOCK
1395 | MAX1363_SETUP_UNIPOLAR
1396 | MAX1363_SETUP_NORESET;
1397
1398 /* Set scan mode writes the config anyway so wait until then */
1399 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1400 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1401 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1402
1403 return max1363_set_scan_mode(st);
1404 }
1405
1406 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1407 {
1408 struct max1363_state *st = iio_priv(indio_dev);
1409 unsigned long *masks;
1410 int i;
1411
1412 masks = kzalloc(BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*sizeof(long)*
1413 (st->chip_info->num_modes + 1), GFP_KERNEL);
1414 if (!masks)
1415 return -ENOMEM;
1416
1417 for (i = 0; i < st->chip_info->num_modes; i++)
1418 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1419 max1363_mode_table[st->chip_info->mode_list[i]]
1420 .modemask, MAX1363_MAX_CHANNELS);
1421
1422 indio_dev->available_scan_masks = masks;
1423
1424 return 0;
1425 }
1426
1427 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1428 {
1429 struct iio_poll_func *pf = p;
1430 struct iio_dev *indio_dev = pf->indio_dev;
1431 struct max1363_state *st = iio_priv(indio_dev);
1432 s64 time_ns;
1433 __u8 *rxbuf;
1434 int b_sent;
1435 size_t d_size;
1436 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1437 MAX1363_MAX_CHANNELS);
1438
1439 /* Ensure the timestamp is 8 byte aligned */
1440 if (st->chip_info->bits != 8)
1441 d_size = numvals*2;
1442 else
1443 d_size = numvals;
1444 if (indio_dev->scan_timestamp) {
1445 d_size += sizeof(s64);
1446 if (d_size % sizeof(s64))
1447 d_size += sizeof(s64) - (d_size % sizeof(s64));
1448 }
1449 /* Monitor mode prevents reading. Whilst not currently implemented
1450 * might as well have this test in here in the meantime as it does
1451 * no harm.
1452 */
1453 if (numvals == 0)
1454 goto done;
1455
1456 rxbuf = kmalloc(d_size, GFP_KERNEL);
1457 if (rxbuf == NULL)
1458 goto done;
1459 if (st->chip_info->bits != 8)
1460 b_sent = i2c_master_recv(st->client, rxbuf, numvals*2);
1461 else
1462 b_sent = i2c_master_recv(st->client, rxbuf, numvals);
1463 if (b_sent < 0)
1464 goto done_free;
1465
1466 time_ns = iio_get_time_ns();
1467
1468 if (indio_dev->scan_timestamp)
1469 memcpy(rxbuf + d_size - sizeof(s64), &time_ns, sizeof(time_ns));
1470 iio_push_to_buffers(indio_dev, rxbuf);
1471
1472 done_free:
1473 kfree(rxbuf);
1474 done:
1475 iio_trigger_notify_done(indio_dev->trig);
1476
1477 return IRQ_HANDLED;
1478 }
1479
1480 static const struct iio_buffer_setup_ops max1363_buffered_setup_ops = {
1481 .postenable = &iio_triggered_buffer_postenable,
1482 .preenable = &iio_sw_buffer_preenable,
1483 .predisable = &iio_triggered_buffer_predisable,
1484 };
1485
1486 static int max1363_probe(struct i2c_client *client,
1487 const struct i2c_device_id *id)
1488 {
1489 int ret;
1490 struct max1363_state *st;
1491 struct iio_dev *indio_dev;
1492
1493 indio_dev = iio_device_alloc(sizeof(struct max1363_state));
1494 if (indio_dev == NULL) {
1495 ret = -ENOMEM;
1496 goto error_out;
1497 }
1498
1499 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1500 if (ret < 0)
1501 goto error_free_device;
1502
1503 st = iio_priv(indio_dev);
1504
1505 st->reg = regulator_get(&client->dev, "vcc");
1506 if (IS_ERR(st->reg)) {
1507 ret = PTR_ERR(st->reg);
1508 goto error_unregister_map;
1509 }
1510
1511 ret = regulator_enable(st->reg);
1512 if (ret)
1513 goto error_put_reg;
1514
1515 /* this is only used for device removal purposes */
1516 i2c_set_clientdata(client, indio_dev);
1517
1518 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1519 st->client = client;
1520
1521 ret = max1363_alloc_scan_masks(indio_dev);
1522 if (ret)
1523 goto error_disable_reg;
1524
1525 /* Establish that the iio_dev is a child of the i2c device */
1526 indio_dev->dev.parent = &client->dev;
1527 indio_dev->name = id->name;
1528 indio_dev->channels = st->chip_info->channels;
1529 indio_dev->num_channels = st->chip_info->num_channels;
1530 indio_dev->info = st->chip_info->info;
1531 indio_dev->modes = INDIO_DIRECT_MODE;
1532 indio_dev->channels = st->chip_info->channels;
1533 indio_dev->num_channels = st->chip_info->num_channels;
1534 ret = max1363_initial_setup(st);
1535 if (ret < 0)
1536 goto error_free_available_scan_masks;
1537
1538 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1539 &max1363_trigger_handler, &max1363_buffered_setup_ops);
1540 if (ret)
1541 goto error_free_available_scan_masks;
1542
1543 if (client->irq) {
1544 ret = request_threaded_irq(st->client->irq,
1545 NULL,
1546 &max1363_event_handler,
1547 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1548 "max1363_event",
1549 indio_dev);
1550
1551 if (ret)
1552 goto error_uninit_buffer;
1553 }
1554
1555 ret = iio_device_register(indio_dev);
1556 if (ret < 0)
1557 goto error_free_irq;
1558
1559 return 0;
1560 error_free_irq:
1561 if (client->irq)
1562 free_irq(st->client->irq, indio_dev);
1563 error_uninit_buffer:
1564 iio_triggered_buffer_cleanup(indio_dev);
1565 error_free_available_scan_masks:
1566 kfree(indio_dev->available_scan_masks);
1567 error_disable_reg:
1568 regulator_disable(st->reg);
1569 error_put_reg:
1570 regulator_put(st->reg);
1571 error_unregister_map:
1572 iio_map_array_unregister(indio_dev, client->dev.platform_data);
1573 error_free_device:
1574 iio_device_free(indio_dev);
1575 error_out:
1576 return ret;
1577 }
1578
1579 static int max1363_remove(struct i2c_client *client)
1580 {
1581 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1582 struct max1363_state *st = iio_priv(indio_dev);
1583
1584 iio_device_unregister(indio_dev);
1585 if (client->irq)
1586 free_irq(st->client->irq, indio_dev);
1587 iio_triggered_buffer_cleanup(indio_dev);
1588 kfree(indio_dev->available_scan_masks);
1589 regulator_disable(st->reg);
1590 regulator_put(st->reg);
1591 iio_map_array_unregister(indio_dev, client->dev.platform_data);
1592 iio_device_free(indio_dev);
1593
1594 return 0;
1595 }
1596
1597 static const struct i2c_device_id max1363_id[] = {
1598 { "max1361", max1361 },
1599 { "max1362", max1362 },
1600 { "max1363", max1363 },
1601 { "max1364", max1364 },
1602 { "max1036", max1036 },
1603 { "max1037", max1037 },
1604 { "max1038", max1038 },
1605 { "max1039", max1039 },
1606 { "max1136", max1136 },
1607 { "max1137", max1137 },
1608 { "max1138", max1138 },
1609 { "max1139", max1139 },
1610 { "max1236", max1236 },
1611 { "max1237", max1237 },
1612 { "max1238", max1238 },
1613 { "max1239", max1239 },
1614 { "max11600", max11600 },
1615 { "max11601", max11601 },
1616 { "max11602", max11602 },
1617 { "max11603", max11603 },
1618 { "max11604", max11604 },
1619 { "max11605", max11605 },
1620 { "max11606", max11606 },
1621 { "max11607", max11607 },
1622 { "max11608", max11608 },
1623 { "max11609", max11609 },
1624 { "max11610", max11610 },
1625 { "max11611", max11611 },
1626 { "max11612", max11612 },
1627 { "max11613", max11613 },
1628 { "max11614", max11614 },
1629 { "max11615", max11615 },
1630 { "max11616", max11616 },
1631 { "max11617", max11617 },
1632 {}
1633 };
1634
1635 MODULE_DEVICE_TABLE(i2c, max1363_id);
1636
1637 static struct i2c_driver max1363_driver = {
1638 .driver = {
1639 .name = "max1363",
1640 },
1641 .probe = max1363_probe,
1642 .remove = max1363_remove,
1643 .id_table = max1363_id,
1644 };
1645 module_i2c_driver(max1363_driver);
1646
1647 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1648 MODULE_DESCRIPTION("Maxim 1363 ADC");
1649 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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