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IB/mlx5: Fix passing casted pointer in mlx5_query_port_roce
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/sched.h>
42 #include <rdma/ib_user_verbs.h>
43 #include <rdma/ib_addr.h>
44 #include <rdma/ib_cache.h>
45 #include <linux/mlx5/vport.h>
46 #include <rdma/ib_smi.h>
47 #include <rdma/ib_umem.h>
48 #include "user.h"
49 #include "mlx5_ib.h"
50
51 #define DRIVER_NAME "mlx5_ib"
52 #define DRIVER_VERSION "2.2-1"
53 #define DRIVER_RELDATE "Feb 2014"
54
55 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
57 MODULE_LICENSE("Dual BSD/GPL");
58 MODULE_VERSION(DRIVER_VERSION);
59
60 static int deprecated_prof_sel = 2;
61 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
62 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
63
64 static char mlx5_version[] =
65 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
66 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
67
68 enum {
69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
70 };
71
72 static enum rdma_link_layer
73 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
74 {
75 switch (port_type_cap) {
76 case MLX5_CAP_PORT_TYPE_IB:
77 return IB_LINK_LAYER_INFINIBAND;
78 case MLX5_CAP_PORT_TYPE_ETH:
79 return IB_LINK_LAYER_ETHERNET;
80 default:
81 return IB_LINK_LAYER_UNSPECIFIED;
82 }
83 }
84
85 static enum rdma_link_layer
86 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
87 {
88 struct mlx5_ib_dev *dev = to_mdev(device);
89 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
90
91 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
92 }
93
94 static int mlx5_netdev_event(struct notifier_block *this,
95 unsigned long event, void *ptr)
96 {
97 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
98 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
99 roce.nb);
100
101 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
102 return NOTIFY_DONE;
103
104 write_lock(&ibdev->roce.netdev_lock);
105 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
106 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
107 write_unlock(&ibdev->roce.netdev_lock);
108
109 return NOTIFY_DONE;
110 }
111
112 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
113 u8 port_num)
114 {
115 struct mlx5_ib_dev *ibdev = to_mdev(device);
116 struct net_device *ndev;
117
118 /* Ensure ndev does not disappear before we invoke dev_hold()
119 */
120 read_lock(&ibdev->roce.netdev_lock);
121 ndev = ibdev->roce.netdev;
122 if (ndev)
123 dev_hold(ndev);
124 read_unlock(&ibdev->roce.netdev_lock);
125
126 return ndev;
127 }
128
129 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
130 struct ib_port_attr *props)
131 {
132 struct mlx5_ib_dev *dev = to_mdev(device);
133 struct net_device *ndev;
134 enum ib_mtu ndev_ib_mtu;
135 u16 qkey_viol_cntr;
136
137 memset(props, 0, sizeof(*props));
138
139 props->port_cap_flags |= IB_PORT_CM_SUP;
140 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
141
142 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
143 roce_address_table_size);
144 props->max_mtu = IB_MTU_4096;
145 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
146 props->pkey_tbl_len = 1;
147 props->state = IB_PORT_DOWN;
148 props->phys_state = 3;
149
150 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
151 props->qkey_viol_cntr = qkey_viol_cntr;
152
153 ndev = mlx5_ib_get_netdev(device, port_num);
154 if (!ndev)
155 return 0;
156
157 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
158 props->state = IB_PORT_ACTIVE;
159 props->phys_state = 5;
160 }
161
162 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
163
164 dev_put(ndev);
165
166 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
167
168 props->active_width = IB_WIDTH_4X; /* TODO */
169 props->active_speed = IB_SPEED_QDR; /* TODO */
170
171 return 0;
172 }
173
174 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
175 const struct ib_gid_attr *attr,
176 void *mlx5_addr)
177 {
178 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
179 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
180 source_l3_address);
181 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
182 source_mac_47_32);
183
184 if (!gid)
185 return;
186
187 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
188
189 if (is_vlan_dev(attr->ndev)) {
190 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
191 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
192 }
193
194 switch (attr->gid_type) {
195 case IB_GID_TYPE_IB:
196 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
197 break;
198 case IB_GID_TYPE_ROCE_UDP_ENCAP:
199 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
200 break;
201
202 default:
203 WARN_ON(true);
204 }
205
206 if (attr->gid_type != IB_GID_TYPE_IB) {
207 if (ipv6_addr_v4mapped((void *)gid))
208 MLX5_SET_RA(mlx5_addr, roce_l3_type,
209 MLX5_ROCE_L3_TYPE_IPV4);
210 else
211 MLX5_SET_RA(mlx5_addr, roce_l3_type,
212 MLX5_ROCE_L3_TYPE_IPV6);
213 }
214
215 if ((attr->gid_type == IB_GID_TYPE_IB) ||
216 !ipv6_addr_v4mapped((void *)gid))
217 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
218 else
219 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
220 }
221
222 static int set_roce_addr(struct ib_device *device, u8 port_num,
223 unsigned int index,
224 const union ib_gid *gid,
225 const struct ib_gid_attr *attr)
226 {
227 struct mlx5_ib_dev *dev = to_mdev(device);
228 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
229 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
230 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
231 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
232
233 if (ll != IB_LINK_LAYER_ETHERNET)
234 return -EINVAL;
235
236 memset(in, 0, sizeof(in));
237
238 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
239
240 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
241 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
242
243 memset(out, 0, sizeof(out));
244 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
245 }
246
247 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
248 unsigned int index, const union ib_gid *gid,
249 const struct ib_gid_attr *attr,
250 __always_unused void **context)
251 {
252 return set_roce_addr(device, port_num, index, gid, attr);
253 }
254
255 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
256 unsigned int index, __always_unused void **context)
257 {
258 return set_roce_addr(device, port_num, index, NULL, NULL);
259 }
260
261 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
262 int index)
263 {
264 struct ib_gid_attr attr;
265 union ib_gid gid;
266
267 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
268 return 0;
269
270 if (!attr.ndev)
271 return 0;
272
273 dev_put(attr.ndev);
274
275 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
276 return 0;
277
278 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
279 }
280
281 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
282 {
283 return !dev->mdev->issi;
284 }
285
286 enum {
287 MLX5_VPORT_ACCESS_METHOD_MAD,
288 MLX5_VPORT_ACCESS_METHOD_HCA,
289 MLX5_VPORT_ACCESS_METHOD_NIC,
290 };
291
292 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
293 {
294 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
295 return MLX5_VPORT_ACCESS_METHOD_MAD;
296
297 if (mlx5_ib_port_link_layer(ibdev, 1) ==
298 IB_LINK_LAYER_ETHERNET)
299 return MLX5_VPORT_ACCESS_METHOD_NIC;
300
301 return MLX5_VPORT_ACCESS_METHOD_HCA;
302 }
303
304 static void get_atomic_caps(struct mlx5_ib_dev *dev,
305 struct ib_device_attr *props)
306 {
307 u8 tmp;
308 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
309 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
310 u8 atomic_req_8B_endianness_mode =
311 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
312
313 /* Check if HW supports 8 bytes standard atomic operations and capable
314 * of host endianness respond
315 */
316 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
317 if (((atomic_operations & tmp) == tmp) &&
318 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
319 (atomic_req_8B_endianness_mode)) {
320 props->atomic_cap = IB_ATOMIC_HCA;
321 } else {
322 props->atomic_cap = IB_ATOMIC_NONE;
323 }
324 }
325
326 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
327 __be64 *sys_image_guid)
328 {
329 struct mlx5_ib_dev *dev = to_mdev(ibdev);
330 struct mlx5_core_dev *mdev = dev->mdev;
331 u64 tmp;
332 int err;
333
334 switch (mlx5_get_vport_access_method(ibdev)) {
335 case MLX5_VPORT_ACCESS_METHOD_MAD:
336 return mlx5_query_mad_ifc_system_image_guid(ibdev,
337 sys_image_guid);
338
339 case MLX5_VPORT_ACCESS_METHOD_HCA:
340 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
341 break;
342
343 case MLX5_VPORT_ACCESS_METHOD_NIC:
344 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
345 break;
346
347 default:
348 return -EINVAL;
349 }
350
351 if (!err)
352 *sys_image_guid = cpu_to_be64(tmp);
353
354 return err;
355
356 }
357
358 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
359 u16 *max_pkeys)
360 {
361 struct mlx5_ib_dev *dev = to_mdev(ibdev);
362 struct mlx5_core_dev *mdev = dev->mdev;
363
364 switch (mlx5_get_vport_access_method(ibdev)) {
365 case MLX5_VPORT_ACCESS_METHOD_MAD:
366 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
367
368 case MLX5_VPORT_ACCESS_METHOD_HCA:
369 case MLX5_VPORT_ACCESS_METHOD_NIC:
370 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
371 pkey_table_size));
372 return 0;
373
374 default:
375 return -EINVAL;
376 }
377 }
378
379 static int mlx5_query_vendor_id(struct ib_device *ibdev,
380 u32 *vendor_id)
381 {
382 struct mlx5_ib_dev *dev = to_mdev(ibdev);
383
384 switch (mlx5_get_vport_access_method(ibdev)) {
385 case MLX5_VPORT_ACCESS_METHOD_MAD:
386 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
387
388 case MLX5_VPORT_ACCESS_METHOD_HCA:
389 case MLX5_VPORT_ACCESS_METHOD_NIC:
390 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
391
392 default:
393 return -EINVAL;
394 }
395 }
396
397 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
398 __be64 *node_guid)
399 {
400 u64 tmp;
401 int err;
402
403 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
404 case MLX5_VPORT_ACCESS_METHOD_MAD:
405 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
406
407 case MLX5_VPORT_ACCESS_METHOD_HCA:
408 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
409 break;
410
411 case MLX5_VPORT_ACCESS_METHOD_NIC:
412 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
413 break;
414
415 default:
416 return -EINVAL;
417 }
418
419 if (!err)
420 *node_guid = cpu_to_be64(tmp);
421
422 return err;
423 }
424
425 struct mlx5_reg_node_desc {
426 u8 desc[64];
427 };
428
429 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
430 {
431 struct mlx5_reg_node_desc in;
432
433 if (mlx5_use_mad_ifc(dev))
434 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
435
436 memset(&in, 0, sizeof(in));
437
438 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
439 sizeof(struct mlx5_reg_node_desc),
440 MLX5_REG_NODE_DESC, 0, 0);
441 }
442
443 static int mlx5_ib_query_device(struct ib_device *ibdev,
444 struct ib_device_attr *props,
445 struct ib_udata *uhw)
446 {
447 struct mlx5_ib_dev *dev = to_mdev(ibdev);
448 struct mlx5_core_dev *mdev = dev->mdev;
449 int err = -ENOMEM;
450 int max_rq_sg;
451 int max_sq_sg;
452 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
453
454 if (uhw->inlen || uhw->outlen)
455 return -EINVAL;
456
457 memset(props, 0, sizeof(*props));
458 err = mlx5_query_system_image_guid(ibdev,
459 &props->sys_image_guid);
460 if (err)
461 return err;
462
463 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
464 if (err)
465 return err;
466
467 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
468 if (err)
469 return err;
470
471 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
472 (fw_rev_min(dev->mdev) << 16) |
473 fw_rev_sub(dev->mdev);
474 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
475 IB_DEVICE_PORT_ACTIVE_EVENT |
476 IB_DEVICE_SYS_IMAGE_GUID |
477 IB_DEVICE_RC_RNR_NAK_GEN;
478
479 if (MLX5_CAP_GEN(mdev, pkv))
480 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
481 if (MLX5_CAP_GEN(mdev, qkv))
482 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
483 if (MLX5_CAP_GEN(mdev, apm))
484 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
485 if (MLX5_CAP_GEN(mdev, xrc))
486 props->device_cap_flags |= IB_DEVICE_XRC;
487 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
488 if (MLX5_CAP_GEN(mdev, sho)) {
489 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
490 /* At this stage no support for signature handover */
491 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
492 IB_PROT_T10DIF_TYPE_2 |
493 IB_PROT_T10DIF_TYPE_3;
494 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
495 IB_GUARD_T10DIF_CSUM;
496 }
497 if (MLX5_CAP_GEN(mdev, block_lb_mc))
498 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
499
500 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
501 (MLX5_CAP_ETH(dev->mdev, csum_cap)))
502 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
503
504 props->vendor_part_id = mdev->pdev->device;
505 props->hw_ver = mdev->pdev->revision;
506
507 props->max_mr_size = ~0ull;
508 props->page_size_cap = ~(min_page_size - 1);
509 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
510 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
511 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
512 sizeof(struct mlx5_wqe_data_seg);
513 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
514 sizeof(struct mlx5_wqe_ctrl_seg)) /
515 sizeof(struct mlx5_wqe_data_seg);
516 props->max_sge = min(max_rq_sg, max_sq_sg);
517 props->max_sge_rd = props->max_sge;
518 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
519 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
520 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
521 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
522 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
523 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
524 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
525 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
526 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
527 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
528 props->max_srq_sge = max_rq_sg - 1;
529 props->max_fast_reg_page_list_len = (unsigned int)-1;
530 get_atomic_caps(dev, props);
531 props->masked_atomic_cap = IB_ATOMIC_NONE;
532 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
533 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
534 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
535 props->max_mcast_grp;
536 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
537 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
538 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
539
540 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
541 if (MLX5_CAP_GEN(mdev, pg))
542 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
543 props->odp_caps = dev->odp_caps;
544 #endif
545
546 if (MLX5_CAP_GEN(mdev, cd))
547 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
548
549 return 0;
550 }
551
552 enum mlx5_ib_width {
553 MLX5_IB_WIDTH_1X = 1 << 0,
554 MLX5_IB_WIDTH_2X = 1 << 1,
555 MLX5_IB_WIDTH_4X = 1 << 2,
556 MLX5_IB_WIDTH_8X = 1 << 3,
557 MLX5_IB_WIDTH_12X = 1 << 4
558 };
559
560 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
561 u8 *ib_width)
562 {
563 struct mlx5_ib_dev *dev = to_mdev(ibdev);
564 int err = 0;
565
566 if (active_width & MLX5_IB_WIDTH_1X) {
567 *ib_width = IB_WIDTH_1X;
568 } else if (active_width & MLX5_IB_WIDTH_2X) {
569 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
570 (int)active_width);
571 err = -EINVAL;
572 } else if (active_width & MLX5_IB_WIDTH_4X) {
573 *ib_width = IB_WIDTH_4X;
574 } else if (active_width & MLX5_IB_WIDTH_8X) {
575 *ib_width = IB_WIDTH_8X;
576 } else if (active_width & MLX5_IB_WIDTH_12X) {
577 *ib_width = IB_WIDTH_12X;
578 } else {
579 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
580 (int)active_width);
581 err = -EINVAL;
582 }
583
584 return err;
585 }
586
587 static int mlx5_mtu_to_ib_mtu(int mtu)
588 {
589 switch (mtu) {
590 case 256: return 1;
591 case 512: return 2;
592 case 1024: return 3;
593 case 2048: return 4;
594 case 4096: return 5;
595 default:
596 pr_warn("invalid mtu\n");
597 return -1;
598 }
599 }
600
601 enum ib_max_vl_num {
602 __IB_MAX_VL_0 = 1,
603 __IB_MAX_VL_0_1 = 2,
604 __IB_MAX_VL_0_3 = 3,
605 __IB_MAX_VL_0_7 = 4,
606 __IB_MAX_VL_0_14 = 5,
607 };
608
609 enum mlx5_vl_hw_cap {
610 MLX5_VL_HW_0 = 1,
611 MLX5_VL_HW_0_1 = 2,
612 MLX5_VL_HW_0_2 = 3,
613 MLX5_VL_HW_0_3 = 4,
614 MLX5_VL_HW_0_4 = 5,
615 MLX5_VL_HW_0_5 = 6,
616 MLX5_VL_HW_0_6 = 7,
617 MLX5_VL_HW_0_7 = 8,
618 MLX5_VL_HW_0_14 = 15
619 };
620
621 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
622 u8 *max_vl_num)
623 {
624 switch (vl_hw_cap) {
625 case MLX5_VL_HW_0:
626 *max_vl_num = __IB_MAX_VL_0;
627 break;
628 case MLX5_VL_HW_0_1:
629 *max_vl_num = __IB_MAX_VL_0_1;
630 break;
631 case MLX5_VL_HW_0_3:
632 *max_vl_num = __IB_MAX_VL_0_3;
633 break;
634 case MLX5_VL_HW_0_7:
635 *max_vl_num = __IB_MAX_VL_0_7;
636 break;
637 case MLX5_VL_HW_0_14:
638 *max_vl_num = __IB_MAX_VL_0_14;
639 break;
640
641 default:
642 return -EINVAL;
643 }
644
645 return 0;
646 }
647
648 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
649 struct ib_port_attr *props)
650 {
651 struct mlx5_ib_dev *dev = to_mdev(ibdev);
652 struct mlx5_core_dev *mdev = dev->mdev;
653 struct mlx5_hca_vport_context *rep;
654 int max_mtu;
655 int oper_mtu;
656 int err;
657 u8 ib_link_width_oper;
658 u8 vl_hw_cap;
659
660 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
661 if (!rep) {
662 err = -ENOMEM;
663 goto out;
664 }
665
666 memset(props, 0, sizeof(*props));
667
668 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
669 if (err)
670 goto out;
671
672 props->lid = rep->lid;
673 props->lmc = rep->lmc;
674 props->sm_lid = rep->sm_lid;
675 props->sm_sl = rep->sm_sl;
676 props->state = rep->vport_state;
677 props->phys_state = rep->port_physical_state;
678 props->port_cap_flags = rep->cap_mask1;
679 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
680 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
681 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
682 props->bad_pkey_cntr = rep->pkey_violation_counter;
683 props->qkey_viol_cntr = rep->qkey_violation_counter;
684 props->subnet_timeout = rep->subnet_timeout;
685 props->init_type_reply = rep->init_type_reply;
686
687 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
688 if (err)
689 goto out;
690
691 err = translate_active_width(ibdev, ib_link_width_oper,
692 &props->active_width);
693 if (err)
694 goto out;
695 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
696 port);
697 if (err)
698 goto out;
699
700 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
701
702 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
703
704 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
705
706 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
707
708 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
709 if (err)
710 goto out;
711
712 err = translate_max_vl_num(ibdev, vl_hw_cap,
713 &props->max_vl_num);
714 out:
715 kfree(rep);
716 return err;
717 }
718
719 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
720 struct ib_port_attr *props)
721 {
722 switch (mlx5_get_vport_access_method(ibdev)) {
723 case MLX5_VPORT_ACCESS_METHOD_MAD:
724 return mlx5_query_mad_ifc_port(ibdev, port, props);
725
726 case MLX5_VPORT_ACCESS_METHOD_HCA:
727 return mlx5_query_hca_port(ibdev, port, props);
728
729 case MLX5_VPORT_ACCESS_METHOD_NIC:
730 return mlx5_query_port_roce(ibdev, port, props);
731
732 default:
733 return -EINVAL;
734 }
735 }
736
737 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
738 union ib_gid *gid)
739 {
740 struct mlx5_ib_dev *dev = to_mdev(ibdev);
741 struct mlx5_core_dev *mdev = dev->mdev;
742
743 switch (mlx5_get_vport_access_method(ibdev)) {
744 case MLX5_VPORT_ACCESS_METHOD_MAD:
745 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
746
747 case MLX5_VPORT_ACCESS_METHOD_HCA:
748 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
749
750 default:
751 return -EINVAL;
752 }
753
754 }
755
756 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
757 u16 *pkey)
758 {
759 struct mlx5_ib_dev *dev = to_mdev(ibdev);
760 struct mlx5_core_dev *mdev = dev->mdev;
761
762 switch (mlx5_get_vport_access_method(ibdev)) {
763 case MLX5_VPORT_ACCESS_METHOD_MAD:
764 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
765
766 case MLX5_VPORT_ACCESS_METHOD_HCA:
767 case MLX5_VPORT_ACCESS_METHOD_NIC:
768 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
769 pkey);
770 default:
771 return -EINVAL;
772 }
773 }
774
775 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
776 struct ib_device_modify *props)
777 {
778 struct mlx5_ib_dev *dev = to_mdev(ibdev);
779 struct mlx5_reg_node_desc in;
780 struct mlx5_reg_node_desc out;
781 int err;
782
783 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
784 return -EOPNOTSUPP;
785
786 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
787 return 0;
788
789 /*
790 * If possible, pass node desc to FW, so it can generate
791 * a 144 trap. If cmd fails, just ignore.
792 */
793 memcpy(&in, props->node_desc, 64);
794 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
795 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
796 if (err)
797 return err;
798
799 memcpy(ibdev->node_desc, props->node_desc, 64);
800
801 return err;
802 }
803
804 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
805 struct ib_port_modify *props)
806 {
807 struct mlx5_ib_dev *dev = to_mdev(ibdev);
808 struct ib_port_attr attr;
809 u32 tmp;
810 int err;
811
812 mutex_lock(&dev->cap_mask_mutex);
813
814 err = mlx5_ib_query_port(ibdev, port, &attr);
815 if (err)
816 goto out;
817
818 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
819 ~props->clr_port_cap_mask;
820
821 err = mlx5_set_port_caps(dev->mdev, port, tmp);
822
823 out:
824 mutex_unlock(&dev->cap_mask_mutex);
825 return err;
826 }
827
828 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
829 struct ib_udata *udata)
830 {
831 struct mlx5_ib_dev *dev = to_mdev(ibdev);
832 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
833 struct mlx5_ib_alloc_ucontext_resp resp = {};
834 struct mlx5_ib_ucontext *context;
835 struct mlx5_uuar_info *uuari;
836 struct mlx5_uar *uars;
837 int gross_uuars;
838 int num_uars;
839 int ver;
840 int uuarn;
841 int err;
842 int i;
843 size_t reqlen;
844
845 if (!dev->ib_active)
846 return ERR_PTR(-EAGAIN);
847
848 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
849 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
850 ver = 0;
851 else if (reqlen >= sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
852 ver = 2;
853 else
854 return ERR_PTR(-EINVAL);
855
856 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
857 if (err)
858 return ERR_PTR(err);
859
860 if (req.flags)
861 return ERR_PTR(-EINVAL);
862
863 if (req.total_num_uuars > MLX5_MAX_UUARS)
864 return ERR_PTR(-ENOMEM);
865
866 if (req.total_num_uuars == 0)
867 return ERR_PTR(-EINVAL);
868
869 if (req.comp_mask)
870 return ERR_PTR(-EOPNOTSUPP);
871
872 if (reqlen > sizeof(req) &&
873 !ib_is_udata_cleared(udata, sizeof(req),
874 udata->inlen - sizeof(req)))
875 return ERR_PTR(-EOPNOTSUPP);
876
877 req.total_num_uuars = ALIGN(req.total_num_uuars,
878 MLX5_NON_FP_BF_REGS_PER_PAGE);
879 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
880 return ERR_PTR(-EINVAL);
881
882 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
883 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
884 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
885 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
886 resp.cache_line_size = L1_CACHE_BYTES;
887 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
888 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
889 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
890 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
891 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
892 resp.response_length = min(offsetof(typeof(resp), response_length) +
893 sizeof(resp.response_length), udata->outlen);
894
895 context = kzalloc(sizeof(*context), GFP_KERNEL);
896 if (!context)
897 return ERR_PTR(-ENOMEM);
898
899 uuari = &context->uuari;
900 mutex_init(&uuari->lock);
901 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
902 if (!uars) {
903 err = -ENOMEM;
904 goto out_ctx;
905 }
906
907 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
908 sizeof(*uuari->bitmap),
909 GFP_KERNEL);
910 if (!uuari->bitmap) {
911 err = -ENOMEM;
912 goto out_uar_ctx;
913 }
914 /*
915 * clear all fast path uuars
916 */
917 for (i = 0; i < gross_uuars; i++) {
918 uuarn = i & 3;
919 if (uuarn == 2 || uuarn == 3)
920 set_bit(i, uuari->bitmap);
921 }
922
923 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
924 if (!uuari->count) {
925 err = -ENOMEM;
926 goto out_bitmap;
927 }
928
929 for (i = 0; i < num_uars; i++) {
930 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
931 if (err)
932 goto out_count;
933 }
934
935 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
936 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
937 #endif
938
939 INIT_LIST_HEAD(&context->db_page_list);
940 mutex_init(&context->db_page_mutex);
941
942 resp.tot_uuars = req.total_num_uuars;
943 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
944
945 if (field_avail(typeof(resp), reserved2, udata->outlen))
946 resp.response_length += sizeof(resp.reserved2);
947
948 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
949 resp.comp_mask |=
950 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
951 resp.hca_core_clock_offset =
952 offsetof(struct mlx5_init_seg, internal_timer_h) %
953 PAGE_SIZE;
954 resp.response_length += sizeof(resp.hca_core_clock_offset);
955 }
956
957 err = ib_copy_to_udata(udata, &resp, resp.response_length);
958 if (err)
959 goto out_uars;
960
961 uuari->ver = ver;
962 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
963 uuari->uars = uars;
964 uuari->num_uars = num_uars;
965 return &context->ibucontext;
966
967 out_uars:
968 for (i--; i >= 0; i--)
969 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
970 out_count:
971 kfree(uuari->count);
972
973 out_bitmap:
974 kfree(uuari->bitmap);
975
976 out_uar_ctx:
977 kfree(uars);
978
979 out_ctx:
980 kfree(context);
981 return ERR_PTR(err);
982 }
983
984 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
985 {
986 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
987 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
988 struct mlx5_uuar_info *uuari = &context->uuari;
989 int i;
990
991 for (i = 0; i < uuari->num_uars; i++) {
992 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
993 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
994 }
995
996 kfree(uuari->count);
997 kfree(uuari->bitmap);
998 kfree(uuari->uars);
999 kfree(context);
1000
1001 return 0;
1002 }
1003
1004 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1005 {
1006 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1007 }
1008
1009 static int get_command(unsigned long offset)
1010 {
1011 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1012 }
1013
1014 static int get_arg(unsigned long offset)
1015 {
1016 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1017 }
1018
1019 static int get_index(unsigned long offset)
1020 {
1021 return get_arg(offset);
1022 }
1023
1024 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1025 {
1026 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1027 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1028 struct mlx5_uuar_info *uuari = &context->uuari;
1029 unsigned long command;
1030 unsigned long idx;
1031 phys_addr_t pfn;
1032
1033 command = get_command(vma->vm_pgoff);
1034 switch (command) {
1035 case MLX5_IB_MMAP_REGULAR_PAGE:
1036 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1037 return -EINVAL;
1038
1039 idx = get_index(vma->vm_pgoff);
1040 if (idx >= uuari->num_uars)
1041 return -EINVAL;
1042
1043 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1044 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1045 (unsigned long long)pfn);
1046
1047 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1048 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1049 PAGE_SIZE, vma->vm_page_prot))
1050 return -EAGAIN;
1051
1052 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1053 vma->vm_start,
1054 (unsigned long long)pfn << PAGE_SHIFT);
1055 break;
1056
1057 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1058 return -ENOSYS;
1059
1060 case MLX5_IB_MMAP_CORE_CLOCK:
1061 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1062 return -EINVAL;
1063
1064 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1065 return -EPERM;
1066
1067 /* Don't expose to user-space information it shouldn't have */
1068 if (PAGE_SIZE > 4096)
1069 return -EOPNOTSUPP;
1070
1071 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1072 pfn = (dev->mdev->iseg_base +
1073 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1074 PAGE_SHIFT;
1075 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1076 PAGE_SIZE, vma->vm_page_prot))
1077 return -EAGAIN;
1078
1079 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1080 vma->vm_start,
1081 (unsigned long long)pfn << PAGE_SHIFT);
1082 break;
1083
1084 default:
1085 return -EINVAL;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1092 struct ib_ucontext *context,
1093 struct ib_udata *udata)
1094 {
1095 struct mlx5_ib_alloc_pd_resp resp;
1096 struct mlx5_ib_pd *pd;
1097 int err;
1098
1099 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1100 if (!pd)
1101 return ERR_PTR(-ENOMEM);
1102
1103 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1104 if (err) {
1105 kfree(pd);
1106 return ERR_PTR(err);
1107 }
1108
1109 if (context) {
1110 resp.pdn = pd->pdn;
1111 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1112 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1113 kfree(pd);
1114 return ERR_PTR(-EFAULT);
1115 }
1116 }
1117
1118 return &pd->ibpd;
1119 }
1120
1121 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1122 {
1123 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1124 struct mlx5_ib_pd *mpd = to_mpd(pd);
1125
1126 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1127 kfree(mpd);
1128
1129 return 0;
1130 }
1131
1132 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1133 {
1134 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1135 int err;
1136
1137 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
1138 if (err)
1139 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1140 ibqp->qp_num, gid->raw);
1141
1142 return err;
1143 }
1144
1145 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1146 {
1147 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1148 int err;
1149
1150 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
1151 if (err)
1152 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1153 ibqp->qp_num, gid->raw);
1154
1155 return err;
1156 }
1157
1158 static int init_node_data(struct mlx5_ib_dev *dev)
1159 {
1160 int err;
1161
1162 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
1163 if (err)
1164 return err;
1165
1166 dev->mdev->rev_id = dev->mdev->pdev->revision;
1167
1168 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
1169 }
1170
1171 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1172 char *buf)
1173 {
1174 struct mlx5_ib_dev *dev =
1175 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1176
1177 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
1178 }
1179
1180 static ssize_t show_reg_pages(struct device *device,
1181 struct device_attribute *attr, char *buf)
1182 {
1183 struct mlx5_ib_dev *dev =
1184 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1185
1186 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
1187 }
1188
1189 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1190 char *buf)
1191 {
1192 struct mlx5_ib_dev *dev =
1193 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1194 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
1195 }
1196
1197 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1198 char *buf)
1199 {
1200 struct mlx5_ib_dev *dev =
1201 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1202 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1203 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
1204 }
1205
1206 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1207 char *buf)
1208 {
1209 struct mlx5_ib_dev *dev =
1210 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1211 return sprintf(buf, "%x\n", dev->mdev->rev_id);
1212 }
1213
1214 static ssize_t show_board(struct device *device, struct device_attribute *attr,
1215 char *buf)
1216 {
1217 struct mlx5_ib_dev *dev =
1218 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1219 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
1220 dev->mdev->board_id);
1221 }
1222
1223 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1224 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1225 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1226 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1227 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1228 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1229
1230 static struct device_attribute *mlx5_class_attributes[] = {
1231 &dev_attr_hw_rev,
1232 &dev_attr_fw_ver,
1233 &dev_attr_hca_type,
1234 &dev_attr_board_id,
1235 &dev_attr_fw_pages,
1236 &dev_attr_reg_pages,
1237 };
1238
1239 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
1240 enum mlx5_dev_event event, unsigned long param)
1241 {
1242 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
1243 struct ib_event ibev;
1244
1245 u8 port = 0;
1246
1247 switch (event) {
1248 case MLX5_DEV_EVENT_SYS_ERROR:
1249 ibdev->ib_active = false;
1250 ibev.event = IB_EVENT_DEVICE_FATAL;
1251 break;
1252
1253 case MLX5_DEV_EVENT_PORT_UP:
1254 ibev.event = IB_EVENT_PORT_ACTIVE;
1255 port = (u8)param;
1256 break;
1257
1258 case MLX5_DEV_EVENT_PORT_DOWN:
1259 ibev.event = IB_EVENT_PORT_ERR;
1260 port = (u8)param;
1261 break;
1262
1263 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1264 /* not used by ULPs */
1265 return;
1266
1267 case MLX5_DEV_EVENT_LID_CHANGE:
1268 ibev.event = IB_EVENT_LID_CHANGE;
1269 port = (u8)param;
1270 break;
1271
1272 case MLX5_DEV_EVENT_PKEY_CHANGE:
1273 ibev.event = IB_EVENT_PKEY_CHANGE;
1274 port = (u8)param;
1275 break;
1276
1277 case MLX5_DEV_EVENT_GUID_CHANGE:
1278 ibev.event = IB_EVENT_GID_CHANGE;
1279 port = (u8)param;
1280 break;
1281
1282 case MLX5_DEV_EVENT_CLIENT_REREG:
1283 ibev.event = IB_EVENT_CLIENT_REREGISTER;
1284 port = (u8)param;
1285 break;
1286 }
1287
1288 ibev.device = &ibdev->ib_dev;
1289 ibev.element.port_num = port;
1290
1291 if (port < 1 || port > ibdev->num_ports) {
1292 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1293 return;
1294 }
1295
1296 if (ibdev->ib_active)
1297 ib_dispatch_event(&ibev);
1298 }
1299
1300 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1301 {
1302 int port;
1303
1304 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
1305 mlx5_query_ext_port_caps(dev, port);
1306 }
1307
1308 static int get_port_caps(struct mlx5_ib_dev *dev)
1309 {
1310 struct ib_device_attr *dprops = NULL;
1311 struct ib_port_attr *pprops = NULL;
1312 int err = -ENOMEM;
1313 int port;
1314 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
1315
1316 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1317 if (!pprops)
1318 goto out;
1319
1320 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1321 if (!dprops)
1322 goto out;
1323
1324 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
1325 if (err) {
1326 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1327 goto out;
1328 }
1329
1330 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
1331 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1332 if (err) {
1333 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1334 port, err);
1335 break;
1336 }
1337 dev->mdev->port_caps[port - 1].pkey_table_len =
1338 dprops->max_pkeys;
1339 dev->mdev->port_caps[port - 1].gid_table_len =
1340 pprops->gid_tbl_len;
1341 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1342 dprops->max_pkeys, pprops->gid_tbl_len);
1343 }
1344
1345 out:
1346 kfree(pprops);
1347 kfree(dprops);
1348
1349 return err;
1350 }
1351
1352 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1353 {
1354 int err;
1355
1356 err = mlx5_mr_cache_cleanup(dev);
1357 if (err)
1358 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1359
1360 mlx5_ib_destroy_qp(dev->umrc.qp);
1361 ib_destroy_cq(dev->umrc.cq);
1362 ib_dealloc_pd(dev->umrc.pd);
1363 }
1364
1365 enum {
1366 MAX_UMR_WR = 128,
1367 };
1368
1369 static int create_umr_res(struct mlx5_ib_dev *dev)
1370 {
1371 struct ib_qp_init_attr *init_attr = NULL;
1372 struct ib_qp_attr *attr = NULL;
1373 struct ib_pd *pd;
1374 struct ib_cq *cq;
1375 struct ib_qp *qp;
1376 struct ib_cq_init_attr cq_attr = {};
1377 int ret;
1378
1379 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1380 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1381 if (!attr || !init_attr) {
1382 ret = -ENOMEM;
1383 goto error_0;
1384 }
1385
1386 pd = ib_alloc_pd(&dev->ib_dev);
1387 if (IS_ERR(pd)) {
1388 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1389 ret = PTR_ERR(pd);
1390 goto error_0;
1391 }
1392
1393 cq_attr.cqe = 128;
1394 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
1395 &cq_attr);
1396 if (IS_ERR(cq)) {
1397 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1398 ret = PTR_ERR(cq);
1399 goto error_2;
1400 }
1401 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1402
1403 init_attr->send_cq = cq;
1404 init_attr->recv_cq = cq;
1405 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1406 init_attr->cap.max_send_wr = MAX_UMR_WR;
1407 init_attr->cap.max_send_sge = 1;
1408 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1409 init_attr->port_num = 1;
1410 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1411 if (IS_ERR(qp)) {
1412 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1413 ret = PTR_ERR(qp);
1414 goto error_3;
1415 }
1416 qp->device = &dev->ib_dev;
1417 qp->real_qp = qp;
1418 qp->uobject = NULL;
1419 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1420
1421 attr->qp_state = IB_QPS_INIT;
1422 attr->port_num = 1;
1423 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1424 IB_QP_PORT, NULL);
1425 if (ret) {
1426 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1427 goto error_4;
1428 }
1429
1430 memset(attr, 0, sizeof(*attr));
1431 attr->qp_state = IB_QPS_RTR;
1432 attr->path_mtu = IB_MTU_256;
1433
1434 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1435 if (ret) {
1436 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1437 goto error_4;
1438 }
1439
1440 memset(attr, 0, sizeof(*attr));
1441 attr->qp_state = IB_QPS_RTS;
1442 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1443 if (ret) {
1444 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1445 goto error_4;
1446 }
1447
1448 dev->umrc.qp = qp;
1449 dev->umrc.cq = cq;
1450 dev->umrc.pd = pd;
1451
1452 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1453 ret = mlx5_mr_cache_init(dev);
1454 if (ret) {
1455 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1456 goto error_4;
1457 }
1458
1459 kfree(attr);
1460 kfree(init_attr);
1461
1462 return 0;
1463
1464 error_4:
1465 mlx5_ib_destroy_qp(qp);
1466
1467 error_3:
1468 ib_destroy_cq(cq);
1469
1470 error_2:
1471 ib_dealloc_pd(pd);
1472
1473 error_0:
1474 kfree(attr);
1475 kfree(init_attr);
1476 return ret;
1477 }
1478
1479 static int create_dev_resources(struct mlx5_ib_resources *devr)
1480 {
1481 struct ib_srq_init_attr attr;
1482 struct mlx5_ib_dev *dev;
1483 struct ib_cq_init_attr cq_attr = {.cqe = 1};
1484 int ret = 0;
1485
1486 dev = container_of(devr, struct mlx5_ib_dev, devr);
1487
1488 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1489 if (IS_ERR(devr->p0)) {
1490 ret = PTR_ERR(devr->p0);
1491 goto error0;
1492 }
1493 devr->p0->device = &dev->ib_dev;
1494 devr->p0->uobject = NULL;
1495 atomic_set(&devr->p0->usecnt, 0);
1496
1497 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
1498 if (IS_ERR(devr->c0)) {
1499 ret = PTR_ERR(devr->c0);
1500 goto error1;
1501 }
1502 devr->c0->device = &dev->ib_dev;
1503 devr->c0->uobject = NULL;
1504 devr->c0->comp_handler = NULL;
1505 devr->c0->event_handler = NULL;
1506 devr->c0->cq_context = NULL;
1507 atomic_set(&devr->c0->usecnt, 0);
1508
1509 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1510 if (IS_ERR(devr->x0)) {
1511 ret = PTR_ERR(devr->x0);
1512 goto error2;
1513 }
1514 devr->x0->device = &dev->ib_dev;
1515 devr->x0->inode = NULL;
1516 atomic_set(&devr->x0->usecnt, 0);
1517 mutex_init(&devr->x0->tgt_qp_mutex);
1518 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1519
1520 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1521 if (IS_ERR(devr->x1)) {
1522 ret = PTR_ERR(devr->x1);
1523 goto error3;
1524 }
1525 devr->x1->device = &dev->ib_dev;
1526 devr->x1->inode = NULL;
1527 atomic_set(&devr->x1->usecnt, 0);
1528 mutex_init(&devr->x1->tgt_qp_mutex);
1529 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1530
1531 memset(&attr, 0, sizeof(attr));
1532 attr.attr.max_sge = 1;
1533 attr.attr.max_wr = 1;
1534 attr.srq_type = IB_SRQT_XRC;
1535 attr.ext.xrc.cq = devr->c0;
1536 attr.ext.xrc.xrcd = devr->x0;
1537
1538 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1539 if (IS_ERR(devr->s0)) {
1540 ret = PTR_ERR(devr->s0);
1541 goto error4;
1542 }
1543 devr->s0->device = &dev->ib_dev;
1544 devr->s0->pd = devr->p0;
1545 devr->s0->uobject = NULL;
1546 devr->s0->event_handler = NULL;
1547 devr->s0->srq_context = NULL;
1548 devr->s0->srq_type = IB_SRQT_XRC;
1549 devr->s0->ext.xrc.xrcd = devr->x0;
1550 devr->s0->ext.xrc.cq = devr->c0;
1551 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1552 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1553 atomic_inc(&devr->p0->usecnt);
1554 atomic_set(&devr->s0->usecnt, 0);
1555
1556 memset(&attr, 0, sizeof(attr));
1557 attr.attr.max_sge = 1;
1558 attr.attr.max_wr = 1;
1559 attr.srq_type = IB_SRQT_BASIC;
1560 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1561 if (IS_ERR(devr->s1)) {
1562 ret = PTR_ERR(devr->s1);
1563 goto error5;
1564 }
1565 devr->s1->device = &dev->ib_dev;
1566 devr->s1->pd = devr->p0;
1567 devr->s1->uobject = NULL;
1568 devr->s1->event_handler = NULL;
1569 devr->s1->srq_context = NULL;
1570 devr->s1->srq_type = IB_SRQT_BASIC;
1571 devr->s1->ext.xrc.cq = devr->c0;
1572 atomic_inc(&devr->p0->usecnt);
1573 atomic_set(&devr->s0->usecnt, 0);
1574
1575 return 0;
1576
1577 error5:
1578 mlx5_ib_destroy_srq(devr->s0);
1579 error4:
1580 mlx5_ib_dealloc_xrcd(devr->x1);
1581 error3:
1582 mlx5_ib_dealloc_xrcd(devr->x0);
1583 error2:
1584 mlx5_ib_destroy_cq(devr->c0);
1585 error1:
1586 mlx5_ib_dealloc_pd(devr->p0);
1587 error0:
1588 return ret;
1589 }
1590
1591 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1592 {
1593 mlx5_ib_destroy_srq(devr->s1);
1594 mlx5_ib_destroy_srq(devr->s0);
1595 mlx5_ib_dealloc_xrcd(devr->x0);
1596 mlx5_ib_dealloc_xrcd(devr->x1);
1597 mlx5_ib_destroy_cq(devr->c0);
1598 mlx5_ib_dealloc_pd(devr->p0);
1599 }
1600
1601 static u32 get_core_cap_flags(struct ib_device *ibdev)
1602 {
1603 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1604 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
1605 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
1606 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
1607 u32 ret = 0;
1608
1609 if (ll == IB_LINK_LAYER_INFINIBAND)
1610 return RDMA_CORE_PORT_IBA_IB;
1611
1612 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
1613 return 0;
1614
1615 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
1616 return 0;
1617
1618 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
1619 ret |= RDMA_CORE_PORT_IBA_ROCE;
1620
1621 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
1622 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
1623
1624 return ret;
1625 }
1626
1627 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
1628 struct ib_port_immutable *immutable)
1629 {
1630 struct ib_port_attr attr;
1631 int err;
1632
1633 err = mlx5_ib_query_port(ibdev, port_num, &attr);
1634 if (err)
1635 return err;
1636
1637 immutable->pkey_tbl_len = attr.pkey_tbl_len;
1638 immutable->gid_tbl_len = attr.gid_tbl_len;
1639 immutable->core_cap_flags = get_core_cap_flags(ibdev);
1640 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
1641
1642 return 0;
1643 }
1644
1645 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
1646 {
1647 int err;
1648
1649 dev->roce.nb.notifier_call = mlx5_netdev_event;
1650 err = register_netdevice_notifier(&dev->roce.nb);
1651 if (err)
1652 return err;
1653
1654 err = mlx5_nic_vport_enable_roce(dev->mdev);
1655 if (err)
1656 goto err_unregister_netdevice_notifier;
1657
1658 return 0;
1659
1660 err_unregister_netdevice_notifier:
1661 unregister_netdevice_notifier(&dev->roce.nb);
1662 return err;
1663 }
1664
1665 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
1666 {
1667 mlx5_nic_vport_disable_roce(dev->mdev);
1668 unregister_netdevice_notifier(&dev->roce.nb);
1669 }
1670
1671 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
1672 {
1673 struct mlx5_ib_dev *dev;
1674 enum rdma_link_layer ll;
1675 int port_type_cap;
1676 int err;
1677 int i;
1678
1679 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
1680 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
1681
1682 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
1683 return NULL;
1684
1685 printk_once(KERN_INFO "%s", mlx5_version);
1686
1687 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1688 if (!dev)
1689 return NULL;
1690
1691 dev->mdev = mdev;
1692
1693 rwlock_init(&dev->roce.netdev_lock);
1694 err = get_port_caps(dev);
1695 if (err)
1696 goto err_dealloc;
1697
1698 if (mlx5_use_mad_ifc(dev))
1699 get_ext_port_caps(dev);
1700
1701 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1702
1703 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1704 dev->ib_dev.owner = THIS_MODULE;
1705 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
1706 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
1707 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
1708 dev->ib_dev.phys_port_cnt = dev->num_ports;
1709 dev->ib_dev.num_comp_vectors =
1710 dev->mdev->priv.eq_table.num_comp_vectors;
1711 dev->ib_dev.dma_device = &mdev->pdev->dev;
1712
1713 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1714 dev->ib_dev.uverbs_cmd_mask =
1715 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1716 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1717 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1718 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1719 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1720 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1721 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1722 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1723 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1724 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1725 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1726 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1727 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1728 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1729 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1730 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1731 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1732 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1733 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1734 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1735 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1736 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1737 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1738 dev->ib_dev.uverbs_ex_cmd_mask =
1739 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
1740
1741 dev->ib_dev.query_device = mlx5_ib_query_device;
1742 dev->ib_dev.query_port = mlx5_ib_query_port;
1743 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
1744 if (ll == IB_LINK_LAYER_ETHERNET)
1745 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
1746 dev->ib_dev.query_gid = mlx5_ib_query_gid;
1747 dev->ib_dev.add_gid = mlx5_ib_add_gid;
1748 dev->ib_dev.del_gid = mlx5_ib_del_gid;
1749 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1750 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1751 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1752 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1753 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1754 dev->ib_dev.mmap = mlx5_ib_mmap;
1755 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1756 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1757 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1758 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1759 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1760 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1761 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1762 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1763 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1764 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1765 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1766 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1767 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1768 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1769 dev->ib_dev.post_send = mlx5_ib_post_send;
1770 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1771 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1772 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1773 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1774 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1775 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1776 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1777 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1778 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1779 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
1780 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1781 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1782 dev->ib_dev.process_mad = mlx5_ib_process_mad;
1783 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
1784 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
1785 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
1786 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
1787
1788 mlx5_ib_internal_fill_odp_caps(dev);
1789
1790 if (MLX5_CAP_GEN(mdev, xrc)) {
1791 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1792 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1793 dev->ib_dev.uverbs_cmd_mask |=
1794 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1795 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1796 }
1797
1798 err = init_node_data(dev);
1799 if (err)
1800 goto err_dealloc;
1801
1802 mutex_init(&dev->cap_mask_mutex);
1803
1804 if (ll == IB_LINK_LAYER_ETHERNET) {
1805 err = mlx5_enable_roce(dev);
1806 if (err)
1807 goto err_dealloc;
1808 }
1809
1810 err = create_dev_resources(&dev->devr);
1811 if (err)
1812 goto err_disable_roce;
1813
1814 err = mlx5_ib_odp_init_one(dev);
1815 if (err)
1816 goto err_rsrc;
1817
1818 err = ib_register_device(&dev->ib_dev, NULL);
1819 if (err)
1820 goto err_odp;
1821
1822 err = create_umr_res(dev);
1823 if (err)
1824 goto err_dev;
1825
1826 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
1827 err = device_create_file(&dev->ib_dev.dev,
1828 mlx5_class_attributes[i]);
1829 if (err)
1830 goto err_umrc;
1831 }
1832
1833 dev->ib_active = true;
1834
1835 return dev;
1836
1837 err_umrc:
1838 destroy_umrc_res(dev);
1839
1840 err_dev:
1841 ib_unregister_device(&dev->ib_dev);
1842
1843 err_odp:
1844 mlx5_ib_odp_remove_one(dev);
1845
1846 err_rsrc:
1847 destroy_dev_resources(&dev->devr);
1848
1849 err_disable_roce:
1850 if (ll == IB_LINK_LAYER_ETHERNET)
1851 mlx5_disable_roce(dev);
1852
1853 err_dealloc:
1854 ib_dealloc_device((struct ib_device *)dev);
1855
1856 return NULL;
1857 }
1858
1859 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
1860 {
1861 struct mlx5_ib_dev *dev = context;
1862 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
1863
1864 ib_unregister_device(&dev->ib_dev);
1865 destroy_umrc_res(dev);
1866 mlx5_ib_odp_remove_one(dev);
1867 destroy_dev_resources(&dev->devr);
1868 if (ll == IB_LINK_LAYER_ETHERNET)
1869 mlx5_disable_roce(dev);
1870 ib_dealloc_device(&dev->ib_dev);
1871 }
1872
1873 static struct mlx5_interface mlx5_ib_interface = {
1874 .add = mlx5_ib_add,
1875 .remove = mlx5_ib_remove,
1876 .event = mlx5_ib_event,
1877 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
1878 };
1879
1880 static int __init mlx5_ib_init(void)
1881 {
1882 int err;
1883
1884 if (deprecated_prof_sel != 2)
1885 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1886
1887 err = mlx5_ib_odp_init();
1888 if (err)
1889 return err;
1890
1891 err = mlx5_register_interface(&mlx5_ib_interface);
1892 if (err)
1893 goto clean_odp;
1894
1895 return err;
1896
1897 clean_odp:
1898 mlx5_ib_odp_cleanup();
1899 return err;
1900 }
1901
1902 static void __exit mlx5_ib_cleanup(void)
1903 {
1904 mlx5_unregister_interface(&mlx5_ib_interface);
1905 mlx5_ib_odp_cleanup();
1906 }
1907
1908 module_init(mlx5_ib_init);
1909 module_exit(mlx5_ib_cleanup);
Linux kernel - Deliverables
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