2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
59 #define DRIVER_NAME "mlx5_ib"
60 #define DRIVER_VERSION "2.2-1"
61 #define DRIVER_RELDATE "Feb 2014"
63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
64 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
65 MODULE_LICENSE("Dual BSD/GPL");
66 MODULE_VERSION(DRIVER_VERSION
);
68 static int deprecated_prof_sel
= 2;
69 module_param_named(prof_sel
, deprecated_prof_sel
, int, 0444);
70 MODULE_PARM_DESC(prof_sel
, "profile selector. Deprecated here. Moved to module mlx5_core");
72 static char mlx5_version
[] =
73 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
74 DRIVER_VERSION
" (" DRIVER_RELDATE
")\n";
77 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
80 static enum rdma_link_layer
81 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
83 switch (port_type_cap
) {
84 case MLX5_CAP_PORT_TYPE_IB
:
85 return IB_LINK_LAYER_INFINIBAND
;
86 case MLX5_CAP_PORT_TYPE_ETH
:
87 return IB_LINK_LAYER_ETHERNET
;
89 return IB_LINK_LAYER_UNSPECIFIED
;
93 static enum rdma_link_layer
94 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
96 struct mlx5_ib_dev
*dev
= to_mdev(device
);
97 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
99 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
102 static int mlx5_netdev_event(struct notifier_block
*this,
103 unsigned long event
, void *ptr
)
105 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
106 struct mlx5_ib_dev
*ibdev
= container_of(this, struct mlx5_ib_dev
,
109 if ((event
!= NETDEV_UNREGISTER
) && (event
!= NETDEV_REGISTER
))
112 write_lock(&ibdev
->roce
.netdev_lock
);
113 if (ndev
->dev
.parent
== &ibdev
->mdev
->pdev
->dev
)
114 ibdev
->roce
.netdev
= (event
== NETDEV_UNREGISTER
) ? NULL
: ndev
;
115 write_unlock(&ibdev
->roce
.netdev_lock
);
120 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
123 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
124 struct net_device
*ndev
;
126 /* Ensure ndev does not disappear before we invoke dev_hold()
128 read_lock(&ibdev
->roce
.netdev_lock
);
129 ndev
= ibdev
->roce
.netdev
;
132 read_unlock(&ibdev
->roce
.netdev_lock
);
137 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
138 struct ib_port_attr
*props
)
140 struct mlx5_ib_dev
*dev
= to_mdev(device
);
141 struct net_device
*ndev
;
142 enum ib_mtu ndev_ib_mtu
;
145 memset(props
, 0, sizeof(*props
));
147 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
148 props
->port_cap_flags
|= IB_PORT_IP_BASED_GIDS
;
150 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
151 roce_address_table_size
);
152 props
->max_mtu
= IB_MTU_4096
;
153 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
154 props
->pkey_tbl_len
= 1;
155 props
->state
= IB_PORT_DOWN
;
156 props
->phys_state
= 3;
158 mlx5_query_nic_vport_qkey_viol_cntr(dev
->mdev
, &qkey_viol_cntr
);
159 props
->qkey_viol_cntr
= qkey_viol_cntr
;
161 ndev
= mlx5_ib_get_netdev(device
, port_num
);
165 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
166 props
->state
= IB_PORT_ACTIVE
;
167 props
->phys_state
= 5;
170 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
174 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
176 props
->active_width
= IB_WIDTH_4X
; /* TODO */
177 props
->active_speed
= IB_SPEED_QDR
; /* TODO */
182 static void ib_gid_to_mlx5_roce_addr(const union ib_gid
*gid
,
183 const struct ib_gid_attr
*attr
,
186 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
187 char *mlx5_addr_l3_addr
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
189 void *mlx5_addr_mac
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
195 ether_addr_copy(mlx5_addr_mac
, attr
->ndev
->dev_addr
);
197 if (is_vlan_dev(attr
->ndev
)) {
198 MLX5_SET_RA(mlx5_addr
, vlan_valid
, 1);
199 MLX5_SET_RA(mlx5_addr
, vlan_id
, vlan_dev_vlan_id(attr
->ndev
));
202 switch (attr
->gid_type
) {
204 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_1
);
206 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
207 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_2
);
214 if (attr
->gid_type
!= IB_GID_TYPE_IB
) {
215 if (ipv6_addr_v4mapped((void *)gid
))
216 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
217 MLX5_ROCE_L3_TYPE_IPV4
);
219 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
220 MLX5_ROCE_L3_TYPE_IPV6
);
223 if ((attr
->gid_type
== IB_GID_TYPE_IB
) ||
224 !ipv6_addr_v4mapped((void *)gid
))
225 memcpy(mlx5_addr_l3_addr
, gid
, sizeof(*gid
));
227 memcpy(&mlx5_addr_l3_addr
[12], &gid
->raw
[12], 4);
230 static int set_roce_addr(struct ib_device
*device
, u8 port_num
,
232 const union ib_gid
*gid
,
233 const struct ib_gid_attr
*attr
)
235 struct mlx5_ib_dev
*dev
= to_mdev(device
);
236 u32 in
[MLX5_ST_SZ_DW(set_roce_address_in
)] = {0};
237 u32 out
[MLX5_ST_SZ_DW(set_roce_address_out
)] = {0};
238 void *in_addr
= MLX5_ADDR_OF(set_roce_address_in
, in
, roce_address
);
239 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(device
, port_num
);
241 if (ll
!= IB_LINK_LAYER_ETHERNET
)
244 ib_gid_to_mlx5_roce_addr(gid
, attr
, in_addr
);
246 MLX5_SET(set_roce_address_in
, in
, roce_address_index
, index
);
247 MLX5_SET(set_roce_address_in
, in
, opcode
, MLX5_CMD_OP_SET_ROCE_ADDRESS
);
248 return mlx5_cmd_exec(dev
->mdev
, in
, sizeof(in
), out
, sizeof(out
));
251 static int mlx5_ib_add_gid(struct ib_device
*device
, u8 port_num
,
252 unsigned int index
, const union ib_gid
*gid
,
253 const struct ib_gid_attr
*attr
,
254 __always_unused
void **context
)
256 return set_roce_addr(device
, port_num
, index
, gid
, attr
);
259 static int mlx5_ib_del_gid(struct ib_device
*device
, u8 port_num
,
260 unsigned int index
, __always_unused
void **context
)
262 return set_roce_addr(device
, port_num
, index
, NULL
, NULL
);
265 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
268 struct ib_gid_attr attr
;
271 if (ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
))
279 if (attr
.gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
282 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
285 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
287 return !MLX5_CAP_GEN(dev
->mdev
, ib_virt
);
291 MLX5_VPORT_ACCESS_METHOD_MAD
,
292 MLX5_VPORT_ACCESS_METHOD_HCA
,
293 MLX5_VPORT_ACCESS_METHOD_NIC
,
296 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
298 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
299 return MLX5_VPORT_ACCESS_METHOD_MAD
;
301 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
302 IB_LINK_LAYER_ETHERNET
)
303 return MLX5_VPORT_ACCESS_METHOD_NIC
;
305 return MLX5_VPORT_ACCESS_METHOD_HCA
;
308 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
309 struct ib_device_attr
*props
)
312 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
313 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
314 u8 atomic_req_8B_endianness_mode
=
315 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianess_mode
);
317 /* Check if HW supports 8 bytes standard atomic operations and capable
318 * of host endianness respond
320 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
321 if (((atomic_operations
& tmp
) == tmp
) &&
322 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
323 (atomic_req_8B_endianness_mode
)) {
324 props
->atomic_cap
= IB_ATOMIC_HCA
;
326 props
->atomic_cap
= IB_ATOMIC_NONE
;
330 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
331 __be64
*sys_image_guid
)
333 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
334 struct mlx5_core_dev
*mdev
= dev
->mdev
;
338 switch (mlx5_get_vport_access_method(ibdev
)) {
339 case MLX5_VPORT_ACCESS_METHOD_MAD
:
340 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
343 case MLX5_VPORT_ACCESS_METHOD_HCA
:
344 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
347 case MLX5_VPORT_ACCESS_METHOD_NIC
:
348 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
356 *sys_image_guid
= cpu_to_be64(tmp
);
362 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
365 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
366 struct mlx5_core_dev
*mdev
= dev
->mdev
;
368 switch (mlx5_get_vport_access_method(ibdev
)) {
369 case MLX5_VPORT_ACCESS_METHOD_MAD
:
370 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
372 case MLX5_VPORT_ACCESS_METHOD_HCA
:
373 case MLX5_VPORT_ACCESS_METHOD_NIC
:
374 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
383 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
386 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
388 switch (mlx5_get_vport_access_method(ibdev
)) {
389 case MLX5_VPORT_ACCESS_METHOD_MAD
:
390 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
392 case MLX5_VPORT_ACCESS_METHOD_HCA
:
393 case MLX5_VPORT_ACCESS_METHOD_NIC
:
394 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
401 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
407 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
408 case MLX5_VPORT_ACCESS_METHOD_MAD
:
409 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
411 case MLX5_VPORT_ACCESS_METHOD_HCA
:
412 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
415 case MLX5_VPORT_ACCESS_METHOD_NIC
:
416 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
424 *node_guid
= cpu_to_be64(tmp
);
429 struct mlx5_reg_node_desc
{
433 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
435 struct mlx5_reg_node_desc in
;
437 if (mlx5_use_mad_ifc(dev
))
438 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
440 memset(&in
, 0, sizeof(in
));
442 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
443 sizeof(struct mlx5_reg_node_desc
),
444 MLX5_REG_NODE_DESC
, 0, 0);
447 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
448 struct ib_device_attr
*props
,
449 struct ib_udata
*uhw
)
451 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
452 struct mlx5_core_dev
*mdev
= dev
->mdev
;
456 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
457 struct mlx5_ib_query_device_resp resp
= {};
461 resp_len
= sizeof(resp
.comp_mask
) + sizeof(resp
.response_length
);
462 if (uhw
->outlen
&& uhw
->outlen
< resp_len
)
465 resp
.response_length
= resp_len
;
467 if (uhw
->inlen
&& !ib_is_udata_cleared(uhw
, 0, uhw
->inlen
))
470 memset(props
, 0, sizeof(*props
));
471 err
= mlx5_query_system_image_guid(ibdev
,
472 &props
->sys_image_guid
);
476 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
480 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
484 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
485 (fw_rev_min(dev
->mdev
) << 16) |
486 fw_rev_sub(dev
->mdev
);
487 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
488 IB_DEVICE_PORT_ACTIVE_EVENT
|
489 IB_DEVICE_SYS_IMAGE_GUID
|
490 IB_DEVICE_RC_RNR_NAK_GEN
;
492 if (MLX5_CAP_GEN(mdev
, pkv
))
493 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
494 if (MLX5_CAP_GEN(mdev
, qkv
))
495 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
496 if (MLX5_CAP_GEN(mdev
, apm
))
497 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
498 if (MLX5_CAP_GEN(mdev
, xrc
))
499 props
->device_cap_flags
|= IB_DEVICE_XRC
;
500 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
501 props
->device_cap_flags
|= IB_DEVICE_MEM_WINDOW
|
502 IB_DEVICE_MEM_WINDOW_TYPE_2B
;
503 props
->max_mw
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
504 /* We support 'Gappy' memory registration too */
505 props
->device_cap_flags
|= IB_DEVICE_SG_GAPS_REG
;
507 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
508 if (MLX5_CAP_GEN(mdev
, sho
)) {
509 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
510 /* At this stage no support for signature handover */
511 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
512 IB_PROT_T10DIF_TYPE_2
|
513 IB_PROT_T10DIF_TYPE_3
;
514 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
515 IB_GUARD_T10DIF_CSUM
;
517 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
518 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
520 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
)) {
521 if (MLX5_CAP_ETH(mdev
, csum_cap
))
522 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
524 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
)) {
525 max_tso
= MLX5_CAP_ETH(mdev
, max_lso_cap
);
527 resp
.tso_caps
.max_tso
= 1 << max_tso
;
528 resp
.tso_caps
.supported_qpts
|=
529 1 << IB_QPT_RAW_PACKET
;
530 resp
.response_length
+= sizeof(resp
.tso_caps
);
535 if (MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
536 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
537 props
->device_cap_flags
|= IB_DEVICE_UD_TSO
;
540 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
541 MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
))
542 props
->device_cap_flags
|= IB_DEVICE_RAW_SCATTER_FCS
;
544 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
))
545 props
->device_cap_flags
|= IB_DEVICE_MANAGED_FLOW_STEERING
;
547 props
->vendor_part_id
= mdev
->pdev
->device
;
548 props
->hw_ver
= mdev
->pdev
->revision
;
550 props
->max_mr_size
= ~0ull;
551 props
->page_size_cap
= ~(min_page_size
- 1);
552 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
553 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
554 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
555 sizeof(struct mlx5_wqe_data_seg
);
556 max_sq_sg
= (MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
) -
557 sizeof(struct mlx5_wqe_ctrl_seg
)) /
558 sizeof(struct mlx5_wqe_data_seg
);
559 props
->max_sge
= min(max_rq_sg
, max_sq_sg
);
560 props
->max_sge_rd
= MLX5_MAX_SGE_RD
;
561 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
562 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
563 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
564 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
565 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
566 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
567 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
568 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
569 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
570 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
571 props
->max_srq_sge
= max_rq_sg
- 1;
572 props
->max_fast_reg_page_list_len
=
573 1 << MLX5_CAP_GEN(mdev
, log_max_klm_list_size
);
574 get_atomic_caps(dev
, props
);
575 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
576 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
577 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
578 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
579 props
->max_mcast_grp
;
580 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
581 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
582 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
584 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
585 if (MLX5_CAP_GEN(mdev
, pg
))
586 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
587 props
->odp_caps
= dev
->odp_caps
;
590 if (MLX5_CAP_GEN(mdev
, cd
))
591 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
593 if (!mlx5_core_is_pf(mdev
))
594 props
->device_cap_flags
|= IB_DEVICE_VIRTUAL_FUNCTION
;
597 err
= ib_copy_to_udata(uhw
, &resp
, resp
.response_length
);
607 MLX5_IB_WIDTH_1X
= 1 << 0,
608 MLX5_IB_WIDTH_2X
= 1 << 1,
609 MLX5_IB_WIDTH_4X
= 1 << 2,
610 MLX5_IB_WIDTH_8X
= 1 << 3,
611 MLX5_IB_WIDTH_12X
= 1 << 4
614 static int translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
617 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
620 if (active_width
& MLX5_IB_WIDTH_1X
) {
621 *ib_width
= IB_WIDTH_1X
;
622 } else if (active_width
& MLX5_IB_WIDTH_2X
) {
623 mlx5_ib_dbg(dev
, "active_width %d is not supported by IB spec\n",
626 } else if (active_width
& MLX5_IB_WIDTH_4X
) {
627 *ib_width
= IB_WIDTH_4X
;
628 } else if (active_width
& MLX5_IB_WIDTH_8X
) {
629 *ib_width
= IB_WIDTH_8X
;
630 } else if (active_width
& MLX5_IB_WIDTH_12X
) {
631 *ib_width
= IB_WIDTH_12X
;
633 mlx5_ib_dbg(dev
, "Invalid active_width %d\n",
641 static int mlx5_mtu_to_ib_mtu(int mtu
)
650 pr_warn("invalid mtu\n");
660 __IB_MAX_VL_0_14
= 5,
663 enum mlx5_vl_hw_cap
{
675 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
680 *max_vl_num
= __IB_MAX_VL_0
;
683 *max_vl_num
= __IB_MAX_VL_0_1
;
686 *max_vl_num
= __IB_MAX_VL_0_3
;
689 *max_vl_num
= __IB_MAX_VL_0_7
;
691 case MLX5_VL_HW_0_14
:
692 *max_vl_num
= __IB_MAX_VL_0_14
;
702 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
703 struct ib_port_attr
*props
)
705 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
706 struct mlx5_core_dev
*mdev
= dev
->mdev
;
707 struct mlx5_hca_vport_context
*rep
;
711 u8 ib_link_width_oper
;
714 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
720 memset(props
, 0, sizeof(*props
));
722 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
726 props
->lid
= rep
->lid
;
727 props
->lmc
= rep
->lmc
;
728 props
->sm_lid
= rep
->sm_lid
;
729 props
->sm_sl
= rep
->sm_sl
;
730 props
->state
= rep
->vport_state
;
731 props
->phys_state
= rep
->port_physical_state
;
732 props
->port_cap_flags
= rep
->cap_mask1
;
733 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
734 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
735 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
736 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
737 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
738 props
->subnet_timeout
= rep
->subnet_timeout
;
739 props
->init_type_reply
= rep
->init_type_reply
;
740 props
->grh_required
= rep
->grh_required
;
742 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
746 err
= translate_active_width(ibdev
, ib_link_width_oper
,
747 &props
->active_width
);
750 err
= mlx5_query_port_ib_proto_oper(mdev
, &props
->active_speed
, port
);
754 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
756 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
758 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
760 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
762 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
766 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
773 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
774 struct ib_port_attr
*props
)
776 switch (mlx5_get_vport_access_method(ibdev
)) {
777 case MLX5_VPORT_ACCESS_METHOD_MAD
:
778 return mlx5_query_mad_ifc_port(ibdev
, port
, props
);
780 case MLX5_VPORT_ACCESS_METHOD_HCA
:
781 return mlx5_query_hca_port(ibdev
, port
, props
);
783 case MLX5_VPORT_ACCESS_METHOD_NIC
:
784 return mlx5_query_port_roce(ibdev
, port
, props
);
791 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
794 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
795 struct mlx5_core_dev
*mdev
= dev
->mdev
;
797 switch (mlx5_get_vport_access_method(ibdev
)) {
798 case MLX5_VPORT_ACCESS_METHOD_MAD
:
799 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
801 case MLX5_VPORT_ACCESS_METHOD_HCA
:
802 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
810 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
813 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
814 struct mlx5_core_dev
*mdev
= dev
->mdev
;
816 switch (mlx5_get_vport_access_method(ibdev
)) {
817 case MLX5_VPORT_ACCESS_METHOD_MAD
:
818 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
820 case MLX5_VPORT_ACCESS_METHOD_HCA
:
821 case MLX5_VPORT_ACCESS_METHOD_NIC
:
822 return mlx5_query_hca_vport_pkey(mdev
, 0, port
, 0, index
,
829 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
830 struct ib_device_modify
*props
)
832 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
833 struct mlx5_reg_node_desc in
;
834 struct mlx5_reg_node_desc out
;
837 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
840 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
844 * If possible, pass node desc to FW, so it can generate
845 * a 144 trap. If cmd fails, just ignore.
847 memcpy(&in
, props
->node_desc
, 64);
848 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
849 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
853 memcpy(ibdev
->node_desc
, props
->node_desc
, 64);
858 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
859 struct ib_port_modify
*props
)
861 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
862 struct ib_port_attr attr
;
866 mutex_lock(&dev
->cap_mask_mutex
);
868 err
= mlx5_ib_query_port(ibdev
, port
, &attr
);
872 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
873 ~props
->clr_port_cap_mask
;
875 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
878 mutex_unlock(&dev
->cap_mask_mutex
);
882 static struct ib_ucontext
*mlx5_ib_alloc_ucontext(struct ib_device
*ibdev
,
883 struct ib_udata
*udata
)
885 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
886 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
887 struct mlx5_ib_alloc_ucontext_resp resp
= {};
888 struct mlx5_ib_ucontext
*context
;
889 struct mlx5_uuar_info
*uuari
;
890 struct mlx5_uar
*uars
;
898 size_t min_req_v2
= offsetof(struct mlx5_ib_alloc_ucontext_req_v2
,
902 return ERR_PTR(-EAGAIN
);
904 if (udata
->inlen
< sizeof(struct ib_uverbs_cmd_hdr
))
905 return ERR_PTR(-EINVAL
);
907 reqlen
= udata
->inlen
- sizeof(struct ib_uverbs_cmd_hdr
);
908 if (reqlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
910 else if (reqlen
>= min_req_v2
)
913 return ERR_PTR(-EINVAL
);
915 err
= ib_copy_from_udata(&req
, udata
, min(reqlen
, sizeof(req
)));
920 return ERR_PTR(-EINVAL
);
922 if (req
.total_num_uuars
> MLX5_MAX_UUARS
)
923 return ERR_PTR(-ENOMEM
);
925 if (req
.total_num_uuars
== 0)
926 return ERR_PTR(-EINVAL
);
928 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
929 return ERR_PTR(-EOPNOTSUPP
);
931 if (reqlen
> sizeof(req
) &&
932 !ib_is_udata_cleared(udata
, sizeof(req
),
933 reqlen
- sizeof(req
)))
934 return ERR_PTR(-EOPNOTSUPP
);
936 req
.total_num_uuars
= ALIGN(req
.total_num_uuars
,
937 MLX5_NON_FP_BF_REGS_PER_PAGE
);
938 if (req
.num_low_latency_uuars
> req
.total_num_uuars
- 1)
939 return ERR_PTR(-EINVAL
);
941 num_uars
= req
.total_num_uuars
/ MLX5_NON_FP_BF_REGS_PER_PAGE
;
942 gross_uuars
= num_uars
* MLX5_BF_REGS_PER_PAGE
;
943 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
944 if (mlx5_core_is_pf(dev
->mdev
) && MLX5_CAP_GEN(dev
->mdev
, bf
))
945 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
946 resp
.cache_line_size
= L1_CACHE_BYTES
;
947 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
948 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
949 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
950 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
951 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
952 resp
.cqe_version
= min_t(__u8
,
953 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
954 req
.max_cqe_version
);
955 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
956 sizeof(resp
.response_length
), udata
->outlen
);
958 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
960 return ERR_PTR(-ENOMEM
);
962 uuari
= &context
->uuari
;
963 mutex_init(&uuari
->lock
);
964 uars
= kcalloc(num_uars
, sizeof(*uars
), GFP_KERNEL
);
970 uuari
->bitmap
= kcalloc(BITS_TO_LONGS(gross_uuars
),
971 sizeof(*uuari
->bitmap
),
973 if (!uuari
->bitmap
) {
978 * clear all fast path uuars
980 for (i
= 0; i
< gross_uuars
; i
++) {
982 if (uuarn
== 2 || uuarn
== 3)
983 set_bit(i
, uuari
->bitmap
);
986 uuari
->count
= kcalloc(gross_uuars
, sizeof(*uuari
->count
), GFP_KERNEL
);
992 for (i
= 0; i
< num_uars
; i
++) {
993 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &uars
[i
].index
);
998 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
999 context
->ibucontext
.invalidate_range
= &mlx5_ib_invalidate_range
;
1002 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
)) {
1003 err
= mlx5_core_alloc_transport_domain(dev
->mdev
,
1009 INIT_LIST_HEAD(&context
->vma_private_list
);
1010 INIT_LIST_HEAD(&context
->db_page_list
);
1011 mutex_init(&context
->db_page_mutex
);
1013 resp
.tot_uuars
= req
.total_num_uuars
;
1014 resp
.num_ports
= MLX5_CAP_GEN(dev
->mdev
, num_ports
);
1016 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
1017 resp
.response_length
+= sizeof(resp
.cqe_version
);
1019 if (field_avail(typeof(resp
), cmds_supp_uhw
, udata
->outlen
)) {
1020 resp
.cmds_supp_uhw
|= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE
;
1021 resp
.response_length
+= sizeof(resp
.cmds_supp_uhw
);
1025 * We don't want to expose information from the PCI bar that is located
1026 * after 4096 bytes, so if the arch only supports larger pages, let's
1027 * pretend we don't support reading the HCA's core clock. This is also
1028 * forced by mmap function.
1030 if (PAGE_SIZE
<= 4096 &&
1031 field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
1033 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
1034 resp
.hca_core_clock_offset
=
1035 offsetof(struct mlx5_init_seg
, internal_timer_h
) %
1037 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
) +
1038 sizeof(resp
.reserved2
);
1041 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1046 uuari
->num_low_latency_uuars
= req
.num_low_latency_uuars
;
1048 uuari
->num_uars
= num_uars
;
1049 context
->cqe_version
= resp
.cqe_version
;
1051 return &context
->ibucontext
;
1054 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1055 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1058 for (i
--; i
>= 0; i
--)
1059 mlx5_cmd_free_uar(dev
->mdev
, uars
[i
].index
);
1061 kfree(uuari
->count
);
1064 kfree(uuari
->bitmap
);
1071 return ERR_PTR(err
);
1074 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
1076 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1077 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1078 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1081 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1082 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1084 for (i
= 0; i
< uuari
->num_uars
; i
++) {
1085 if (mlx5_cmd_free_uar(dev
->mdev
, uuari
->uars
[i
].index
))
1086 mlx5_ib_warn(dev
, "failed to free UAR 0x%x\n", uuari
->uars
[i
].index
);
1089 kfree(uuari
->count
);
1090 kfree(uuari
->bitmap
);
1097 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
, int index
)
1099 return (pci_resource_start(dev
->mdev
->pdev
, 0) >> PAGE_SHIFT
) + index
;
1102 static int get_command(unsigned long offset
)
1104 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
1107 static int get_arg(unsigned long offset
)
1109 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
1112 static int get_index(unsigned long offset
)
1114 return get_arg(offset
);
1117 static void mlx5_ib_vma_open(struct vm_area_struct
*area
)
1119 /* vma_open is called when a new VMA is created on top of our VMA. This
1120 * is done through either mremap flow or split_vma (usually due to
1121 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1122 * as this VMA is strongly hardware related. Therefore we set the
1123 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1124 * calling us again and trying to do incorrect actions. We assume that
1125 * the original VMA size is exactly a single page, and therefore all
1126 * "splitting" operation will not happen to it.
1128 area
->vm_ops
= NULL
;
1131 static void mlx5_ib_vma_close(struct vm_area_struct
*area
)
1133 struct mlx5_ib_vma_private_data
*mlx5_ib_vma_priv_data
;
1135 /* It's guaranteed that all VMAs opened on a FD are closed before the
1136 * file itself is closed, therefore no sync is needed with the regular
1137 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1138 * However need a sync with accessing the vma as part of
1139 * mlx5_ib_disassociate_ucontext.
1140 * The close operation is usually called under mm->mmap_sem except when
1141 * process is exiting.
1142 * The exiting case is handled explicitly as part of
1143 * mlx5_ib_disassociate_ucontext.
1145 mlx5_ib_vma_priv_data
= (struct mlx5_ib_vma_private_data
*)area
->vm_private_data
;
1147 /* setting the vma context pointer to null in the mlx5_ib driver's
1148 * private data, to protect a race condition in
1149 * mlx5_ib_disassociate_ucontext().
1151 mlx5_ib_vma_priv_data
->vma
= NULL
;
1152 list_del(&mlx5_ib_vma_priv_data
->list
);
1153 kfree(mlx5_ib_vma_priv_data
);
1156 static const struct vm_operations_struct mlx5_ib_vm_ops
= {
1157 .open
= mlx5_ib_vma_open
,
1158 .close
= mlx5_ib_vma_close
1161 static int mlx5_ib_set_vma_data(struct vm_area_struct
*vma
,
1162 struct mlx5_ib_ucontext
*ctx
)
1164 struct mlx5_ib_vma_private_data
*vma_prv
;
1165 struct list_head
*vma_head
= &ctx
->vma_private_list
;
1167 vma_prv
= kzalloc(sizeof(*vma_prv
), GFP_KERNEL
);
1172 vma
->vm_private_data
= vma_prv
;
1173 vma
->vm_ops
= &mlx5_ib_vm_ops
;
1175 list_add(&vma_prv
->list
, vma_head
);
1180 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext
*ibcontext
)
1183 struct vm_area_struct
*vma
;
1184 struct mlx5_ib_vma_private_data
*vma_private
, *n
;
1185 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1186 struct task_struct
*owning_process
= NULL
;
1187 struct mm_struct
*owning_mm
= NULL
;
1189 owning_process
= get_pid_task(ibcontext
->tgid
, PIDTYPE_PID
);
1190 if (!owning_process
)
1193 owning_mm
= get_task_mm(owning_process
);
1195 pr_info("no mm, disassociate ucontext is pending task termination\n");
1197 put_task_struct(owning_process
);
1198 usleep_range(1000, 2000);
1199 owning_process
= get_pid_task(ibcontext
->tgid
,
1201 if (!owning_process
||
1202 owning_process
->state
== TASK_DEAD
) {
1203 pr_info("disassociate ucontext done, task was terminated\n");
1204 /* in case task was dead need to release the
1208 put_task_struct(owning_process
);
1214 /* need to protect from a race on closing the vma as part of
1215 * mlx5_ib_vma_close.
1217 down_read(&owning_mm
->mmap_sem
);
1218 list_for_each_entry_safe(vma_private
, n
, &context
->vma_private_list
,
1220 vma
= vma_private
->vma
;
1221 ret
= zap_vma_ptes(vma
, vma
->vm_start
,
1223 WARN_ONCE(ret
, "%s: zap_vma_ptes failed", __func__
);
1224 /* context going to be destroyed, should
1225 * not access ops any more.
1228 list_del(&vma_private
->list
);
1231 up_read(&owning_mm
->mmap_sem
);
1233 put_task_struct(owning_process
);
1236 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd
)
1239 case MLX5_IB_MMAP_WC_PAGE
:
1241 case MLX5_IB_MMAP_REGULAR_PAGE
:
1242 return "best effort WC";
1243 case MLX5_IB_MMAP_NC_PAGE
:
1250 static int uar_mmap(struct mlx5_ib_dev
*dev
, enum mlx5_ib_mmap_cmd cmd
,
1251 struct vm_area_struct
*vma
,
1252 struct mlx5_ib_ucontext
*context
)
1254 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1257 phys_addr_t pfn
, pa
;
1261 case MLX5_IB_MMAP_WC_PAGE
:
1262 /* Some architectures don't support WC memory */
1263 #if defined(CONFIG_X86)
1266 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1270 case MLX5_IB_MMAP_REGULAR_PAGE
:
1271 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1272 prot
= pgprot_writecombine(vma
->vm_page_prot
);
1274 case MLX5_IB_MMAP_NC_PAGE
:
1275 prot
= pgprot_noncached(vma
->vm_page_prot
);
1281 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1284 idx
= get_index(vma
->vm_pgoff
);
1285 if (idx
>= uuari
->num_uars
)
1288 pfn
= uar_index2pfn(dev
, uuari
->uars
[idx
].index
);
1289 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn %pa\n", idx
, &pfn
);
1291 vma
->vm_page_prot
= prot
;
1292 err
= io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1293 PAGE_SIZE
, vma
->vm_page_prot
);
1295 mlx5_ib_err(dev
, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1296 err
, vma
->vm_start
, &pfn
, mmap_cmd2str(cmd
));
1300 pa
= pfn
<< PAGE_SHIFT
;
1301 mlx5_ib_dbg(dev
, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd
),
1302 vma
->vm_start
, &pa
);
1304 return mlx5_ib_set_vma_data(vma
, context
);
1307 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
1309 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1310 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1311 unsigned long command
;
1314 command
= get_command(vma
->vm_pgoff
);
1316 case MLX5_IB_MMAP_WC_PAGE
:
1317 case MLX5_IB_MMAP_NC_PAGE
:
1318 case MLX5_IB_MMAP_REGULAR_PAGE
:
1319 return uar_mmap(dev
, command
, vma
, context
);
1321 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
1324 case MLX5_IB_MMAP_CORE_CLOCK
:
1325 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1328 if (vma
->vm_flags
& VM_WRITE
)
1331 /* Don't expose to user-space information it shouldn't have */
1332 if (PAGE_SIZE
> 4096)
1335 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
1336 pfn
= (dev
->mdev
->iseg_base
+
1337 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
1339 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1340 PAGE_SIZE
, vma
->vm_page_prot
))
1343 mlx5_ib_dbg(dev
, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1345 (unsigned long long)pfn
<< PAGE_SHIFT
);
1355 static struct ib_pd
*mlx5_ib_alloc_pd(struct ib_device
*ibdev
,
1356 struct ib_ucontext
*context
,
1357 struct ib_udata
*udata
)
1359 struct mlx5_ib_alloc_pd_resp resp
;
1360 struct mlx5_ib_pd
*pd
;
1363 pd
= kmalloc(sizeof(*pd
), GFP_KERNEL
);
1365 return ERR_PTR(-ENOMEM
);
1367 err
= mlx5_core_alloc_pd(to_mdev(ibdev
)->mdev
, &pd
->pdn
);
1370 return ERR_PTR(err
);
1375 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
1376 mlx5_core_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
);
1378 return ERR_PTR(-EFAULT
);
1385 static int mlx5_ib_dealloc_pd(struct ib_pd
*pd
)
1387 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
1388 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
1390 mlx5_core_dealloc_pd(mdev
->mdev
, mpd
->pdn
);
1396 static bool outer_header_zero(u32
*match_criteria
)
1398 int size
= MLX5_ST_SZ_BYTES(fte_match_param
);
1399 char *outer_headers_c
= MLX5_ADDR_OF(fte_match_param
, match_criteria
,
1402 return outer_headers_c
[0] == 0 && !memcmp(outer_headers_c
,
1403 outer_headers_c
+ 1,
1407 static int parse_flow_attr(u32
*match_c
, u32
*match_v
,
1408 union ib_flow_spec
*ib_spec
)
1410 void *outer_headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1412 void *outer_headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1414 switch (ib_spec
->type
) {
1415 case IB_FLOW_SPEC_ETH
:
1416 if (ib_spec
->size
!= sizeof(ib_spec
->eth
))
1419 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1421 ib_spec
->eth
.mask
.dst_mac
);
1422 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1424 ib_spec
->eth
.val
.dst_mac
);
1426 if (ib_spec
->eth
.mask
.vlan_tag
) {
1427 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1429 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1432 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1433 first_vid
, ntohs(ib_spec
->eth
.mask
.vlan_tag
));
1434 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1435 first_vid
, ntohs(ib_spec
->eth
.val
.vlan_tag
));
1437 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1439 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 12);
1440 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1442 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 12);
1444 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1446 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 13);
1447 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1449 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 13);
1451 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1452 ethertype
, ntohs(ib_spec
->eth
.mask
.ether_type
));
1453 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1454 ethertype
, ntohs(ib_spec
->eth
.val
.ether_type
));
1456 case IB_FLOW_SPEC_IPV4
:
1457 if (ib_spec
->size
!= sizeof(ib_spec
->ipv4
))
1460 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1462 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1463 ethertype
, ETH_P_IP
);
1465 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1466 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1467 &ib_spec
->ipv4
.mask
.src_ip
,
1468 sizeof(ib_spec
->ipv4
.mask
.src_ip
));
1469 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1470 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1471 &ib_spec
->ipv4
.val
.src_ip
,
1472 sizeof(ib_spec
->ipv4
.val
.src_ip
));
1473 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1474 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1475 &ib_spec
->ipv4
.mask
.dst_ip
,
1476 sizeof(ib_spec
->ipv4
.mask
.dst_ip
));
1477 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1478 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1479 &ib_spec
->ipv4
.val
.dst_ip
,
1480 sizeof(ib_spec
->ipv4
.val
.dst_ip
));
1482 case IB_FLOW_SPEC_IPV6
:
1483 if (ib_spec
->size
!= sizeof(ib_spec
->ipv6
))
1486 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1488 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1489 ethertype
, ETH_P_IPV6
);
1491 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1492 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1493 &ib_spec
->ipv6
.mask
.src_ip
,
1494 sizeof(ib_spec
->ipv6
.mask
.src_ip
));
1495 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1496 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1497 &ib_spec
->ipv6
.val
.src_ip
,
1498 sizeof(ib_spec
->ipv6
.val
.src_ip
));
1499 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1500 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1501 &ib_spec
->ipv6
.mask
.dst_ip
,
1502 sizeof(ib_spec
->ipv6
.mask
.dst_ip
));
1503 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1504 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1505 &ib_spec
->ipv6
.val
.dst_ip
,
1506 sizeof(ib_spec
->ipv6
.val
.dst_ip
));
1508 case IB_FLOW_SPEC_TCP
:
1509 if (ib_spec
->size
!= sizeof(ib_spec
->tcp_udp
))
1512 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, ip_protocol
,
1514 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, ip_protocol
,
1517 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, tcp_sport
,
1518 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1519 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, tcp_sport
,
1520 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1522 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, tcp_dport
,
1523 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1524 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, tcp_dport
,
1525 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1527 case IB_FLOW_SPEC_UDP
:
1528 if (ib_spec
->size
!= sizeof(ib_spec
->tcp_udp
))
1531 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, ip_protocol
,
1533 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, ip_protocol
,
1536 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, udp_sport
,
1537 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1538 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, udp_sport
,
1539 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1541 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, udp_dport
,
1542 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1543 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, udp_dport
,
1544 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1553 /* If a flow could catch both multicast and unicast packets,
1554 * it won't fall into the multicast flow steering table and this rule
1555 * could steal other multicast packets.
1557 static bool flow_is_multicast_only(struct ib_flow_attr
*ib_attr
)
1559 struct ib_flow_spec_eth
*eth_spec
;
1561 if (ib_attr
->type
!= IB_FLOW_ATTR_NORMAL
||
1562 ib_attr
->size
< sizeof(struct ib_flow_attr
) +
1563 sizeof(struct ib_flow_spec_eth
) ||
1564 ib_attr
->num_of_specs
< 1)
1567 eth_spec
= (struct ib_flow_spec_eth
*)(ib_attr
+ 1);
1568 if (eth_spec
->type
!= IB_FLOW_SPEC_ETH
||
1569 eth_spec
->size
!= sizeof(*eth_spec
))
1572 return is_multicast_ether_addr(eth_spec
->mask
.dst_mac
) &&
1573 is_multicast_ether_addr(eth_spec
->val
.dst_mac
);
1576 static bool is_valid_attr(struct ib_flow_attr
*flow_attr
)
1578 union ib_flow_spec
*ib_spec
= (union ib_flow_spec
*)(flow_attr
+ 1);
1579 bool has_ipv4_spec
= false;
1580 bool eth_type_ipv4
= true;
1581 unsigned int spec_index
;
1583 /* Validate that ethertype is correct */
1584 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1585 if (ib_spec
->type
== IB_FLOW_SPEC_ETH
&&
1586 ib_spec
->eth
.mask
.ether_type
) {
1587 if (!((ib_spec
->eth
.mask
.ether_type
== htons(0xffff)) &&
1588 ib_spec
->eth
.val
.ether_type
== htons(ETH_P_IP
)))
1589 eth_type_ipv4
= false;
1590 } else if (ib_spec
->type
== IB_FLOW_SPEC_IPV4
) {
1591 has_ipv4_spec
= true;
1593 ib_spec
= (void *)ib_spec
+ ib_spec
->size
;
1595 return !has_ipv4_spec
|| eth_type_ipv4
;
1598 static void put_flow_table(struct mlx5_ib_dev
*dev
,
1599 struct mlx5_ib_flow_prio
*prio
, bool ft_added
)
1601 prio
->refcount
-= !!ft_added
;
1602 if (!prio
->refcount
) {
1603 mlx5_destroy_flow_table(prio
->flow_table
);
1604 prio
->flow_table
= NULL
;
1608 static int mlx5_ib_destroy_flow(struct ib_flow
*flow_id
)
1610 struct mlx5_ib_dev
*dev
= to_mdev(flow_id
->qp
->device
);
1611 struct mlx5_ib_flow_handler
*handler
= container_of(flow_id
,
1612 struct mlx5_ib_flow_handler
,
1614 struct mlx5_ib_flow_handler
*iter
, *tmp
;
1616 mutex_lock(&dev
->flow_db
.lock
);
1618 list_for_each_entry_safe(iter
, tmp
, &handler
->list
, list
) {
1619 mlx5_del_flow_rule(iter
->rule
);
1620 list_del(&iter
->list
);
1624 mlx5_del_flow_rule(handler
->rule
);
1625 put_flow_table(dev
, &dev
->flow_db
.prios
[handler
->prio
], true);
1626 mutex_unlock(&dev
->flow_db
.lock
);
1633 static int ib_prio_to_core_prio(unsigned int priority
, bool dont_trap
)
1641 #define MLX5_FS_MAX_TYPES 10
1642 #define MLX5_FS_MAX_ENTRIES 32000UL
1643 static struct mlx5_ib_flow_prio
*get_flow_table(struct mlx5_ib_dev
*dev
,
1644 struct ib_flow_attr
*flow_attr
)
1646 bool dont_trap
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
;
1647 struct mlx5_flow_namespace
*ns
= NULL
;
1648 struct mlx5_ib_flow_prio
*prio
;
1649 struct mlx5_flow_table
*ft
;
1655 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
1656 if (flow_is_multicast_only(flow_attr
) &&
1658 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
1660 priority
= ib_prio_to_core_prio(flow_attr
->priority
,
1662 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1663 MLX5_FLOW_NAMESPACE_BYPASS
);
1664 num_entries
= MLX5_FS_MAX_ENTRIES
;
1665 num_groups
= MLX5_FS_MAX_TYPES
;
1666 prio
= &dev
->flow_db
.prios
[priority
];
1667 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
1668 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
1669 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1670 MLX5_FLOW_NAMESPACE_LEFTOVERS
);
1671 build_leftovers_ft_param(&priority
,
1674 prio
= &dev
->flow_db
.prios
[MLX5_IB_FLOW_LEFTOVERS_PRIO
];
1678 return ERR_PTR(-ENOTSUPP
);
1680 ft
= prio
->flow_table
;
1682 ft
= mlx5_create_auto_grouped_flow_table(ns
, priority
,
1689 prio
->flow_table
= ft
;
1695 return err
? ERR_PTR(err
) : prio
;
1698 static struct mlx5_ib_flow_handler
*create_flow_rule(struct mlx5_ib_dev
*dev
,
1699 struct mlx5_ib_flow_prio
*ft_prio
,
1700 struct ib_flow_attr
*flow_attr
,
1701 struct mlx5_flow_destination
*dst
)
1703 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
1704 struct mlx5_ib_flow_handler
*handler
;
1705 struct mlx5_flow_spec
*spec
;
1706 void *ib_flow
= flow_attr
+ 1;
1707 unsigned int spec_index
;
1711 if (!is_valid_attr(flow_attr
))
1712 return ERR_PTR(-EINVAL
);
1714 spec
= mlx5_vzalloc(sizeof(*spec
));
1715 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
1716 if (!handler
|| !spec
) {
1721 INIT_LIST_HEAD(&handler
->list
);
1723 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1724 err
= parse_flow_attr(spec
->match_criteria
,
1725 spec
->match_value
, ib_flow
);
1729 ib_flow
+= ((union ib_flow_spec
*)ib_flow
)->size
;
1732 /* Outer header support only */
1733 spec
->match_criteria_enable
= (!outer_header_zero(spec
->match_criteria
))
1735 action
= dst
? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
:
1736 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO
;
1737 handler
->rule
= mlx5_add_flow_rule(ft
, spec
,
1739 MLX5_FS_DEFAULT_FLOW_TAG
,
1742 if (IS_ERR(handler
->rule
)) {
1743 err
= PTR_ERR(handler
->rule
);
1747 handler
->prio
= ft_prio
- dev
->flow_db
.prios
;
1749 ft_prio
->flow_table
= ft
;
1754 return err
? ERR_PTR(err
) : handler
;
1757 static struct mlx5_ib_flow_handler
*create_dont_trap_rule(struct mlx5_ib_dev
*dev
,
1758 struct mlx5_ib_flow_prio
*ft_prio
,
1759 struct ib_flow_attr
*flow_attr
,
1760 struct mlx5_flow_destination
*dst
)
1762 struct mlx5_ib_flow_handler
*handler_dst
= NULL
;
1763 struct mlx5_ib_flow_handler
*handler
= NULL
;
1765 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
, NULL
);
1766 if (!IS_ERR(handler
)) {
1767 handler_dst
= create_flow_rule(dev
, ft_prio
,
1769 if (IS_ERR(handler_dst
)) {
1770 mlx5_del_flow_rule(handler
->rule
);
1772 handler
= handler_dst
;
1774 list_add(&handler_dst
->list
, &handler
->list
);
1785 static struct mlx5_ib_flow_handler
*create_leftovers_rule(struct mlx5_ib_dev
*dev
,
1786 struct mlx5_ib_flow_prio
*ft_prio
,
1787 struct ib_flow_attr
*flow_attr
,
1788 struct mlx5_flow_destination
*dst
)
1790 struct mlx5_ib_flow_handler
*handler_ucast
= NULL
;
1791 struct mlx5_ib_flow_handler
*handler
= NULL
;
1794 struct ib_flow_attr flow_attr
;
1795 struct ib_flow_spec_eth eth_flow
;
1796 } leftovers_specs
[] = {
1800 .size
= sizeof(leftovers_specs
[0])
1803 .type
= IB_FLOW_SPEC_ETH
,
1804 .size
= sizeof(struct ib_flow_spec_eth
),
1805 .mask
= {.dst_mac
= {0x1} },
1806 .val
= {.dst_mac
= {0x1} }
1812 .size
= sizeof(leftovers_specs
[0])
1815 .type
= IB_FLOW_SPEC_ETH
,
1816 .size
= sizeof(struct ib_flow_spec_eth
),
1817 .mask
= {.dst_mac
= {0x1} },
1818 .val
= {.dst_mac
= {} }
1823 handler
= create_flow_rule(dev
, ft_prio
,
1824 &leftovers_specs
[LEFTOVERS_MC
].flow_attr
,
1826 if (!IS_ERR(handler
) &&
1827 flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
) {
1828 handler_ucast
= create_flow_rule(dev
, ft_prio
,
1829 &leftovers_specs
[LEFTOVERS_UC
].flow_attr
,
1831 if (IS_ERR(handler_ucast
)) {
1833 handler
= handler_ucast
;
1835 list_add(&handler_ucast
->list
, &handler
->list
);
1842 static struct ib_flow
*mlx5_ib_create_flow(struct ib_qp
*qp
,
1843 struct ib_flow_attr
*flow_attr
,
1846 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
1847 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
1848 struct mlx5_ib_flow_handler
*handler
= NULL
;
1849 struct mlx5_flow_destination
*dst
= NULL
;
1850 struct mlx5_ib_flow_prio
*ft_prio
;
1853 if (flow_attr
->priority
> MLX5_IB_FLOW_LAST_PRIO
)
1854 return ERR_PTR(-ENOSPC
);
1856 if (domain
!= IB_FLOW_DOMAIN_USER
||
1857 flow_attr
->port
> MLX5_CAP_GEN(dev
->mdev
, num_ports
) ||
1858 (flow_attr
->flags
& ~IB_FLOW_ATTR_FLAGS_DONT_TRAP
))
1859 return ERR_PTR(-EINVAL
);
1861 dst
= kzalloc(sizeof(*dst
), GFP_KERNEL
);
1863 return ERR_PTR(-ENOMEM
);
1865 mutex_lock(&dev
->flow_db
.lock
);
1867 ft_prio
= get_flow_table(dev
, flow_attr
);
1868 if (IS_ERR(ft_prio
)) {
1869 err
= PTR_ERR(ft_prio
);
1873 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_TIR
;
1874 if (mqp
->flags
& MLX5_IB_QP_RSS
)
1875 dst
->tir_num
= mqp
->rss_qp
.tirn
;
1877 dst
->tir_num
= mqp
->raw_packet_qp
.rq
.tirn
;
1879 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
1880 if (flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
) {
1881 handler
= create_dont_trap_rule(dev
, ft_prio
,
1884 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
,
1887 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
1888 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
1889 handler
= create_leftovers_rule(dev
, ft_prio
, flow_attr
,
1896 if (IS_ERR(handler
)) {
1897 err
= PTR_ERR(handler
);
1902 ft_prio
->refcount
++;
1903 mutex_unlock(&dev
->flow_db
.lock
);
1906 return &handler
->ibflow
;
1909 put_flow_table(dev
, ft_prio
, false);
1911 mutex_unlock(&dev
->flow_db
.lock
);
1914 return ERR_PTR(err
);
1917 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1919 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1922 err
= mlx5_core_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1924 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
1925 ibqp
->qp_num
, gid
->raw
);
1930 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1932 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1935 err
= mlx5_core_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1937 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
1938 ibqp
->qp_num
, gid
->raw
);
1943 static int init_node_data(struct mlx5_ib_dev
*dev
)
1947 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
1951 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
1953 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
1956 static ssize_t
show_fw_pages(struct device
*device
, struct device_attribute
*attr
,
1959 struct mlx5_ib_dev
*dev
=
1960 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1962 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
1965 static ssize_t
show_reg_pages(struct device
*device
,
1966 struct device_attribute
*attr
, char *buf
)
1968 struct mlx5_ib_dev
*dev
=
1969 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1971 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
1974 static ssize_t
show_hca(struct device
*device
, struct device_attribute
*attr
,
1977 struct mlx5_ib_dev
*dev
=
1978 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1979 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
1982 static ssize_t
show_rev(struct device
*device
, struct device_attribute
*attr
,
1985 struct mlx5_ib_dev
*dev
=
1986 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1987 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
1990 static ssize_t
show_board(struct device
*device
, struct device_attribute
*attr
,
1993 struct mlx5_ib_dev
*dev
=
1994 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1995 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
1996 dev
->mdev
->board_id
);
1999 static DEVICE_ATTR(hw_rev
, S_IRUGO
, show_rev
, NULL
);
2000 static DEVICE_ATTR(hca_type
, S_IRUGO
, show_hca
, NULL
);
2001 static DEVICE_ATTR(board_id
, S_IRUGO
, show_board
, NULL
);
2002 static DEVICE_ATTR(fw_pages
, S_IRUGO
, show_fw_pages
, NULL
);
2003 static DEVICE_ATTR(reg_pages
, S_IRUGO
, show_reg_pages
, NULL
);
2005 static struct device_attribute
*mlx5_class_attributes
[] = {
2010 &dev_attr_reg_pages
,
2013 static void pkey_change_handler(struct work_struct
*work
)
2015 struct mlx5_ib_port_resources
*ports
=
2016 container_of(work
, struct mlx5_ib_port_resources
,
2019 mutex_lock(&ports
->devr
->mutex
);
2020 mlx5_ib_gsi_pkey_change(ports
->gsi
);
2021 mutex_unlock(&ports
->devr
->mutex
);
2024 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev
*ibdev
)
2026 struct mlx5_ib_qp
*mqp
;
2027 struct mlx5_ib_cq
*send_mcq
, *recv_mcq
;
2028 struct mlx5_core_cq
*mcq
;
2029 struct list_head cq_armed_list
;
2030 unsigned long flags_qp
;
2031 unsigned long flags_cq
;
2032 unsigned long flags
;
2034 INIT_LIST_HEAD(&cq_armed_list
);
2036 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2037 spin_lock_irqsave(&ibdev
->reset_flow_resource_lock
, flags
);
2038 list_for_each_entry(mqp
, &ibdev
->qp_list
, qps_list
) {
2039 spin_lock_irqsave(&mqp
->sq
.lock
, flags_qp
);
2040 if (mqp
->sq
.tail
!= mqp
->sq
.head
) {
2041 send_mcq
= to_mcq(mqp
->ibqp
.send_cq
);
2042 spin_lock_irqsave(&send_mcq
->lock
, flags_cq
);
2043 if (send_mcq
->mcq
.comp
&&
2044 mqp
->ibqp
.send_cq
->comp_handler
) {
2045 if (!send_mcq
->mcq
.reset_notify_added
) {
2046 send_mcq
->mcq
.reset_notify_added
= 1;
2047 list_add_tail(&send_mcq
->mcq
.reset_notify
,
2051 spin_unlock_irqrestore(&send_mcq
->lock
, flags_cq
);
2053 spin_unlock_irqrestore(&mqp
->sq
.lock
, flags_qp
);
2054 spin_lock_irqsave(&mqp
->rq
.lock
, flags_qp
);
2055 /* no handling is needed for SRQ */
2056 if (!mqp
->ibqp
.srq
) {
2057 if (mqp
->rq
.tail
!= mqp
->rq
.head
) {
2058 recv_mcq
= to_mcq(mqp
->ibqp
.recv_cq
);
2059 spin_lock_irqsave(&recv_mcq
->lock
, flags_cq
);
2060 if (recv_mcq
->mcq
.comp
&&
2061 mqp
->ibqp
.recv_cq
->comp_handler
) {
2062 if (!recv_mcq
->mcq
.reset_notify_added
) {
2063 recv_mcq
->mcq
.reset_notify_added
= 1;
2064 list_add_tail(&recv_mcq
->mcq
.reset_notify
,
2068 spin_unlock_irqrestore(&recv_mcq
->lock
,
2072 spin_unlock_irqrestore(&mqp
->rq
.lock
, flags_qp
);
2074 /*At that point all inflight post send were put to be executed as of we
2075 * lock/unlock above locks Now need to arm all involved CQs.
2077 list_for_each_entry(mcq
, &cq_armed_list
, reset_notify
) {
2080 spin_unlock_irqrestore(&ibdev
->reset_flow_resource_lock
, flags
);
2083 static void mlx5_ib_event(struct mlx5_core_dev
*dev
, void *context
,
2084 enum mlx5_dev_event event
, unsigned long param
)
2086 struct mlx5_ib_dev
*ibdev
= (struct mlx5_ib_dev
*)context
;
2087 struct ib_event ibev
;
2092 case MLX5_DEV_EVENT_SYS_ERROR
:
2093 ibdev
->ib_active
= false;
2094 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
2095 mlx5_ib_handle_internal_error(ibdev
);
2098 case MLX5_DEV_EVENT_PORT_UP
:
2099 ibev
.event
= IB_EVENT_PORT_ACTIVE
;
2103 case MLX5_DEV_EVENT_PORT_DOWN
:
2104 case MLX5_DEV_EVENT_PORT_INITIALIZED
:
2105 ibev
.event
= IB_EVENT_PORT_ERR
;
2109 case MLX5_DEV_EVENT_LID_CHANGE
:
2110 ibev
.event
= IB_EVENT_LID_CHANGE
;
2114 case MLX5_DEV_EVENT_PKEY_CHANGE
:
2115 ibev
.event
= IB_EVENT_PKEY_CHANGE
;
2118 schedule_work(&ibdev
->devr
.ports
[port
- 1].pkey_change_work
);
2121 case MLX5_DEV_EVENT_GUID_CHANGE
:
2122 ibev
.event
= IB_EVENT_GID_CHANGE
;
2126 case MLX5_DEV_EVENT_CLIENT_REREG
:
2127 ibev
.event
= IB_EVENT_CLIENT_REREGISTER
;
2132 ibev
.device
= &ibdev
->ib_dev
;
2133 ibev
.element
.port_num
= port
;
2135 if (port
< 1 || port
> ibdev
->num_ports
) {
2136 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", port
);
2140 if (ibdev
->ib_active
)
2141 ib_dispatch_event(&ibev
);
2144 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
2148 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++)
2149 mlx5_query_ext_port_caps(dev
, port
);
2152 static int get_port_caps(struct mlx5_ib_dev
*dev
)
2154 struct ib_device_attr
*dprops
= NULL
;
2155 struct ib_port_attr
*pprops
= NULL
;
2158 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
2160 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
2164 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
2168 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
2170 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
2174 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++) {
2175 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
2177 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
2181 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
2183 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
2184 pprops
->gid_tbl_len
;
2185 mlx5_ib_dbg(dev
, "pkey_table_len %d, gid_table_len %d\n",
2186 dprops
->max_pkeys
, pprops
->gid_tbl_len
);
2196 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
2200 err
= mlx5_mr_cache_cleanup(dev
);
2202 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
2204 mlx5_ib_destroy_qp(dev
->umrc
.qp
);
2205 ib_free_cq(dev
->umrc
.cq
);
2206 ib_dealloc_pd(dev
->umrc
.pd
);
2213 static int create_umr_res(struct mlx5_ib_dev
*dev
)
2215 struct ib_qp_init_attr
*init_attr
= NULL
;
2216 struct ib_qp_attr
*attr
= NULL
;
2222 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
2223 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
2224 if (!attr
|| !init_attr
) {
2229 pd
= ib_alloc_pd(&dev
->ib_dev
);
2231 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
2236 cq
= ib_alloc_cq(&dev
->ib_dev
, NULL
, 128, 0, IB_POLL_SOFTIRQ
);
2238 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
2243 init_attr
->send_cq
= cq
;
2244 init_attr
->recv_cq
= cq
;
2245 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
2246 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
2247 init_attr
->cap
.max_send_sge
= 1;
2248 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2249 init_attr
->port_num
= 1;
2250 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
2252 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
2256 qp
->device
= &dev
->ib_dev
;
2259 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2261 attr
->qp_state
= IB_QPS_INIT
;
2263 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
2266 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
2270 memset(attr
, 0, sizeof(*attr
));
2271 attr
->qp_state
= IB_QPS_RTR
;
2272 attr
->path_mtu
= IB_MTU_256
;
2274 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2276 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
2280 memset(attr
, 0, sizeof(*attr
));
2281 attr
->qp_state
= IB_QPS_RTS
;
2282 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2284 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
2292 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
2293 ret
= mlx5_mr_cache_init(dev
);
2295 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
2305 mlx5_ib_destroy_qp(qp
);
2319 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
2321 struct ib_srq_init_attr attr
;
2322 struct mlx5_ib_dev
*dev
;
2323 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
2327 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
2329 mutex_init(&devr
->mutex
);
2331 devr
->p0
= mlx5_ib_alloc_pd(&dev
->ib_dev
, NULL
, NULL
);
2332 if (IS_ERR(devr
->p0
)) {
2333 ret
= PTR_ERR(devr
->p0
);
2336 devr
->p0
->device
= &dev
->ib_dev
;
2337 devr
->p0
->uobject
= NULL
;
2338 atomic_set(&devr
->p0
->usecnt
, 0);
2340 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
, NULL
);
2341 if (IS_ERR(devr
->c0
)) {
2342 ret
= PTR_ERR(devr
->c0
);
2345 devr
->c0
->device
= &dev
->ib_dev
;
2346 devr
->c0
->uobject
= NULL
;
2347 devr
->c0
->comp_handler
= NULL
;
2348 devr
->c0
->event_handler
= NULL
;
2349 devr
->c0
->cq_context
= NULL
;
2350 atomic_set(&devr
->c0
->usecnt
, 0);
2352 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2353 if (IS_ERR(devr
->x0
)) {
2354 ret
= PTR_ERR(devr
->x0
);
2357 devr
->x0
->device
= &dev
->ib_dev
;
2358 devr
->x0
->inode
= NULL
;
2359 atomic_set(&devr
->x0
->usecnt
, 0);
2360 mutex_init(&devr
->x0
->tgt_qp_mutex
);
2361 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
2363 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2364 if (IS_ERR(devr
->x1
)) {
2365 ret
= PTR_ERR(devr
->x1
);
2368 devr
->x1
->device
= &dev
->ib_dev
;
2369 devr
->x1
->inode
= NULL
;
2370 atomic_set(&devr
->x1
->usecnt
, 0);
2371 mutex_init(&devr
->x1
->tgt_qp_mutex
);
2372 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
2374 memset(&attr
, 0, sizeof(attr
));
2375 attr
.attr
.max_sge
= 1;
2376 attr
.attr
.max_wr
= 1;
2377 attr
.srq_type
= IB_SRQT_XRC
;
2378 attr
.ext
.xrc
.cq
= devr
->c0
;
2379 attr
.ext
.xrc
.xrcd
= devr
->x0
;
2381 devr
->s0
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2382 if (IS_ERR(devr
->s0
)) {
2383 ret
= PTR_ERR(devr
->s0
);
2386 devr
->s0
->device
= &dev
->ib_dev
;
2387 devr
->s0
->pd
= devr
->p0
;
2388 devr
->s0
->uobject
= NULL
;
2389 devr
->s0
->event_handler
= NULL
;
2390 devr
->s0
->srq_context
= NULL
;
2391 devr
->s0
->srq_type
= IB_SRQT_XRC
;
2392 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
2393 devr
->s0
->ext
.xrc
.cq
= devr
->c0
;
2394 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
2395 atomic_inc(&devr
->s0
->ext
.xrc
.cq
->usecnt
);
2396 atomic_inc(&devr
->p0
->usecnt
);
2397 atomic_set(&devr
->s0
->usecnt
, 0);
2399 memset(&attr
, 0, sizeof(attr
));
2400 attr
.attr
.max_sge
= 1;
2401 attr
.attr
.max_wr
= 1;
2402 attr
.srq_type
= IB_SRQT_BASIC
;
2403 devr
->s1
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2404 if (IS_ERR(devr
->s1
)) {
2405 ret
= PTR_ERR(devr
->s1
);
2408 devr
->s1
->device
= &dev
->ib_dev
;
2409 devr
->s1
->pd
= devr
->p0
;
2410 devr
->s1
->uobject
= NULL
;
2411 devr
->s1
->event_handler
= NULL
;
2412 devr
->s1
->srq_context
= NULL
;
2413 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
2414 devr
->s1
->ext
.xrc
.cq
= devr
->c0
;
2415 atomic_inc(&devr
->p0
->usecnt
);
2416 atomic_set(&devr
->s0
->usecnt
, 0);
2418 for (port
= 0; port
< ARRAY_SIZE(devr
->ports
); ++port
) {
2419 INIT_WORK(&devr
->ports
[port
].pkey_change_work
,
2420 pkey_change_handler
);
2421 devr
->ports
[port
].devr
= devr
;
2427 mlx5_ib_destroy_srq(devr
->s0
);
2429 mlx5_ib_dealloc_xrcd(devr
->x1
);
2431 mlx5_ib_dealloc_xrcd(devr
->x0
);
2433 mlx5_ib_destroy_cq(devr
->c0
);
2435 mlx5_ib_dealloc_pd(devr
->p0
);
2440 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
2442 struct mlx5_ib_dev
*dev
=
2443 container_of(devr
, struct mlx5_ib_dev
, devr
);
2446 mlx5_ib_destroy_srq(devr
->s1
);
2447 mlx5_ib_destroy_srq(devr
->s0
);
2448 mlx5_ib_dealloc_xrcd(devr
->x0
);
2449 mlx5_ib_dealloc_xrcd(devr
->x1
);
2450 mlx5_ib_destroy_cq(devr
->c0
);
2451 mlx5_ib_dealloc_pd(devr
->p0
);
2453 /* Make sure no change P_Key work items are still executing */
2454 for (port
= 0; port
< dev
->num_ports
; ++port
)
2455 cancel_work_sync(&devr
->ports
[port
].pkey_change_work
);
2458 static u32
get_core_cap_flags(struct ib_device
*ibdev
)
2460 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
2461 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
2462 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
2463 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
2466 if (ll
== IB_LINK_LAYER_INFINIBAND
)
2467 return RDMA_CORE_PORT_IBA_IB
;
2469 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
2472 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
2475 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
2476 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
2478 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
2479 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
2484 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
2485 struct ib_port_immutable
*immutable
)
2487 struct ib_port_attr attr
;
2490 err
= mlx5_ib_query_port(ibdev
, port_num
, &attr
);
2494 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
2495 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
2496 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
2497 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
2502 static void get_dev_fw_str(struct ib_device
*ibdev
, char *str
,
2505 struct mlx5_ib_dev
*dev
=
2506 container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
2507 snprintf(str
, str_len
, "%d.%d.%04d", fw_rev_maj(dev
->mdev
),
2508 fw_rev_min(dev
->mdev
), fw_rev_sub(dev
->mdev
));
2511 static int mlx5_enable_roce(struct mlx5_ib_dev
*dev
)
2515 dev
->roce
.nb
.notifier_call
= mlx5_netdev_event
;
2516 err
= register_netdevice_notifier(&dev
->roce
.nb
);
2520 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
2522 goto err_unregister_netdevice_notifier
;
2526 err_unregister_netdevice_notifier
:
2527 unregister_netdevice_notifier(&dev
->roce
.nb
);
2531 static void mlx5_disable_roce(struct mlx5_ib_dev
*dev
)
2533 mlx5_nic_vport_disable_roce(dev
->mdev
);
2534 unregister_netdevice_notifier(&dev
->roce
.nb
);
2537 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev
*dev
)
2541 for (i
= 0; i
< dev
->num_ports
; i
++)
2542 mlx5_core_dealloc_q_counter(dev
->mdev
,
2543 dev
->port
[i
].q_cnt_id
);
2546 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev
*dev
)
2551 for (i
= 0; i
< dev
->num_ports
; i
++) {
2552 ret
= mlx5_core_alloc_q_counter(dev
->mdev
,
2553 &dev
->port
[i
].q_cnt_id
);
2556 "couldn't allocate queue counter for port %d, err %d\n",
2558 goto dealloc_counters
;
2566 mlx5_core_dealloc_q_counter(dev
->mdev
,
2567 dev
->port
[i
].q_cnt_id
);
2572 static const char * const names
[] = {
2573 "rx_write_requests",
2575 "rx_atomic_requests",
2578 "duplicate_request",
2579 "rnr_nak_retry_err",
2581 "implied_nak_seq_err",
2582 "local_ack_timeout_err",
2585 static const size_t stats_offsets
[] = {
2586 MLX5_BYTE_OFF(query_q_counter_out
, rx_write_requests
),
2587 MLX5_BYTE_OFF(query_q_counter_out
, rx_read_requests
),
2588 MLX5_BYTE_OFF(query_q_counter_out
, rx_atomic_requests
),
2589 MLX5_BYTE_OFF(query_q_counter_out
, out_of_buffer
),
2590 MLX5_BYTE_OFF(query_q_counter_out
, out_of_sequence
),
2591 MLX5_BYTE_OFF(query_q_counter_out
, duplicate_request
),
2592 MLX5_BYTE_OFF(query_q_counter_out
, rnr_nak_retry_err
),
2593 MLX5_BYTE_OFF(query_q_counter_out
, packet_seq_err
),
2594 MLX5_BYTE_OFF(query_q_counter_out
, implied_nak_seq_err
),
2595 MLX5_BYTE_OFF(query_q_counter_out
, local_ack_timeout_err
),
2598 static struct rdma_hw_stats
*mlx5_ib_alloc_hw_stats(struct ib_device
*ibdev
,
2601 BUILD_BUG_ON(ARRAY_SIZE(names
) != ARRAY_SIZE(stats_offsets
));
2603 /* We support only per port stats */
2607 return rdma_alloc_hw_stats_struct(names
, ARRAY_SIZE(names
),
2608 RDMA_HW_STATS_DEFAULT_LIFESPAN
);
2611 static int mlx5_ib_get_hw_stats(struct ib_device
*ibdev
,
2612 struct rdma_hw_stats
*stats
,
2615 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
2616 int outlen
= MLX5_ST_SZ_BYTES(query_q_counter_out
);
2622 if (!port
|| !stats
)
2625 out
= mlx5_vzalloc(outlen
);
2629 ret
= mlx5_core_query_q_counter(dev
->mdev
,
2630 dev
->port
[port
- 1].q_cnt_id
, 0,
2635 for (i
= 0; i
< ARRAY_SIZE(names
); i
++) {
2636 val
= *(__be32
*)(out
+ stats_offsets
[i
]);
2637 stats
->value
[i
] = (u64
)be32_to_cpu(val
);
2641 return ARRAY_SIZE(names
);
2644 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
2646 struct mlx5_ib_dev
*dev
;
2647 enum rdma_link_layer ll
;
2652 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
2653 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
2655 if ((ll
== IB_LINK_LAYER_ETHERNET
) && !MLX5_CAP_GEN(mdev
, roce
))
2658 printk_once(KERN_INFO
"%s", mlx5_version
);
2660 dev
= (struct mlx5_ib_dev
*)ib_alloc_device(sizeof(*dev
));
2666 dev
->port
= kcalloc(MLX5_CAP_GEN(mdev
, num_ports
), sizeof(*dev
->port
),
2671 rwlock_init(&dev
->roce
.netdev_lock
);
2672 err
= get_port_caps(dev
);
2676 if (mlx5_use_mad_ifc(dev
))
2677 get_ext_port_caps(dev
);
2679 MLX5_INIT_DOORBELL_LOCK(&dev
->uar_lock
);
2681 strlcpy(dev
->ib_dev
.name
, "mlx5_%d", IB_DEVICE_NAME_MAX
);
2682 dev
->ib_dev
.owner
= THIS_MODULE
;
2683 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
2684 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
2685 dev
->num_ports
= MLX5_CAP_GEN(mdev
, num_ports
);
2686 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
2687 dev
->ib_dev
.num_comp_vectors
=
2688 dev
->mdev
->priv
.eq_table
.num_comp_vectors
;
2689 dev
->ib_dev
.dma_device
= &mdev
->pdev
->dev
;
2691 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
2692 dev
->ib_dev
.uverbs_cmd_mask
=
2693 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
2694 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
2695 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
2696 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
2697 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
2698 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
2699 (1ull << IB_USER_VERBS_CMD_REREG_MR
) |
2700 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
2701 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
2702 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
2703 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
2704 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
2705 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
2706 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
2707 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
2708 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
2709 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
2710 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
2711 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
2712 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
2713 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
2714 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
2715 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
2716 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
2717 dev
->ib_dev
.uverbs_ex_cmd_mask
=
2718 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
) |
2719 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ
) |
2720 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP
);
2722 dev
->ib_dev
.query_device
= mlx5_ib_query_device
;
2723 dev
->ib_dev
.query_port
= mlx5_ib_query_port
;
2724 dev
->ib_dev
.get_link_layer
= mlx5_ib_port_link_layer
;
2725 if (ll
== IB_LINK_LAYER_ETHERNET
)
2726 dev
->ib_dev
.get_netdev
= mlx5_ib_get_netdev
;
2727 dev
->ib_dev
.query_gid
= mlx5_ib_query_gid
;
2728 dev
->ib_dev
.add_gid
= mlx5_ib_add_gid
;
2729 dev
->ib_dev
.del_gid
= mlx5_ib_del_gid
;
2730 dev
->ib_dev
.query_pkey
= mlx5_ib_query_pkey
;
2731 dev
->ib_dev
.modify_device
= mlx5_ib_modify_device
;
2732 dev
->ib_dev
.modify_port
= mlx5_ib_modify_port
;
2733 dev
->ib_dev
.alloc_ucontext
= mlx5_ib_alloc_ucontext
;
2734 dev
->ib_dev
.dealloc_ucontext
= mlx5_ib_dealloc_ucontext
;
2735 dev
->ib_dev
.mmap
= mlx5_ib_mmap
;
2736 dev
->ib_dev
.alloc_pd
= mlx5_ib_alloc_pd
;
2737 dev
->ib_dev
.dealloc_pd
= mlx5_ib_dealloc_pd
;
2738 dev
->ib_dev
.create_ah
= mlx5_ib_create_ah
;
2739 dev
->ib_dev
.query_ah
= mlx5_ib_query_ah
;
2740 dev
->ib_dev
.destroy_ah
= mlx5_ib_destroy_ah
;
2741 dev
->ib_dev
.create_srq
= mlx5_ib_create_srq
;
2742 dev
->ib_dev
.modify_srq
= mlx5_ib_modify_srq
;
2743 dev
->ib_dev
.query_srq
= mlx5_ib_query_srq
;
2744 dev
->ib_dev
.destroy_srq
= mlx5_ib_destroy_srq
;
2745 dev
->ib_dev
.post_srq_recv
= mlx5_ib_post_srq_recv
;
2746 dev
->ib_dev
.create_qp
= mlx5_ib_create_qp
;
2747 dev
->ib_dev
.modify_qp
= mlx5_ib_modify_qp
;
2748 dev
->ib_dev
.query_qp
= mlx5_ib_query_qp
;
2749 dev
->ib_dev
.destroy_qp
= mlx5_ib_destroy_qp
;
2750 dev
->ib_dev
.post_send
= mlx5_ib_post_send
;
2751 dev
->ib_dev
.post_recv
= mlx5_ib_post_recv
;
2752 dev
->ib_dev
.create_cq
= mlx5_ib_create_cq
;
2753 dev
->ib_dev
.modify_cq
= mlx5_ib_modify_cq
;
2754 dev
->ib_dev
.resize_cq
= mlx5_ib_resize_cq
;
2755 dev
->ib_dev
.destroy_cq
= mlx5_ib_destroy_cq
;
2756 dev
->ib_dev
.poll_cq
= mlx5_ib_poll_cq
;
2757 dev
->ib_dev
.req_notify_cq
= mlx5_ib_arm_cq
;
2758 dev
->ib_dev
.get_dma_mr
= mlx5_ib_get_dma_mr
;
2759 dev
->ib_dev
.reg_user_mr
= mlx5_ib_reg_user_mr
;
2760 dev
->ib_dev
.rereg_user_mr
= mlx5_ib_rereg_user_mr
;
2761 dev
->ib_dev
.dereg_mr
= mlx5_ib_dereg_mr
;
2762 dev
->ib_dev
.attach_mcast
= mlx5_ib_mcg_attach
;
2763 dev
->ib_dev
.detach_mcast
= mlx5_ib_mcg_detach
;
2764 dev
->ib_dev
.process_mad
= mlx5_ib_process_mad
;
2765 dev
->ib_dev
.alloc_mr
= mlx5_ib_alloc_mr
;
2766 dev
->ib_dev
.map_mr_sg
= mlx5_ib_map_mr_sg
;
2767 dev
->ib_dev
.check_mr_status
= mlx5_ib_check_mr_status
;
2768 dev
->ib_dev
.get_port_immutable
= mlx5_port_immutable
;
2769 dev
->ib_dev
.get_dev_fw_str
= get_dev_fw_str
;
2770 if (mlx5_core_is_pf(mdev
)) {
2771 dev
->ib_dev
.get_vf_config
= mlx5_ib_get_vf_config
;
2772 dev
->ib_dev
.set_vf_link_state
= mlx5_ib_set_vf_link_state
;
2773 dev
->ib_dev
.get_vf_stats
= mlx5_ib_get_vf_stats
;
2774 dev
->ib_dev
.set_vf_guid
= mlx5_ib_set_vf_guid
;
2777 dev
->ib_dev
.disassociate_ucontext
= mlx5_ib_disassociate_ucontext
;
2779 mlx5_ib_internal_fill_odp_caps(dev
);
2781 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
2782 dev
->ib_dev
.alloc_mw
= mlx5_ib_alloc_mw
;
2783 dev
->ib_dev
.dealloc_mw
= mlx5_ib_dealloc_mw
;
2784 dev
->ib_dev
.uverbs_cmd_mask
|=
2785 (1ull << IB_USER_VERBS_CMD_ALLOC_MW
) |
2786 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW
);
2789 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
) &&
2790 MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
)) {
2791 dev
->ib_dev
.get_hw_stats
= mlx5_ib_get_hw_stats
;
2792 dev
->ib_dev
.alloc_hw_stats
= mlx5_ib_alloc_hw_stats
;
2795 if (MLX5_CAP_GEN(mdev
, xrc
)) {
2796 dev
->ib_dev
.alloc_xrcd
= mlx5_ib_alloc_xrcd
;
2797 dev
->ib_dev
.dealloc_xrcd
= mlx5_ib_dealloc_xrcd
;
2798 dev
->ib_dev
.uverbs_cmd_mask
|=
2799 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
2800 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
2803 if (mlx5_ib_port_link_layer(&dev
->ib_dev
, 1) ==
2804 IB_LINK_LAYER_ETHERNET
) {
2805 dev
->ib_dev
.create_flow
= mlx5_ib_create_flow
;
2806 dev
->ib_dev
.destroy_flow
= mlx5_ib_destroy_flow
;
2807 dev
->ib_dev
.create_wq
= mlx5_ib_create_wq
;
2808 dev
->ib_dev
.modify_wq
= mlx5_ib_modify_wq
;
2809 dev
->ib_dev
.destroy_wq
= mlx5_ib_destroy_wq
;
2810 dev
->ib_dev
.create_rwq_ind_table
= mlx5_ib_create_rwq_ind_table
;
2811 dev
->ib_dev
.destroy_rwq_ind_table
= mlx5_ib_destroy_rwq_ind_table
;
2812 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
2813 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW
) |
2814 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW
) |
2815 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ
) |
2816 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ
) |
2817 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ
) |
2818 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL
) |
2819 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL
);
2821 err
= init_node_data(dev
);
2825 mutex_init(&dev
->flow_db
.lock
);
2826 mutex_init(&dev
->cap_mask_mutex
);
2827 INIT_LIST_HEAD(&dev
->qp_list
);
2828 spin_lock_init(&dev
->reset_flow_resource_lock
);
2830 if (ll
== IB_LINK_LAYER_ETHERNET
) {
2831 err
= mlx5_enable_roce(dev
);
2836 err
= create_dev_resources(&dev
->devr
);
2838 goto err_disable_roce
;
2840 err
= mlx5_ib_odp_init_one(dev
);
2844 err
= mlx5_ib_alloc_q_counters(dev
);
2848 err
= ib_register_device(&dev
->ib_dev
, NULL
);
2852 err
= create_umr_res(dev
);
2856 for (i
= 0; i
< ARRAY_SIZE(mlx5_class_attributes
); i
++) {
2857 err
= device_create_file(&dev
->ib_dev
.dev
,
2858 mlx5_class_attributes
[i
]);
2863 dev
->ib_active
= true;
2868 destroy_umrc_res(dev
);
2871 ib_unregister_device(&dev
->ib_dev
);
2874 mlx5_ib_dealloc_q_counters(dev
);
2877 mlx5_ib_odp_remove_one(dev
);
2880 destroy_dev_resources(&dev
->devr
);
2883 if (ll
== IB_LINK_LAYER_ETHERNET
)
2884 mlx5_disable_roce(dev
);
2890 ib_dealloc_device((struct ib_device
*)dev
);
2895 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
2897 struct mlx5_ib_dev
*dev
= context
;
2898 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
, 1);
2900 ib_unregister_device(&dev
->ib_dev
);
2901 mlx5_ib_dealloc_q_counters(dev
);
2902 destroy_umrc_res(dev
);
2903 mlx5_ib_odp_remove_one(dev
);
2904 destroy_dev_resources(&dev
->devr
);
2905 if (ll
== IB_LINK_LAYER_ETHERNET
)
2906 mlx5_disable_roce(dev
);
2908 ib_dealloc_device(&dev
->ib_dev
);
2911 static struct mlx5_interface mlx5_ib_interface
= {
2913 .remove
= mlx5_ib_remove
,
2914 .event
= mlx5_ib_event
,
2915 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
2918 static int __init
mlx5_ib_init(void)
2922 if (deprecated_prof_sel
!= 2)
2923 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2925 err
= mlx5_ib_odp_init();
2929 err
= mlx5_register_interface(&mlx5_ib_interface
);
2936 mlx5_ib_odp_cleanup();
2940 static void __exit
mlx5_ib_cleanup(void)
2942 mlx5_unregister_interface(&mlx5_ib_interface
);
2943 mlx5_ib_odp_cleanup();
2946 module_init(mlx5_ib_init
);
2947 module_exit(mlx5_ib_cleanup
);