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Merge remote-tracking branches 'asoc/topic/ab8500', 'asoc/topic/adau17x1', 'asoc...
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include "mlx5_ib.h"
38 #include "user.h"
39
40 /* not supported currently */
41 static int wq_signature;
42
43 enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52 };
53
54 enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57 };
58
59 static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73 };
74
75
76 static int is_qp0(enum ib_qp_type qp_type)
77 {
78 return qp_type == IB_QPT_SMI;
79 }
80
81 static int is_sqp(enum ib_qp_type qp_type)
82 {
83 return is_qp0(qp_type) || is_qp1(qp_type);
84 }
85
86 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
87 {
88 return mlx5_buf_offset(&qp->buf, offset);
89 }
90
91 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
92 {
93 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
94 }
95
96 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
97 {
98 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
99 }
100
101 /**
102 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
103 *
104 * @qp: QP to copy from.
105 * @send: copy from the send queue when non-zero, use the receive queue
106 * otherwise.
107 * @wqe_index: index to start copying from. For send work queues, the
108 * wqe_index is in units of MLX5_SEND_WQE_BB.
109 * For receive work queue, it is the number of work queue
110 * element in the queue.
111 * @buffer: destination buffer.
112 * @length: maximum number of bytes to copy.
113 *
114 * Copies at least a single WQE, but may copy more data.
115 *
116 * Return: the number of bytes copied, or an error code.
117 */
118 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
119 void *buffer, u32 length,
120 struct mlx5_ib_qp_base *base)
121 {
122 struct ib_device *ibdev = qp->ibqp.device;
123 struct mlx5_ib_dev *dev = to_mdev(ibdev);
124 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
125 size_t offset;
126 size_t wq_end;
127 struct ib_umem *umem = base->ubuffer.umem;
128 u32 first_copy_length;
129 int wqe_length;
130 int ret;
131
132 if (wq->wqe_cnt == 0) {
133 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
134 qp->ibqp.qp_type);
135 return -EINVAL;
136 }
137
138 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
139 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
140
141 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
142 return -EINVAL;
143
144 if (offset > umem->length ||
145 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
146 return -EINVAL;
147
148 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
149 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
150 if (ret)
151 return ret;
152
153 if (send) {
154 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
155 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
156
157 wqe_length = ds * MLX5_WQE_DS_UNITS;
158 } else {
159 wqe_length = 1 << wq->wqe_shift;
160 }
161
162 if (wqe_length <= first_copy_length)
163 return first_copy_length;
164
165 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
166 wqe_length - first_copy_length);
167 if (ret)
168 return ret;
169
170 return wqe_length;
171 }
172
173 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
174 {
175 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
176 struct ib_event event;
177
178 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
179 /* This event is only valid for trans_qps */
180 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
181 }
182
183 if (ibqp->event_handler) {
184 event.device = ibqp->device;
185 event.element.qp = ibqp;
186 switch (type) {
187 case MLX5_EVENT_TYPE_PATH_MIG:
188 event.event = IB_EVENT_PATH_MIG;
189 break;
190 case MLX5_EVENT_TYPE_COMM_EST:
191 event.event = IB_EVENT_COMM_EST;
192 break;
193 case MLX5_EVENT_TYPE_SQ_DRAINED:
194 event.event = IB_EVENT_SQ_DRAINED;
195 break;
196 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
197 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
198 break;
199 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
200 event.event = IB_EVENT_QP_FATAL;
201 break;
202 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
203 event.event = IB_EVENT_PATH_MIG_ERR;
204 break;
205 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
206 event.event = IB_EVENT_QP_REQ_ERR;
207 break;
208 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
209 event.event = IB_EVENT_QP_ACCESS_ERR;
210 break;
211 default:
212 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
213 return;
214 }
215
216 ibqp->event_handler(&event, ibqp->qp_context);
217 }
218 }
219
220 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
221 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
222 {
223 int wqe_size;
224 int wq_size;
225
226 /* Sanity check RQ size before proceeding */
227 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
228 return -EINVAL;
229
230 if (!has_rq) {
231 qp->rq.max_gs = 0;
232 qp->rq.wqe_cnt = 0;
233 qp->rq.wqe_shift = 0;
234 } else {
235 if (ucmd) {
236 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
237 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
238 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
239 qp->rq.max_post = qp->rq.wqe_cnt;
240 } else {
241 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
242 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
243 wqe_size = roundup_pow_of_two(wqe_size);
244 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
245 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
246 qp->rq.wqe_cnt = wq_size / wqe_size;
247 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
248 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
249 wqe_size,
250 MLX5_CAP_GEN(dev->mdev,
251 max_wqe_sz_rq));
252 return -EINVAL;
253 }
254 qp->rq.wqe_shift = ilog2(wqe_size);
255 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
256 qp->rq.max_post = qp->rq.wqe_cnt;
257 }
258 }
259
260 return 0;
261 }
262
263 static int sq_overhead(enum ib_qp_type qp_type)
264 {
265 int size = 0;
266
267 switch (qp_type) {
268 case IB_QPT_XRC_INI:
269 size += sizeof(struct mlx5_wqe_xrc_seg);
270 /* fall through */
271 case IB_QPT_RC:
272 size += sizeof(struct mlx5_wqe_ctrl_seg) +
273 max(sizeof(struct mlx5_wqe_atomic_seg) +
274 sizeof(struct mlx5_wqe_raddr_seg),
275 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
276 sizeof(struct mlx5_mkey_seg));
277 break;
278
279 case IB_QPT_XRC_TGT:
280 return 0;
281
282 case IB_QPT_UC:
283 size += sizeof(struct mlx5_wqe_ctrl_seg) +
284 max(sizeof(struct mlx5_wqe_raddr_seg),
285 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
286 sizeof(struct mlx5_mkey_seg));
287 break;
288
289 case IB_QPT_UD:
290 case IB_QPT_SMI:
291 case IB_QPT_GSI:
292 size += sizeof(struct mlx5_wqe_ctrl_seg) +
293 sizeof(struct mlx5_wqe_datagram_seg);
294 break;
295
296 case MLX5_IB_QPT_REG_UMR:
297 size += sizeof(struct mlx5_wqe_ctrl_seg) +
298 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
299 sizeof(struct mlx5_mkey_seg);
300 break;
301
302 default:
303 return -EINVAL;
304 }
305
306 return size;
307 }
308
309 static int calc_send_wqe(struct ib_qp_init_attr *attr)
310 {
311 int inl_size = 0;
312 int size;
313
314 size = sq_overhead(attr->qp_type);
315 if (size < 0)
316 return size;
317
318 if (attr->cap.max_inline_data) {
319 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
320 attr->cap.max_inline_data;
321 }
322
323 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
324 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
325 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
326 return MLX5_SIG_WQE_SIZE;
327 else
328 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
329 }
330
331 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
332 struct mlx5_ib_qp *qp)
333 {
334 int wqe_size;
335 int wq_size;
336
337 if (!attr->cap.max_send_wr)
338 return 0;
339
340 wqe_size = calc_send_wqe(attr);
341 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
342 if (wqe_size < 0)
343 return wqe_size;
344
345 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
346 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
347 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
348 return -EINVAL;
349 }
350
351 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
352 sizeof(struct mlx5_wqe_inline_seg);
353 attr->cap.max_inline_data = qp->max_inline_data;
354
355 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
356 qp->signature_en = true;
357
358 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
359 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
360 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
361 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
362 qp->sq.wqe_cnt,
363 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
364 return -ENOMEM;
365 }
366 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
367 qp->sq.max_gs = attr->cap.max_send_sge;
368 qp->sq.max_post = wq_size / wqe_size;
369 attr->cap.max_send_wr = qp->sq.max_post;
370
371 return wq_size;
372 }
373
374 static int set_user_buf_size(struct mlx5_ib_dev *dev,
375 struct mlx5_ib_qp *qp,
376 struct mlx5_ib_create_qp *ucmd,
377 struct mlx5_ib_qp_base *base,
378 struct ib_qp_init_attr *attr)
379 {
380 int desc_sz = 1 << qp->sq.wqe_shift;
381
382 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
383 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
384 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
385 return -EINVAL;
386 }
387
388 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
389 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
390 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
391 return -EINVAL;
392 }
393
394 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
395
396 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
397 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
398 qp->sq.wqe_cnt,
399 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
400 return -EINVAL;
401 }
402
403 if (attr->qp_type == IB_QPT_RAW_PACKET) {
404 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
405 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
406 } else {
407 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
408 (qp->sq.wqe_cnt << 6);
409 }
410
411 return 0;
412 }
413
414 static int qp_has_rq(struct ib_qp_init_attr *attr)
415 {
416 if (attr->qp_type == IB_QPT_XRC_INI ||
417 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
418 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
419 !attr->cap.max_recv_wr)
420 return 0;
421
422 return 1;
423 }
424
425 static int first_med_uuar(void)
426 {
427 return 1;
428 }
429
430 static int next_uuar(int n)
431 {
432 n++;
433
434 while (((n % 4) & 2))
435 n++;
436
437 return n;
438 }
439
440 static int num_med_uuar(struct mlx5_uuar_info *uuari)
441 {
442 int n;
443
444 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
445 uuari->num_low_latency_uuars - 1;
446
447 return n >= 0 ? n : 0;
448 }
449
450 static int max_uuari(struct mlx5_uuar_info *uuari)
451 {
452 return uuari->num_uars * 4;
453 }
454
455 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
456 {
457 int med;
458 int i;
459 int t;
460
461 med = num_med_uuar(uuari);
462 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
463 t++;
464 if (t == med)
465 return next_uuar(i);
466 }
467
468 return 0;
469 }
470
471 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
472 {
473 int i;
474
475 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
476 if (!test_bit(i, uuari->bitmap)) {
477 set_bit(i, uuari->bitmap);
478 uuari->count[i]++;
479 return i;
480 }
481 }
482
483 return -ENOMEM;
484 }
485
486 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
487 {
488 int minidx = first_med_uuar();
489 int i;
490
491 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
492 if (uuari->count[i] < uuari->count[minidx])
493 minidx = i;
494 }
495
496 uuari->count[minidx]++;
497 return minidx;
498 }
499
500 static int alloc_uuar(struct mlx5_uuar_info *uuari,
501 enum mlx5_ib_latency_class lat)
502 {
503 int uuarn = -EINVAL;
504
505 mutex_lock(&uuari->lock);
506 switch (lat) {
507 case MLX5_IB_LATENCY_CLASS_LOW:
508 uuarn = 0;
509 uuari->count[uuarn]++;
510 break;
511
512 case MLX5_IB_LATENCY_CLASS_MEDIUM:
513 if (uuari->ver < 2)
514 uuarn = -ENOMEM;
515 else
516 uuarn = alloc_med_class_uuar(uuari);
517 break;
518
519 case MLX5_IB_LATENCY_CLASS_HIGH:
520 if (uuari->ver < 2)
521 uuarn = -ENOMEM;
522 else
523 uuarn = alloc_high_class_uuar(uuari);
524 break;
525
526 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
527 uuarn = 2;
528 break;
529 }
530 mutex_unlock(&uuari->lock);
531
532 return uuarn;
533 }
534
535 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
536 {
537 clear_bit(uuarn, uuari->bitmap);
538 --uuari->count[uuarn];
539 }
540
541 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
542 {
543 clear_bit(uuarn, uuari->bitmap);
544 --uuari->count[uuarn];
545 }
546
547 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
548 {
549 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
550 int high_uuar = nuuars - uuari->num_low_latency_uuars;
551
552 mutex_lock(&uuari->lock);
553 if (uuarn == 0) {
554 --uuari->count[uuarn];
555 goto out;
556 }
557
558 if (uuarn < high_uuar) {
559 free_med_class_uuar(uuari, uuarn);
560 goto out;
561 }
562
563 free_high_class_uuar(uuari, uuarn);
564
565 out:
566 mutex_unlock(&uuari->lock);
567 }
568
569 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
570 {
571 switch (state) {
572 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
573 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
574 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
575 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
576 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
577 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
578 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
579 default: return -1;
580 }
581 }
582
583 static int to_mlx5_st(enum ib_qp_type type)
584 {
585 switch (type) {
586 case IB_QPT_RC: return MLX5_QP_ST_RC;
587 case IB_QPT_UC: return MLX5_QP_ST_UC;
588 case IB_QPT_UD: return MLX5_QP_ST_UD;
589 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
590 case IB_QPT_XRC_INI:
591 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
592 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
593 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
594 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
595 case IB_QPT_RAW_PACKET:
596 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
597 case IB_QPT_MAX:
598 default: return -EINVAL;
599 }
600 }
601
602 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
603 {
604 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
605 }
606
607 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
608 struct ib_pd *pd,
609 unsigned long addr, size_t size,
610 struct ib_umem **umem,
611 int *npages, int *page_shift, int *ncont,
612 u32 *offset)
613 {
614 int err;
615
616 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
617 if (IS_ERR(*umem)) {
618 mlx5_ib_dbg(dev, "umem_get failed\n");
619 return PTR_ERR(*umem);
620 }
621
622 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
623
624 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
625 if (err) {
626 mlx5_ib_warn(dev, "bad offset\n");
627 goto err_umem;
628 }
629
630 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
631 addr, size, *npages, *page_shift, *ncont, *offset);
632
633 return 0;
634
635 err_umem:
636 ib_umem_release(*umem);
637 *umem = NULL;
638
639 return err;
640 }
641
642 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
643 struct mlx5_ib_qp *qp, struct ib_udata *udata,
644 struct ib_qp_init_attr *attr,
645 struct mlx5_create_qp_mbox_in **in,
646 struct mlx5_ib_create_qp_resp *resp, int *inlen,
647 struct mlx5_ib_qp_base *base)
648 {
649 struct mlx5_ib_ucontext *context;
650 struct mlx5_ib_create_qp ucmd;
651 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
652 int page_shift = 0;
653 int uar_index;
654 int npages;
655 u32 offset = 0;
656 int uuarn;
657 int ncont = 0;
658 int err;
659
660 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
661 if (err) {
662 mlx5_ib_dbg(dev, "copy failed\n");
663 return err;
664 }
665
666 context = to_mucontext(pd->uobject->context);
667 /*
668 * TBD: should come from the verbs when we have the API
669 */
670 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
671 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
672 uuarn = MLX5_CROSS_CHANNEL_UUAR;
673 else {
674 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
675 if (uuarn < 0) {
676 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
677 mlx5_ib_dbg(dev, "reverting to medium latency\n");
678 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
679 if (uuarn < 0) {
680 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
681 mlx5_ib_dbg(dev, "reverting to high latency\n");
682 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
683 if (uuarn < 0) {
684 mlx5_ib_warn(dev, "uuar allocation failed\n");
685 return uuarn;
686 }
687 }
688 }
689 }
690
691 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
692 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
693
694 qp->rq.offset = 0;
695 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
696 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
697
698 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
699 if (err)
700 goto err_uuar;
701
702 if (ucmd.buf_addr && ubuffer->buf_size) {
703 ubuffer->buf_addr = ucmd.buf_addr;
704 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
705 ubuffer->buf_size,
706 &ubuffer->umem, &npages, &page_shift,
707 &ncont, &offset);
708 if (err)
709 goto err_uuar;
710 } else {
711 ubuffer->umem = NULL;
712 }
713
714 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
715 *in = mlx5_vzalloc(*inlen);
716 if (!*in) {
717 err = -ENOMEM;
718 goto err_umem;
719 }
720 if (ubuffer->umem)
721 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
722 (*in)->pas, 0);
723 (*in)->ctx.log_pg_sz_remote_qpn =
724 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
725 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
726
727 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
728 resp->uuar_index = uuarn;
729 qp->uuarn = uuarn;
730
731 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
732 if (err) {
733 mlx5_ib_dbg(dev, "map failed\n");
734 goto err_free;
735 }
736
737 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
738 if (err) {
739 mlx5_ib_dbg(dev, "copy failed\n");
740 goto err_unmap;
741 }
742 qp->create_type = MLX5_QP_USER;
743
744 return 0;
745
746 err_unmap:
747 mlx5_ib_db_unmap_user(context, &qp->db);
748
749 err_free:
750 kvfree(*in);
751
752 err_umem:
753 if (ubuffer->umem)
754 ib_umem_release(ubuffer->umem);
755
756 err_uuar:
757 free_uuar(&context->uuari, uuarn);
758 return err;
759 }
760
761 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
762 struct mlx5_ib_qp_base *base)
763 {
764 struct mlx5_ib_ucontext *context;
765
766 context = to_mucontext(pd->uobject->context);
767 mlx5_ib_db_unmap_user(context, &qp->db);
768 if (base->ubuffer.umem)
769 ib_umem_release(base->ubuffer.umem);
770 free_uuar(&context->uuari, qp->uuarn);
771 }
772
773 static int create_kernel_qp(struct mlx5_ib_dev *dev,
774 struct ib_qp_init_attr *init_attr,
775 struct mlx5_ib_qp *qp,
776 struct mlx5_create_qp_mbox_in **in, int *inlen,
777 struct mlx5_ib_qp_base *base)
778 {
779 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
780 struct mlx5_uuar_info *uuari;
781 int uar_index;
782 int uuarn;
783 int err;
784
785 uuari = &dev->mdev->priv.uuari;
786 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
787 return -EINVAL;
788
789 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
790 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
791
792 uuarn = alloc_uuar(uuari, lc);
793 if (uuarn < 0) {
794 mlx5_ib_dbg(dev, "\n");
795 return -ENOMEM;
796 }
797
798 qp->bf = &uuari->bfs[uuarn];
799 uar_index = qp->bf->uar->index;
800
801 err = calc_sq_size(dev, init_attr, qp);
802 if (err < 0) {
803 mlx5_ib_dbg(dev, "err %d\n", err);
804 goto err_uuar;
805 }
806
807 qp->rq.offset = 0;
808 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
809 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
810
811 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
812 if (err) {
813 mlx5_ib_dbg(dev, "err %d\n", err);
814 goto err_uuar;
815 }
816
817 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
818 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
819 *in = mlx5_vzalloc(*inlen);
820 if (!*in) {
821 err = -ENOMEM;
822 goto err_buf;
823 }
824 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
825 (*in)->ctx.log_pg_sz_remote_qpn =
826 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
827 /* Set "fast registration enabled" for all kernel QPs */
828 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
829 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
830
831 mlx5_fill_page_array(&qp->buf, (*in)->pas);
832
833 err = mlx5_db_alloc(dev->mdev, &qp->db);
834 if (err) {
835 mlx5_ib_dbg(dev, "err %d\n", err);
836 goto err_free;
837 }
838
839 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
840 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
841 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
842 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
843 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
844
845 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
846 !qp->sq.w_list || !qp->sq.wqe_head) {
847 err = -ENOMEM;
848 goto err_wrid;
849 }
850 qp->create_type = MLX5_QP_KERNEL;
851
852 return 0;
853
854 err_wrid:
855 mlx5_db_free(dev->mdev, &qp->db);
856 kfree(qp->sq.wqe_head);
857 kfree(qp->sq.w_list);
858 kfree(qp->sq.wrid);
859 kfree(qp->sq.wr_data);
860 kfree(qp->rq.wrid);
861
862 err_free:
863 kvfree(*in);
864
865 err_buf:
866 mlx5_buf_free(dev->mdev, &qp->buf);
867
868 err_uuar:
869 free_uuar(&dev->mdev->priv.uuari, uuarn);
870 return err;
871 }
872
873 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
874 {
875 mlx5_db_free(dev->mdev, &qp->db);
876 kfree(qp->sq.wqe_head);
877 kfree(qp->sq.w_list);
878 kfree(qp->sq.wrid);
879 kfree(qp->sq.wr_data);
880 kfree(qp->rq.wrid);
881 mlx5_buf_free(dev->mdev, &qp->buf);
882 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
883 }
884
885 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
886 {
887 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
888 (attr->qp_type == IB_QPT_XRC_INI))
889 return cpu_to_be32(MLX5_SRQ_RQ);
890 else if (!qp->has_rq)
891 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
892 else
893 return cpu_to_be32(MLX5_NON_ZERO_RQ);
894 }
895
896 static int is_connected(enum ib_qp_type qp_type)
897 {
898 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
899 return 1;
900
901 return 0;
902 }
903
904 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
905 struct mlx5_ib_sq *sq, u32 tdn)
906 {
907 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
908 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
909
910 memset(in, 0, sizeof(in));
911
912 MLX5_SET(tisc, tisc, transport_domain, tdn);
913
914 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
915 }
916
917 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
918 struct mlx5_ib_sq *sq)
919 {
920 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
921 }
922
923 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
924 struct mlx5_ib_sq *sq, void *qpin,
925 struct ib_pd *pd)
926 {
927 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
928 __be64 *pas;
929 void *in;
930 void *sqc;
931 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
932 void *wq;
933 int inlen;
934 int err;
935 int page_shift = 0;
936 int npages;
937 int ncont = 0;
938 u32 offset = 0;
939
940 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
941 &sq->ubuffer.umem, &npages, &page_shift,
942 &ncont, &offset);
943 if (err)
944 return err;
945
946 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
947 in = mlx5_vzalloc(inlen);
948 if (!in) {
949 err = -ENOMEM;
950 goto err_umem;
951 }
952
953 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
954 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
955 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
956 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
957 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
958 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
959 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
960
961 wq = MLX5_ADDR_OF(sqc, sqc, wq);
962 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
963 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
964 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
965 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
966 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
967 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
968 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
969 MLX5_SET(wq, wq, page_offset, offset);
970
971 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
972 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
973
974 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
975
976 kvfree(in);
977
978 if (err)
979 goto err_umem;
980
981 return 0;
982
983 err_umem:
984 ib_umem_release(sq->ubuffer.umem);
985 sq->ubuffer.umem = NULL;
986
987 return err;
988 }
989
990 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
991 struct mlx5_ib_sq *sq)
992 {
993 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
994 ib_umem_release(sq->ubuffer.umem);
995 }
996
997 static int get_rq_pas_size(void *qpc)
998 {
999 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1000 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1001 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1002 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1003 u32 po_quanta = 1 << (log_page_size - 6);
1004 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1005 u32 page_size = 1 << log_page_size;
1006 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1007 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1008
1009 return rq_num_pas * sizeof(u64);
1010 }
1011
1012 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1013 struct mlx5_ib_rq *rq, void *qpin)
1014 {
1015 __be64 *pas;
1016 __be64 *qp_pas;
1017 void *in;
1018 void *rqc;
1019 void *wq;
1020 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1021 int inlen;
1022 int err;
1023 u32 rq_pas_size = get_rq_pas_size(qpc);
1024
1025 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1026 in = mlx5_vzalloc(inlen);
1027 if (!in)
1028 return -ENOMEM;
1029
1030 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1031 MLX5_SET(rqc, rqc, vsd, 1);
1032 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1033 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1034 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1035 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1036 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1037
1038 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1039 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1040 MLX5_SET(wq, wq, end_padding_mode,
1041 MLX5_GET(qpc, qpc, end_padding_mode));
1042 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1043 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1044 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1045 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1046 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1047 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1048
1049 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1050 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1051 memcpy(pas, qp_pas, rq_pas_size);
1052
1053 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1054
1055 kvfree(in);
1056
1057 return err;
1058 }
1059
1060 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1061 struct mlx5_ib_rq *rq)
1062 {
1063 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1064 }
1065
1066 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1067 struct mlx5_ib_rq *rq, u32 tdn)
1068 {
1069 u32 *in;
1070 void *tirc;
1071 int inlen;
1072 int err;
1073
1074 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1075 in = mlx5_vzalloc(inlen);
1076 if (!in)
1077 return -ENOMEM;
1078
1079 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1080 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1081 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1082 MLX5_SET(tirc, tirc, transport_domain, tdn);
1083
1084 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1085
1086 kvfree(in);
1087
1088 return err;
1089 }
1090
1091 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1092 struct mlx5_ib_rq *rq)
1093 {
1094 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1095 }
1096
1097 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1098 struct mlx5_create_qp_mbox_in *in,
1099 struct ib_pd *pd)
1100 {
1101 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1102 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1103 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1104 struct ib_uobject *uobj = pd->uobject;
1105 struct ib_ucontext *ucontext = uobj->context;
1106 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1107 int err;
1108 u32 tdn = mucontext->tdn;
1109
1110 if (qp->sq.wqe_cnt) {
1111 err = create_raw_packet_qp_tis(dev, sq, tdn);
1112 if (err)
1113 return err;
1114
1115 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1116 if (err)
1117 goto err_destroy_tis;
1118
1119 sq->base.container_mibqp = qp;
1120 }
1121
1122 if (qp->rq.wqe_cnt) {
1123 err = create_raw_packet_qp_rq(dev, rq, in);
1124 if (err)
1125 goto err_destroy_sq;
1126
1127 rq->base.container_mibqp = qp;
1128
1129 err = create_raw_packet_qp_tir(dev, rq, tdn);
1130 if (err)
1131 goto err_destroy_rq;
1132 }
1133
1134 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1135 rq->base.mqp.qpn;
1136
1137 return 0;
1138
1139 err_destroy_rq:
1140 destroy_raw_packet_qp_rq(dev, rq);
1141 err_destroy_sq:
1142 if (!qp->sq.wqe_cnt)
1143 return err;
1144 destroy_raw_packet_qp_sq(dev, sq);
1145 err_destroy_tis:
1146 destroy_raw_packet_qp_tis(dev, sq);
1147
1148 return err;
1149 }
1150
1151 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1152 struct mlx5_ib_qp *qp)
1153 {
1154 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1155 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1156 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1157
1158 if (qp->rq.wqe_cnt) {
1159 destroy_raw_packet_qp_tir(dev, rq);
1160 destroy_raw_packet_qp_rq(dev, rq);
1161 }
1162
1163 if (qp->sq.wqe_cnt) {
1164 destroy_raw_packet_qp_sq(dev, sq);
1165 destroy_raw_packet_qp_tis(dev, sq);
1166 }
1167 }
1168
1169 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1170 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1171 {
1172 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1173 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1174
1175 sq->sq = &qp->sq;
1176 rq->rq = &qp->rq;
1177 sq->doorbell = &qp->db;
1178 rq->doorbell = &qp->db;
1179 }
1180
1181 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1182 struct ib_qp_init_attr *init_attr,
1183 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1184 {
1185 struct mlx5_ib_resources *devr = &dev->devr;
1186 struct mlx5_core_dev *mdev = dev->mdev;
1187 struct mlx5_ib_qp_base *base;
1188 struct mlx5_ib_create_qp_resp resp;
1189 struct mlx5_create_qp_mbox_in *in;
1190 struct mlx5_ib_create_qp ucmd;
1191 int inlen = sizeof(*in);
1192 int err;
1193 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1194 void *qpc;
1195
1196 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1197 &qp->raw_packet_qp.rq.base :
1198 &qp->trans_qp.base;
1199
1200 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1201 mlx5_ib_odp_create_qp(qp);
1202
1203 mutex_init(&qp->mutex);
1204 spin_lock_init(&qp->sq.lock);
1205 spin_lock_init(&qp->rq.lock);
1206
1207 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1208 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1209 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1210 return -EINVAL;
1211 } else {
1212 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1213 }
1214 }
1215
1216 if (init_attr->create_flags &
1217 (IB_QP_CREATE_CROSS_CHANNEL |
1218 IB_QP_CREATE_MANAGED_SEND |
1219 IB_QP_CREATE_MANAGED_RECV)) {
1220 if (!MLX5_CAP_GEN(mdev, cd)) {
1221 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1222 return -EINVAL;
1223 }
1224 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1225 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1226 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1227 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1228 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1229 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1230 }
1231 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1232 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1233
1234 if (pd && pd->uobject) {
1235 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1236 mlx5_ib_dbg(dev, "copy failed\n");
1237 return -EFAULT;
1238 }
1239
1240 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1241 &ucmd, udata->inlen, &uidx);
1242 if (err)
1243 return err;
1244
1245 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1246 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1247 } else {
1248 qp->wq_sig = !!wq_signature;
1249 }
1250
1251 qp->has_rq = qp_has_rq(init_attr);
1252 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1253 qp, (pd && pd->uobject) ? &ucmd : NULL);
1254 if (err) {
1255 mlx5_ib_dbg(dev, "err %d\n", err);
1256 return err;
1257 }
1258
1259 if (pd) {
1260 if (pd->uobject) {
1261 __u32 max_wqes =
1262 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1263 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1264 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1265 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1266 mlx5_ib_dbg(dev, "invalid rq params\n");
1267 return -EINVAL;
1268 }
1269 if (ucmd.sq_wqe_count > max_wqes) {
1270 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1271 ucmd.sq_wqe_count, max_wqes);
1272 return -EINVAL;
1273 }
1274 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1275 &resp, &inlen, base);
1276 if (err)
1277 mlx5_ib_dbg(dev, "err %d\n", err);
1278 } else {
1279 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1280 base);
1281 if (err)
1282 mlx5_ib_dbg(dev, "err %d\n", err);
1283 }
1284
1285 if (err)
1286 return err;
1287 } else {
1288 in = mlx5_vzalloc(sizeof(*in));
1289 if (!in)
1290 return -ENOMEM;
1291
1292 qp->create_type = MLX5_QP_EMPTY;
1293 }
1294
1295 if (is_sqp(init_attr->qp_type))
1296 qp->port = init_attr->port_num;
1297
1298 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1299 MLX5_QP_PM_MIGRATED << 11);
1300
1301 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1302 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1303 else
1304 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1305
1306 if (qp->wq_sig)
1307 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1308
1309 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1310 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1311
1312 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1313 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1314 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1315 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1316 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1317 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1318
1319 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1320 int rcqe_sz;
1321 int scqe_sz;
1322
1323 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1324 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1325
1326 if (rcqe_sz == 128)
1327 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1328 else
1329 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1330
1331 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1332 if (scqe_sz == 128)
1333 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1334 else
1335 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1336 }
1337 }
1338
1339 if (qp->rq.wqe_cnt) {
1340 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1341 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1342 }
1343
1344 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1345
1346 if (qp->sq.wqe_cnt)
1347 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1348 else
1349 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1350
1351 /* Set default resources */
1352 switch (init_attr->qp_type) {
1353 case IB_QPT_XRC_TGT:
1354 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1355 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1356 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1357 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1358 break;
1359 case IB_QPT_XRC_INI:
1360 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1361 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1362 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1363 break;
1364 default:
1365 if (init_attr->srq) {
1366 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1367 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1368 } else {
1369 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1370 in->ctx.rq_type_srqn |=
1371 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
1372 }
1373 }
1374
1375 if (init_attr->send_cq)
1376 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1377
1378 if (init_attr->recv_cq)
1379 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1380
1381 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1382
1383 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1384 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1385 /* 0xffffff means we ask to work with cqe version 0 */
1386 MLX5_SET(qpc, qpc, user_index, uidx);
1387 }
1388
1389 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1390 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1391 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1392 err = create_raw_packet_qp(dev, qp, in, pd);
1393 } else {
1394 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1395 }
1396
1397 if (err) {
1398 mlx5_ib_dbg(dev, "create qp failed\n");
1399 goto err_create;
1400 }
1401
1402 kvfree(in);
1403
1404 base->container_mibqp = qp;
1405 base->mqp.event = mlx5_ib_qp_event;
1406
1407 return 0;
1408
1409 err_create:
1410 if (qp->create_type == MLX5_QP_USER)
1411 destroy_qp_user(pd, qp, base);
1412 else if (qp->create_type == MLX5_QP_KERNEL)
1413 destroy_qp_kernel(dev, qp);
1414
1415 kvfree(in);
1416 return err;
1417 }
1418
1419 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1420 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1421 {
1422 if (send_cq) {
1423 if (recv_cq) {
1424 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1425 spin_lock_irq(&send_cq->lock);
1426 spin_lock_nested(&recv_cq->lock,
1427 SINGLE_DEPTH_NESTING);
1428 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1429 spin_lock_irq(&send_cq->lock);
1430 __acquire(&recv_cq->lock);
1431 } else {
1432 spin_lock_irq(&recv_cq->lock);
1433 spin_lock_nested(&send_cq->lock,
1434 SINGLE_DEPTH_NESTING);
1435 }
1436 } else {
1437 spin_lock_irq(&send_cq->lock);
1438 __acquire(&recv_cq->lock);
1439 }
1440 } else if (recv_cq) {
1441 spin_lock_irq(&recv_cq->lock);
1442 __acquire(&send_cq->lock);
1443 } else {
1444 __acquire(&send_cq->lock);
1445 __acquire(&recv_cq->lock);
1446 }
1447 }
1448
1449 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1450 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1451 {
1452 if (send_cq) {
1453 if (recv_cq) {
1454 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1455 spin_unlock(&recv_cq->lock);
1456 spin_unlock_irq(&send_cq->lock);
1457 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1458 __release(&recv_cq->lock);
1459 spin_unlock_irq(&send_cq->lock);
1460 } else {
1461 spin_unlock(&send_cq->lock);
1462 spin_unlock_irq(&recv_cq->lock);
1463 }
1464 } else {
1465 __release(&recv_cq->lock);
1466 spin_unlock_irq(&send_cq->lock);
1467 }
1468 } else if (recv_cq) {
1469 __release(&send_cq->lock);
1470 spin_unlock_irq(&recv_cq->lock);
1471 } else {
1472 __release(&recv_cq->lock);
1473 __release(&send_cq->lock);
1474 }
1475 }
1476
1477 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1478 {
1479 return to_mpd(qp->ibqp.pd);
1480 }
1481
1482 static void get_cqs(struct mlx5_ib_qp *qp,
1483 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1484 {
1485 switch (qp->ibqp.qp_type) {
1486 case IB_QPT_XRC_TGT:
1487 *send_cq = NULL;
1488 *recv_cq = NULL;
1489 break;
1490 case MLX5_IB_QPT_REG_UMR:
1491 case IB_QPT_XRC_INI:
1492 *send_cq = to_mcq(qp->ibqp.send_cq);
1493 *recv_cq = NULL;
1494 break;
1495
1496 case IB_QPT_SMI:
1497 case IB_QPT_GSI:
1498 case IB_QPT_RC:
1499 case IB_QPT_UC:
1500 case IB_QPT_UD:
1501 case IB_QPT_RAW_IPV6:
1502 case IB_QPT_RAW_ETHERTYPE:
1503 case IB_QPT_RAW_PACKET:
1504 *send_cq = to_mcq(qp->ibqp.send_cq);
1505 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1506 break;
1507
1508 case IB_QPT_MAX:
1509 default:
1510 *send_cq = NULL;
1511 *recv_cq = NULL;
1512 break;
1513 }
1514 }
1515
1516 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1517 u16 operation);
1518
1519 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1520 {
1521 struct mlx5_ib_cq *send_cq, *recv_cq;
1522 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1523 struct mlx5_modify_qp_mbox_in *in;
1524 int err;
1525
1526 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1527 &qp->raw_packet_qp.rq.base :
1528 &qp->trans_qp.base;
1529
1530 in = kzalloc(sizeof(*in), GFP_KERNEL);
1531 if (!in)
1532 return;
1533
1534 if (qp->state != IB_QPS_RESET) {
1535 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1536 mlx5_ib_qp_disable_pagefaults(qp);
1537 err = mlx5_core_qp_modify(dev->mdev,
1538 MLX5_CMD_OP_2RST_QP, in, 0,
1539 &base->mqp);
1540 } else {
1541 err = modify_raw_packet_qp(dev, qp,
1542 MLX5_CMD_OP_2RST_QP);
1543 }
1544 if (err)
1545 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1546 base->mqp.qpn);
1547 }
1548
1549 get_cqs(qp, &send_cq, &recv_cq);
1550
1551 if (qp->create_type == MLX5_QP_KERNEL) {
1552 mlx5_ib_lock_cqs(send_cq, recv_cq);
1553 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1554 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1555 if (send_cq != recv_cq)
1556 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1557 NULL);
1558 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1559 }
1560
1561 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1562 destroy_raw_packet_qp(dev, qp);
1563 } else {
1564 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1565 if (err)
1566 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1567 base->mqp.qpn);
1568 }
1569
1570 kfree(in);
1571
1572 if (qp->create_type == MLX5_QP_KERNEL)
1573 destroy_qp_kernel(dev, qp);
1574 else if (qp->create_type == MLX5_QP_USER)
1575 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1576 }
1577
1578 static const char *ib_qp_type_str(enum ib_qp_type type)
1579 {
1580 switch (type) {
1581 case IB_QPT_SMI:
1582 return "IB_QPT_SMI";
1583 case IB_QPT_GSI:
1584 return "IB_QPT_GSI";
1585 case IB_QPT_RC:
1586 return "IB_QPT_RC";
1587 case IB_QPT_UC:
1588 return "IB_QPT_UC";
1589 case IB_QPT_UD:
1590 return "IB_QPT_UD";
1591 case IB_QPT_RAW_IPV6:
1592 return "IB_QPT_RAW_IPV6";
1593 case IB_QPT_RAW_ETHERTYPE:
1594 return "IB_QPT_RAW_ETHERTYPE";
1595 case IB_QPT_XRC_INI:
1596 return "IB_QPT_XRC_INI";
1597 case IB_QPT_XRC_TGT:
1598 return "IB_QPT_XRC_TGT";
1599 case IB_QPT_RAW_PACKET:
1600 return "IB_QPT_RAW_PACKET";
1601 case MLX5_IB_QPT_REG_UMR:
1602 return "MLX5_IB_QPT_REG_UMR";
1603 case IB_QPT_MAX:
1604 default:
1605 return "Invalid QP type";
1606 }
1607 }
1608
1609 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1610 struct ib_qp_init_attr *init_attr,
1611 struct ib_udata *udata)
1612 {
1613 struct mlx5_ib_dev *dev;
1614 struct mlx5_ib_qp *qp;
1615 u16 xrcdn = 0;
1616 int err;
1617
1618 if (pd) {
1619 dev = to_mdev(pd->device);
1620
1621 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1622 if (!pd->uobject) {
1623 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1624 return ERR_PTR(-EINVAL);
1625 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1626 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1627 return ERR_PTR(-EINVAL);
1628 }
1629 }
1630 } else {
1631 /* being cautious here */
1632 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1633 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1634 pr_warn("%s: no PD for transport %s\n", __func__,
1635 ib_qp_type_str(init_attr->qp_type));
1636 return ERR_PTR(-EINVAL);
1637 }
1638 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1639 }
1640
1641 switch (init_attr->qp_type) {
1642 case IB_QPT_XRC_TGT:
1643 case IB_QPT_XRC_INI:
1644 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
1645 mlx5_ib_dbg(dev, "XRC not supported\n");
1646 return ERR_PTR(-ENOSYS);
1647 }
1648 init_attr->recv_cq = NULL;
1649 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1650 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1651 init_attr->send_cq = NULL;
1652 }
1653
1654 /* fall through */
1655 case IB_QPT_RAW_PACKET:
1656 case IB_QPT_RC:
1657 case IB_QPT_UC:
1658 case IB_QPT_UD:
1659 case IB_QPT_SMI:
1660 case IB_QPT_GSI:
1661 case MLX5_IB_QPT_REG_UMR:
1662 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1663 if (!qp)
1664 return ERR_PTR(-ENOMEM);
1665
1666 err = create_qp_common(dev, pd, init_attr, udata, qp);
1667 if (err) {
1668 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1669 kfree(qp);
1670 return ERR_PTR(err);
1671 }
1672
1673 if (is_qp0(init_attr->qp_type))
1674 qp->ibqp.qp_num = 0;
1675 else if (is_qp1(init_attr->qp_type))
1676 qp->ibqp.qp_num = 1;
1677 else
1678 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
1679
1680 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1681 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
1682 to_mcq(init_attr->recv_cq)->mcq.cqn,
1683 to_mcq(init_attr->send_cq)->mcq.cqn);
1684
1685 qp->trans_qp.xrcdn = xrcdn;
1686
1687 break;
1688
1689 case IB_QPT_RAW_IPV6:
1690 case IB_QPT_RAW_ETHERTYPE:
1691 case IB_QPT_MAX:
1692 default:
1693 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1694 init_attr->qp_type);
1695 /* Don't support raw QPs */
1696 return ERR_PTR(-EINVAL);
1697 }
1698
1699 return &qp->ibqp;
1700 }
1701
1702 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1703 {
1704 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1705 struct mlx5_ib_qp *mqp = to_mqp(qp);
1706
1707 destroy_qp_common(dev, mqp);
1708
1709 kfree(mqp);
1710
1711 return 0;
1712 }
1713
1714 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1715 int attr_mask)
1716 {
1717 u32 hw_access_flags = 0;
1718 u8 dest_rd_atomic;
1719 u32 access_flags;
1720
1721 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1722 dest_rd_atomic = attr->max_dest_rd_atomic;
1723 else
1724 dest_rd_atomic = qp->trans_qp.resp_depth;
1725
1726 if (attr_mask & IB_QP_ACCESS_FLAGS)
1727 access_flags = attr->qp_access_flags;
1728 else
1729 access_flags = qp->trans_qp.atomic_rd_en;
1730
1731 if (!dest_rd_atomic)
1732 access_flags &= IB_ACCESS_REMOTE_WRITE;
1733
1734 if (access_flags & IB_ACCESS_REMOTE_READ)
1735 hw_access_flags |= MLX5_QP_BIT_RRE;
1736 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1737 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1738 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1739 hw_access_flags |= MLX5_QP_BIT_RWE;
1740
1741 return cpu_to_be32(hw_access_flags);
1742 }
1743
1744 enum {
1745 MLX5_PATH_FLAG_FL = 1 << 0,
1746 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1747 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1748 };
1749
1750 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1751 {
1752 if (rate == IB_RATE_PORT_CURRENT) {
1753 return 0;
1754 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1755 return -EINVAL;
1756 } else {
1757 while (rate != IB_RATE_2_5_GBPS &&
1758 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1759 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
1760 --rate;
1761 }
1762
1763 return rate + MLX5_STAT_RATE_OFFSET;
1764 }
1765
1766 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1767 struct mlx5_ib_sq *sq, u8 sl)
1768 {
1769 void *in;
1770 void *tisc;
1771 int inlen;
1772 int err;
1773
1774 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1775 in = mlx5_vzalloc(inlen);
1776 if (!in)
1777 return -ENOMEM;
1778
1779 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1780
1781 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
1782 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
1783
1784 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
1785
1786 kvfree(in);
1787
1788 return err;
1789 }
1790
1791 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1792 const struct ib_ah_attr *ah,
1793 struct mlx5_qp_path *path, u8 port, int attr_mask,
1794 u32 path_flags, const struct ib_qp_attr *attr)
1795 {
1796 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1797 int err;
1798
1799 if (attr_mask & IB_QP_PKEY_INDEX)
1800 path->pkey_index = attr->pkey_index;
1801
1802 if (ah->ah_flags & IB_AH_GRH) {
1803 if (ah->grh.sgid_index >=
1804 dev->mdev->port_caps[port - 1].gid_table_len) {
1805 pr_err("sgid_index (%u) too large. max is %d\n",
1806 ah->grh.sgid_index,
1807 dev->mdev->port_caps[port - 1].gid_table_len);
1808 return -EINVAL;
1809 }
1810 }
1811
1812 if (ll == IB_LINK_LAYER_ETHERNET) {
1813 if (!(ah->ah_flags & IB_AH_GRH))
1814 return -EINVAL;
1815 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
1816 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
1817 ah->grh.sgid_index);
1818 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
1819 } else {
1820 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1821 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 :
1822 0;
1823 path->rlid = cpu_to_be16(ah->dlid);
1824 path->grh_mlid = ah->src_path_bits & 0x7f;
1825 if (ah->ah_flags & IB_AH_GRH)
1826 path->grh_mlid |= 1 << 7;
1827 path->dci_cfi_prio_sl = ah->sl & 0xf;
1828 }
1829
1830 if (ah->ah_flags & IB_AH_GRH) {
1831 path->mgid_index = ah->grh.sgid_index;
1832 path->hop_limit = ah->grh.hop_limit;
1833 path->tclass_flowlabel =
1834 cpu_to_be32((ah->grh.traffic_class << 20) |
1835 (ah->grh.flow_label));
1836 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1837 }
1838
1839 err = ib_rate_to_mlx5(dev, ah->static_rate);
1840 if (err < 0)
1841 return err;
1842 path->static_rate = err;
1843 path->port = port;
1844
1845 if (attr_mask & IB_QP_TIMEOUT)
1846 path->ackto_lt = attr->timeout << 3;
1847
1848 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
1849 return modify_raw_packet_eth_prio(dev->mdev,
1850 &qp->raw_packet_qp.sq,
1851 ah->sl & 0xf);
1852
1853 return 0;
1854 }
1855
1856 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1857 [MLX5_QP_STATE_INIT] = {
1858 [MLX5_QP_STATE_INIT] = {
1859 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1860 MLX5_QP_OPTPAR_RAE |
1861 MLX5_QP_OPTPAR_RWE |
1862 MLX5_QP_OPTPAR_PKEY_INDEX |
1863 MLX5_QP_OPTPAR_PRI_PORT,
1864 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1865 MLX5_QP_OPTPAR_PKEY_INDEX |
1866 MLX5_QP_OPTPAR_PRI_PORT,
1867 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1868 MLX5_QP_OPTPAR_Q_KEY |
1869 MLX5_QP_OPTPAR_PRI_PORT,
1870 },
1871 [MLX5_QP_STATE_RTR] = {
1872 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1873 MLX5_QP_OPTPAR_RRE |
1874 MLX5_QP_OPTPAR_RAE |
1875 MLX5_QP_OPTPAR_RWE |
1876 MLX5_QP_OPTPAR_PKEY_INDEX,
1877 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1878 MLX5_QP_OPTPAR_RWE |
1879 MLX5_QP_OPTPAR_PKEY_INDEX,
1880 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1881 MLX5_QP_OPTPAR_Q_KEY,
1882 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1883 MLX5_QP_OPTPAR_Q_KEY,
1884 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1885 MLX5_QP_OPTPAR_RRE |
1886 MLX5_QP_OPTPAR_RAE |
1887 MLX5_QP_OPTPAR_RWE |
1888 MLX5_QP_OPTPAR_PKEY_INDEX,
1889 },
1890 },
1891 [MLX5_QP_STATE_RTR] = {
1892 [MLX5_QP_STATE_RTS] = {
1893 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1894 MLX5_QP_OPTPAR_RRE |
1895 MLX5_QP_OPTPAR_RAE |
1896 MLX5_QP_OPTPAR_RWE |
1897 MLX5_QP_OPTPAR_PM_STATE |
1898 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1899 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1900 MLX5_QP_OPTPAR_RWE |
1901 MLX5_QP_OPTPAR_PM_STATE,
1902 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1903 },
1904 },
1905 [MLX5_QP_STATE_RTS] = {
1906 [MLX5_QP_STATE_RTS] = {
1907 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1908 MLX5_QP_OPTPAR_RAE |
1909 MLX5_QP_OPTPAR_RWE |
1910 MLX5_QP_OPTPAR_RNR_TIMEOUT |
1911 MLX5_QP_OPTPAR_PM_STATE |
1912 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1913 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1914 MLX5_QP_OPTPAR_PM_STATE |
1915 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1916 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1917 MLX5_QP_OPTPAR_SRQN |
1918 MLX5_QP_OPTPAR_CQN_RCV,
1919 },
1920 },
1921 [MLX5_QP_STATE_SQER] = {
1922 [MLX5_QP_STATE_RTS] = {
1923 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1924 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1925 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
1926 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1927 MLX5_QP_OPTPAR_RWE |
1928 MLX5_QP_OPTPAR_RAE |
1929 MLX5_QP_OPTPAR_RRE,
1930 },
1931 },
1932 };
1933
1934 static int ib_nr_to_mlx5_nr(int ib_mask)
1935 {
1936 switch (ib_mask) {
1937 case IB_QP_STATE:
1938 return 0;
1939 case IB_QP_CUR_STATE:
1940 return 0;
1941 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1942 return 0;
1943 case IB_QP_ACCESS_FLAGS:
1944 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1945 MLX5_QP_OPTPAR_RAE;
1946 case IB_QP_PKEY_INDEX:
1947 return MLX5_QP_OPTPAR_PKEY_INDEX;
1948 case IB_QP_PORT:
1949 return MLX5_QP_OPTPAR_PRI_PORT;
1950 case IB_QP_QKEY:
1951 return MLX5_QP_OPTPAR_Q_KEY;
1952 case IB_QP_AV:
1953 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1954 MLX5_QP_OPTPAR_PRI_PORT;
1955 case IB_QP_PATH_MTU:
1956 return 0;
1957 case IB_QP_TIMEOUT:
1958 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1959 case IB_QP_RETRY_CNT:
1960 return MLX5_QP_OPTPAR_RETRY_COUNT;
1961 case IB_QP_RNR_RETRY:
1962 return MLX5_QP_OPTPAR_RNR_RETRY;
1963 case IB_QP_RQ_PSN:
1964 return 0;
1965 case IB_QP_MAX_QP_RD_ATOMIC:
1966 return MLX5_QP_OPTPAR_SRA_MAX;
1967 case IB_QP_ALT_PATH:
1968 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1969 case IB_QP_MIN_RNR_TIMER:
1970 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1971 case IB_QP_SQ_PSN:
1972 return 0;
1973 case IB_QP_MAX_DEST_RD_ATOMIC:
1974 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1975 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1976 case IB_QP_PATH_MIG_STATE:
1977 return MLX5_QP_OPTPAR_PM_STATE;
1978 case IB_QP_CAP:
1979 return 0;
1980 case IB_QP_DEST_QPN:
1981 return 0;
1982 }
1983 return 0;
1984 }
1985
1986 static int ib_mask_to_mlx5_opt(int ib_mask)
1987 {
1988 int result = 0;
1989 int i;
1990
1991 for (i = 0; i < 8 * sizeof(int); i++) {
1992 if ((1 << i) & ib_mask)
1993 result |= ib_nr_to_mlx5_nr(1 << i);
1994 }
1995
1996 return result;
1997 }
1998
1999 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2000 struct mlx5_ib_rq *rq, int new_state)
2001 {
2002 void *in;
2003 void *rqc;
2004 int inlen;
2005 int err;
2006
2007 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2008 in = mlx5_vzalloc(inlen);
2009 if (!in)
2010 return -ENOMEM;
2011
2012 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2013
2014 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2015 MLX5_SET(rqc, rqc, state, new_state);
2016
2017 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2018 if (err)
2019 goto out;
2020
2021 rq->state = new_state;
2022
2023 out:
2024 kvfree(in);
2025 return err;
2026 }
2027
2028 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2029 struct mlx5_ib_sq *sq, int new_state)
2030 {
2031 void *in;
2032 void *sqc;
2033 int inlen;
2034 int err;
2035
2036 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2037 in = mlx5_vzalloc(inlen);
2038 if (!in)
2039 return -ENOMEM;
2040
2041 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2042
2043 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2044 MLX5_SET(sqc, sqc, state, new_state);
2045
2046 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2047 if (err)
2048 goto out;
2049
2050 sq->state = new_state;
2051
2052 out:
2053 kvfree(in);
2054 return err;
2055 }
2056
2057 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2058 u16 operation)
2059 {
2060 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2061 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2062 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2063 int rq_state;
2064 int sq_state;
2065 int err;
2066
2067 switch (operation) {
2068 case MLX5_CMD_OP_RST2INIT_QP:
2069 rq_state = MLX5_RQC_STATE_RDY;
2070 sq_state = MLX5_SQC_STATE_RDY;
2071 break;
2072 case MLX5_CMD_OP_2ERR_QP:
2073 rq_state = MLX5_RQC_STATE_ERR;
2074 sq_state = MLX5_SQC_STATE_ERR;
2075 break;
2076 case MLX5_CMD_OP_2RST_QP:
2077 rq_state = MLX5_RQC_STATE_RST;
2078 sq_state = MLX5_SQC_STATE_RST;
2079 break;
2080 case MLX5_CMD_OP_INIT2INIT_QP:
2081 case MLX5_CMD_OP_INIT2RTR_QP:
2082 case MLX5_CMD_OP_RTR2RTS_QP:
2083 case MLX5_CMD_OP_RTS2RTS_QP:
2084 /* Nothing to do here... */
2085 return 0;
2086 default:
2087 WARN_ON(1);
2088 return -EINVAL;
2089 }
2090
2091 if (qp->rq.wqe_cnt) {
2092 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2093 if (err)
2094 return err;
2095 }
2096
2097 if (qp->sq.wqe_cnt)
2098 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2099
2100 return 0;
2101 }
2102
2103 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2104 const struct ib_qp_attr *attr, int attr_mask,
2105 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2106 {
2107 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2108 [MLX5_QP_STATE_RST] = {
2109 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2110 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2111 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2112 },
2113 [MLX5_QP_STATE_INIT] = {
2114 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2115 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2116 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2117 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2118 },
2119 [MLX5_QP_STATE_RTR] = {
2120 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2121 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2122 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2123 },
2124 [MLX5_QP_STATE_RTS] = {
2125 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2126 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2127 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2128 },
2129 [MLX5_QP_STATE_SQD] = {
2130 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2131 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2132 },
2133 [MLX5_QP_STATE_SQER] = {
2134 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2135 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2136 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2137 },
2138 [MLX5_QP_STATE_ERR] = {
2139 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2140 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2141 }
2142 };
2143
2144 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2145 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2146 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2147 struct mlx5_ib_cq *send_cq, *recv_cq;
2148 struct mlx5_qp_context *context;
2149 struct mlx5_modify_qp_mbox_in *in;
2150 struct mlx5_ib_pd *pd;
2151 enum mlx5_qp_state mlx5_cur, mlx5_new;
2152 enum mlx5_qp_optpar optpar;
2153 int sqd_event;
2154 int mlx5_st;
2155 int err;
2156 u16 op;
2157
2158 in = kzalloc(sizeof(*in), GFP_KERNEL);
2159 if (!in)
2160 return -ENOMEM;
2161
2162 context = &in->ctx;
2163 err = to_mlx5_st(ibqp->qp_type);
2164 if (err < 0)
2165 goto out;
2166
2167 context->flags = cpu_to_be32(err << 16);
2168
2169 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2170 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2171 } else {
2172 switch (attr->path_mig_state) {
2173 case IB_MIG_MIGRATED:
2174 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2175 break;
2176 case IB_MIG_REARM:
2177 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2178 break;
2179 case IB_MIG_ARMED:
2180 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2181 break;
2182 }
2183 }
2184
2185 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
2186 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2187 } else if (ibqp->qp_type == IB_QPT_UD ||
2188 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2189 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2190 } else if (attr_mask & IB_QP_PATH_MTU) {
2191 if (attr->path_mtu < IB_MTU_256 ||
2192 attr->path_mtu > IB_MTU_4096) {
2193 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2194 err = -EINVAL;
2195 goto out;
2196 }
2197 context->mtu_msgmax = (attr->path_mtu << 5) |
2198 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2199 }
2200
2201 if (attr_mask & IB_QP_DEST_QPN)
2202 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2203
2204 if (attr_mask & IB_QP_PKEY_INDEX)
2205 context->pri_path.pkey_index = attr->pkey_index;
2206
2207 /* todo implement counter_index functionality */
2208
2209 if (is_sqp(ibqp->qp_type))
2210 context->pri_path.port = qp->port;
2211
2212 if (attr_mask & IB_QP_PORT)
2213 context->pri_path.port = attr->port_num;
2214
2215 if (attr_mask & IB_QP_AV) {
2216 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2217 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2218 attr_mask, 0, attr);
2219 if (err)
2220 goto out;
2221 }
2222
2223 if (attr_mask & IB_QP_TIMEOUT)
2224 context->pri_path.ackto_lt |= attr->timeout << 3;
2225
2226 if (attr_mask & IB_QP_ALT_PATH) {
2227 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2228 &context->alt_path,
2229 attr->alt_port_num, attr_mask, 0, attr);
2230 if (err)
2231 goto out;
2232 }
2233
2234 pd = get_pd(qp);
2235 get_cqs(qp, &send_cq, &recv_cq);
2236
2237 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2238 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2239 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2240 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2241
2242 if (attr_mask & IB_QP_RNR_RETRY)
2243 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2244
2245 if (attr_mask & IB_QP_RETRY_CNT)
2246 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2247
2248 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2249 if (attr->max_rd_atomic)
2250 context->params1 |=
2251 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2252 }
2253
2254 if (attr_mask & IB_QP_SQ_PSN)
2255 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2256
2257 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2258 if (attr->max_dest_rd_atomic)
2259 context->params2 |=
2260 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2261 }
2262
2263 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2264 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2265
2266 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2267 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2268
2269 if (attr_mask & IB_QP_RQ_PSN)
2270 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2271
2272 if (attr_mask & IB_QP_QKEY)
2273 context->qkey = cpu_to_be32(attr->qkey);
2274
2275 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2276 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2277
2278 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2279 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2280 sqd_event = 1;
2281 else
2282 sqd_event = 0;
2283
2284 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2285 context->sq_crq_size |= cpu_to_be16(1 << 4);
2286
2287
2288 mlx5_cur = to_mlx5_state(cur_state);
2289 mlx5_new = to_mlx5_state(new_state);
2290 mlx5_st = to_mlx5_st(ibqp->qp_type);
2291 if (mlx5_st < 0)
2292 goto out;
2293
2294 /* If moving to a reset or error state, we must disable page faults on
2295 * this QP and flush all current page faults. Otherwise a stale page
2296 * fault may attempt to work on this QP after it is reset and moved
2297 * again to RTS, and may cause the driver and the device to get out of
2298 * sync. */
2299 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2300 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2301 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2302 mlx5_ib_qp_disable_pagefaults(qp);
2303
2304 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2305 !optab[mlx5_cur][mlx5_new])
2306 goto out;
2307
2308 op = optab[mlx5_cur][mlx5_new];
2309 optpar = ib_mask_to_mlx5_opt(attr_mask);
2310 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2311 in->optparam = cpu_to_be32(optpar);
2312
2313 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2314 err = modify_raw_packet_qp(dev, qp, op);
2315 else
2316 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2317 &base->mqp);
2318 if (err)
2319 goto out;
2320
2321 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2322 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2323 mlx5_ib_qp_enable_pagefaults(qp);
2324
2325 qp->state = new_state;
2326
2327 if (attr_mask & IB_QP_ACCESS_FLAGS)
2328 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2329 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2330 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2331 if (attr_mask & IB_QP_PORT)
2332 qp->port = attr->port_num;
2333 if (attr_mask & IB_QP_ALT_PATH)
2334 qp->trans_qp.alt_port = attr->alt_port_num;
2335
2336 /*
2337 * If we moved a kernel QP to RESET, clean up all old CQ
2338 * entries and reinitialize the QP.
2339 */
2340 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2341 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2342 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2343 if (send_cq != recv_cq)
2344 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2345
2346 qp->rq.head = 0;
2347 qp->rq.tail = 0;
2348 qp->sq.head = 0;
2349 qp->sq.tail = 0;
2350 qp->sq.cur_post = 0;
2351 qp->sq.last_poll = 0;
2352 qp->db.db[MLX5_RCV_DBR] = 0;
2353 qp->db.db[MLX5_SND_DBR] = 0;
2354 }
2355
2356 out:
2357 kfree(in);
2358 return err;
2359 }
2360
2361 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2362 int attr_mask, struct ib_udata *udata)
2363 {
2364 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2365 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2366 enum ib_qp_state cur_state, new_state;
2367 int err = -EINVAL;
2368 int port;
2369 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2370
2371 mutex_lock(&qp->mutex);
2372
2373 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2374 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2375
2376 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2377 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2378 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2379 }
2380
2381 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
2382 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
2383 ll))
2384 goto out;
2385
2386 if ((attr_mask & IB_QP_PORT) &&
2387 (attr->port_num == 0 ||
2388 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)))
2389 goto out;
2390
2391 if (attr_mask & IB_QP_PKEY_INDEX) {
2392 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2393 if (attr->pkey_index >=
2394 dev->mdev->port_caps[port - 1].pkey_table_len)
2395 goto out;
2396 }
2397
2398 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2399 attr->max_rd_atomic >
2400 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp)))
2401 goto out;
2402
2403 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2404 attr->max_dest_rd_atomic >
2405 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp)))
2406 goto out;
2407
2408 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2409 err = 0;
2410 goto out;
2411 }
2412
2413 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2414
2415 out:
2416 mutex_unlock(&qp->mutex);
2417 return err;
2418 }
2419
2420 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2421 {
2422 struct mlx5_ib_cq *cq;
2423 unsigned cur;
2424
2425 cur = wq->head - wq->tail;
2426 if (likely(cur + nreq < wq->max_post))
2427 return 0;
2428
2429 cq = to_mcq(ib_cq);
2430 spin_lock(&cq->lock);
2431 cur = wq->head - wq->tail;
2432 spin_unlock(&cq->lock);
2433
2434 return cur + nreq >= wq->max_post;
2435 }
2436
2437 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2438 u64 remote_addr, u32 rkey)
2439 {
2440 rseg->raddr = cpu_to_be64(remote_addr);
2441 rseg->rkey = cpu_to_be32(rkey);
2442 rseg->reserved = 0;
2443 }
2444
2445 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2446 struct ib_send_wr *wr)
2447 {
2448 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2449 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2450 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2451 }
2452
2453 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2454 {
2455 dseg->byte_count = cpu_to_be32(sg->length);
2456 dseg->lkey = cpu_to_be32(sg->lkey);
2457 dseg->addr = cpu_to_be64(sg->addr);
2458 }
2459
2460 static __be16 get_klm_octo(int npages)
2461 {
2462 return cpu_to_be16(ALIGN(npages, 8) / 2);
2463 }
2464
2465 static __be64 frwr_mkey_mask(void)
2466 {
2467 u64 result;
2468
2469 result = MLX5_MKEY_MASK_LEN |
2470 MLX5_MKEY_MASK_PAGE_SIZE |
2471 MLX5_MKEY_MASK_START_ADDR |
2472 MLX5_MKEY_MASK_EN_RINVAL |
2473 MLX5_MKEY_MASK_KEY |
2474 MLX5_MKEY_MASK_LR |
2475 MLX5_MKEY_MASK_LW |
2476 MLX5_MKEY_MASK_RR |
2477 MLX5_MKEY_MASK_RW |
2478 MLX5_MKEY_MASK_A |
2479 MLX5_MKEY_MASK_SMALL_FENCE |
2480 MLX5_MKEY_MASK_FREE;
2481
2482 return cpu_to_be64(result);
2483 }
2484
2485 static __be64 sig_mkey_mask(void)
2486 {
2487 u64 result;
2488
2489 result = MLX5_MKEY_MASK_LEN |
2490 MLX5_MKEY_MASK_PAGE_SIZE |
2491 MLX5_MKEY_MASK_START_ADDR |
2492 MLX5_MKEY_MASK_EN_SIGERR |
2493 MLX5_MKEY_MASK_EN_RINVAL |
2494 MLX5_MKEY_MASK_KEY |
2495 MLX5_MKEY_MASK_LR |
2496 MLX5_MKEY_MASK_LW |
2497 MLX5_MKEY_MASK_RR |
2498 MLX5_MKEY_MASK_RW |
2499 MLX5_MKEY_MASK_SMALL_FENCE |
2500 MLX5_MKEY_MASK_FREE |
2501 MLX5_MKEY_MASK_BSF_EN;
2502
2503 return cpu_to_be64(result);
2504 }
2505
2506 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2507 struct mlx5_ib_mr *mr)
2508 {
2509 int ndescs = mr->ndescs;
2510
2511 memset(umr, 0, sizeof(*umr));
2512 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2513 umr->klm_octowords = get_klm_octo(ndescs);
2514 umr->mkey_mask = frwr_mkey_mask();
2515 }
2516
2517 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
2518 {
2519 memset(umr, 0, sizeof(*umr));
2520 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2521 umr->flags = 1 << 7;
2522 }
2523
2524 static __be64 get_umr_reg_mr_mask(void)
2525 {
2526 u64 result;
2527
2528 result = MLX5_MKEY_MASK_LEN |
2529 MLX5_MKEY_MASK_PAGE_SIZE |
2530 MLX5_MKEY_MASK_START_ADDR |
2531 MLX5_MKEY_MASK_PD |
2532 MLX5_MKEY_MASK_LR |
2533 MLX5_MKEY_MASK_LW |
2534 MLX5_MKEY_MASK_KEY |
2535 MLX5_MKEY_MASK_RR |
2536 MLX5_MKEY_MASK_RW |
2537 MLX5_MKEY_MASK_A |
2538 MLX5_MKEY_MASK_FREE;
2539
2540 return cpu_to_be64(result);
2541 }
2542
2543 static __be64 get_umr_unreg_mr_mask(void)
2544 {
2545 u64 result;
2546
2547 result = MLX5_MKEY_MASK_FREE;
2548
2549 return cpu_to_be64(result);
2550 }
2551
2552 static __be64 get_umr_update_mtt_mask(void)
2553 {
2554 u64 result;
2555
2556 result = MLX5_MKEY_MASK_FREE;
2557
2558 return cpu_to_be64(result);
2559 }
2560
2561 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2562 struct ib_send_wr *wr)
2563 {
2564 struct mlx5_umr_wr *umrwr = umr_wr(wr);
2565
2566 memset(umr, 0, sizeof(*umr));
2567
2568 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
2569 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
2570 else
2571 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
2572
2573 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
2574 umr->klm_octowords = get_klm_octo(umrwr->npages);
2575 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
2576 umr->mkey_mask = get_umr_update_mtt_mask();
2577 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
2578 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
2579 } else {
2580 umr->mkey_mask = get_umr_reg_mr_mask();
2581 }
2582 } else {
2583 umr->mkey_mask = get_umr_unreg_mr_mask();
2584 }
2585
2586 if (!wr->num_sge)
2587 umr->flags |= MLX5_UMR_INLINE;
2588 }
2589
2590 static u8 get_umr_flags(int acc)
2591 {
2592 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
2593 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
2594 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
2595 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2596 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
2597 }
2598
2599 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
2600 struct mlx5_ib_mr *mr,
2601 u32 key, int access)
2602 {
2603 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
2604
2605 memset(seg, 0, sizeof(*seg));
2606 seg->flags = get_umr_flags(access) | MLX5_ACCESS_MODE_MTT;
2607 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
2608 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2609 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
2610 seg->len = cpu_to_be64(mr->ibmr.length);
2611 seg->xlt_oct_size = cpu_to_be32(ndescs);
2612 seg->log2_page_size = ilog2(mr->ibmr.page_size);
2613 }
2614
2615 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
2616 {
2617 memset(seg, 0, sizeof(*seg));
2618 seg->status = MLX5_MKEY_STATUS_FREE;
2619 }
2620
2621 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2622 {
2623 struct mlx5_umr_wr *umrwr = umr_wr(wr);
2624
2625 memset(seg, 0, sizeof(*seg));
2626 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
2627 seg->status = MLX5_MKEY_STATUS_FREE;
2628 return;
2629 }
2630
2631 seg->flags = convert_access(umrwr->access_flags);
2632 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
2633 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
2634 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2635 }
2636 seg->len = cpu_to_be64(umrwr->length);
2637 seg->log2_page_size = umrwr->page_shift;
2638 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
2639 mlx5_mkey_variant(umrwr->mkey));
2640 }
2641
2642 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
2643 struct mlx5_ib_mr *mr,
2644 struct mlx5_ib_pd *pd)
2645 {
2646 int bcount = mr->desc_size * mr->ndescs;
2647
2648 dseg->addr = cpu_to_be64(mr->desc_map);
2649 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
2650 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
2651 }
2652
2653 static __be32 send_ieth(struct ib_send_wr *wr)
2654 {
2655 switch (wr->opcode) {
2656 case IB_WR_SEND_WITH_IMM:
2657 case IB_WR_RDMA_WRITE_WITH_IMM:
2658 return wr->ex.imm_data;
2659
2660 case IB_WR_SEND_WITH_INV:
2661 return cpu_to_be32(wr->ex.invalidate_rkey);
2662
2663 default:
2664 return 0;
2665 }
2666 }
2667
2668 static u8 calc_sig(void *wqe, int size)
2669 {
2670 u8 *p = wqe;
2671 u8 res = 0;
2672 int i;
2673
2674 for (i = 0; i < size; i++)
2675 res ^= p[i];
2676
2677 return ~res;
2678 }
2679
2680 static u8 wq_sig(void *wqe)
2681 {
2682 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2683 }
2684
2685 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2686 void *wqe, int *sz)
2687 {
2688 struct mlx5_wqe_inline_seg *seg;
2689 void *qend = qp->sq.qend;
2690 void *addr;
2691 int inl = 0;
2692 int copy;
2693 int len;
2694 int i;
2695
2696 seg = wqe;
2697 wqe += sizeof(*seg);
2698 for (i = 0; i < wr->num_sge; i++) {
2699 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2700 len = wr->sg_list[i].length;
2701 inl += len;
2702
2703 if (unlikely(inl > qp->max_inline_data))
2704 return -ENOMEM;
2705
2706 if (unlikely(wqe + len > qend)) {
2707 copy = qend - wqe;
2708 memcpy(wqe, addr, copy);
2709 addr += copy;
2710 len -= copy;
2711 wqe = mlx5_get_send_wqe(qp, 0);
2712 }
2713 memcpy(wqe, addr, len);
2714 wqe += len;
2715 }
2716
2717 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2718
2719 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2720
2721 return 0;
2722 }
2723
2724 static u16 prot_field_size(enum ib_signature_type type)
2725 {
2726 switch (type) {
2727 case IB_SIG_TYPE_T10_DIF:
2728 return MLX5_DIF_SIZE;
2729 default:
2730 return 0;
2731 }
2732 }
2733
2734 static u8 bs_selector(int block_size)
2735 {
2736 switch (block_size) {
2737 case 512: return 0x1;
2738 case 520: return 0x2;
2739 case 4096: return 0x3;
2740 case 4160: return 0x4;
2741 case 1073741824: return 0x5;
2742 default: return 0;
2743 }
2744 }
2745
2746 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2747 struct mlx5_bsf_inl *inl)
2748 {
2749 /* Valid inline section and allow BSF refresh */
2750 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2751 MLX5_BSF_REFRESH_DIF);
2752 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2753 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
2754 /* repeating block */
2755 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2756 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2757 MLX5_DIF_CRC : MLX5_DIF_IPCS;
2758
2759 if (domain->sig.dif.ref_remap)
2760 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
2761
2762 if (domain->sig.dif.app_escape) {
2763 if (domain->sig.dif.ref_escape)
2764 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2765 else
2766 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
2767 }
2768
2769 inl->dif_app_bitmask_check =
2770 cpu_to_be16(domain->sig.dif.apptag_check_mask);
2771 }
2772
2773 static int mlx5_set_bsf(struct ib_mr *sig_mr,
2774 struct ib_sig_attrs *sig_attrs,
2775 struct mlx5_bsf *bsf, u32 data_size)
2776 {
2777 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2778 struct mlx5_bsf_basic *basic = &bsf->basic;
2779 struct ib_sig_domain *mem = &sig_attrs->mem;
2780 struct ib_sig_domain *wire = &sig_attrs->wire;
2781
2782 memset(bsf, 0, sizeof(*bsf));
2783
2784 /* Basic + Extended + Inline */
2785 basic->bsf_size_sbs = 1 << 7;
2786 /* Input domain check byte mask */
2787 basic->check_byte_mask = sig_attrs->check_mask;
2788 basic->raw_data_size = cpu_to_be32(data_size);
2789
2790 /* Memory domain */
2791 switch (sig_attrs->mem.sig_type) {
2792 case IB_SIG_TYPE_NONE:
2793 break;
2794 case IB_SIG_TYPE_T10_DIF:
2795 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2796 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2797 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2798 break;
2799 default:
2800 return -EINVAL;
2801 }
2802
2803 /* Wire domain */
2804 switch (sig_attrs->wire.sig_type) {
2805 case IB_SIG_TYPE_NONE:
2806 break;
2807 case IB_SIG_TYPE_T10_DIF:
2808 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
2809 mem->sig_type == wire->sig_type) {
2810 /* Same block structure */
2811 basic->bsf_size_sbs |= 1 << 4;
2812 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
2813 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
2814 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
2815 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
2816 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
2817 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
2818 } else
2819 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2820
2821 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
2822 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
2823 break;
2824 default:
2825 return -EINVAL;
2826 }
2827
2828 return 0;
2829 }
2830
2831 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
2832 struct mlx5_ib_qp *qp, void **seg, int *size)
2833 {
2834 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
2835 struct ib_mr *sig_mr = wr->sig_mr;
2836 struct mlx5_bsf *bsf;
2837 u32 data_len = wr->wr.sg_list->length;
2838 u32 data_key = wr->wr.sg_list->lkey;
2839 u64 data_va = wr->wr.sg_list->addr;
2840 int ret;
2841 int wqe_size;
2842
2843 if (!wr->prot ||
2844 (data_key == wr->prot->lkey &&
2845 data_va == wr->prot->addr &&
2846 data_len == wr->prot->length)) {
2847 /**
2848 * Source domain doesn't contain signature information
2849 * or data and protection are interleaved in memory.
2850 * So need construct:
2851 * ------------------
2852 * | data_klm |
2853 * ------------------
2854 * | BSF |
2855 * ------------------
2856 **/
2857 struct mlx5_klm *data_klm = *seg;
2858
2859 data_klm->bcount = cpu_to_be32(data_len);
2860 data_klm->key = cpu_to_be32(data_key);
2861 data_klm->va = cpu_to_be64(data_va);
2862 wqe_size = ALIGN(sizeof(*data_klm), 64);
2863 } else {
2864 /**
2865 * Source domain contains signature information
2866 * So need construct a strided block format:
2867 * ---------------------------
2868 * | stride_block_ctrl |
2869 * ---------------------------
2870 * | data_klm |
2871 * ---------------------------
2872 * | prot_klm |
2873 * ---------------------------
2874 * | BSF |
2875 * ---------------------------
2876 **/
2877 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2878 struct mlx5_stride_block_entry *data_sentry;
2879 struct mlx5_stride_block_entry *prot_sentry;
2880 u32 prot_key = wr->prot->lkey;
2881 u64 prot_va = wr->prot->addr;
2882 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2883 int prot_size;
2884
2885 sblock_ctrl = *seg;
2886 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2887 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2888
2889 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2890 if (!prot_size) {
2891 pr_err("Bad block size given: %u\n", block_size);
2892 return -EINVAL;
2893 }
2894 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
2895 prot_size);
2896 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
2897 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
2898 sblock_ctrl->num_entries = cpu_to_be16(2);
2899
2900 data_sentry->bcount = cpu_to_be16(block_size);
2901 data_sentry->key = cpu_to_be32(data_key);
2902 data_sentry->va = cpu_to_be64(data_va);
2903 data_sentry->stride = cpu_to_be16(block_size);
2904
2905 prot_sentry->bcount = cpu_to_be16(prot_size);
2906 prot_sentry->key = cpu_to_be32(prot_key);
2907 prot_sentry->va = cpu_to_be64(prot_va);
2908 prot_sentry->stride = cpu_to_be16(prot_size);
2909
2910 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
2911 sizeof(*prot_sentry), 64);
2912 }
2913
2914 *seg += wqe_size;
2915 *size += wqe_size / 16;
2916 if (unlikely((*seg == qp->sq.qend)))
2917 *seg = mlx5_get_send_wqe(qp, 0);
2918
2919 bsf = *seg;
2920 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
2921 if (ret)
2922 return -EINVAL;
2923
2924 *seg += sizeof(*bsf);
2925 *size += sizeof(*bsf) / 16;
2926 if (unlikely((*seg == qp->sq.qend)))
2927 *seg = mlx5_get_send_wqe(qp, 0);
2928
2929 return 0;
2930 }
2931
2932 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
2933 struct ib_sig_handover_wr *wr, u32 nelements,
2934 u32 length, u32 pdn)
2935 {
2936 struct ib_mr *sig_mr = wr->sig_mr;
2937 u32 sig_key = sig_mr->rkey;
2938 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
2939
2940 memset(seg, 0, sizeof(*seg));
2941
2942 seg->flags = get_umr_flags(wr->access_flags) |
2943 MLX5_ACCESS_MODE_KLM;
2944 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
2945 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
2946 MLX5_MKEY_BSF_EN | pdn);
2947 seg->len = cpu_to_be64(length);
2948 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
2949 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
2950 }
2951
2952 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2953 u32 nelements)
2954 {
2955 memset(umr, 0, sizeof(*umr));
2956
2957 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
2958 umr->klm_octowords = get_klm_octo(nelements);
2959 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
2960 umr->mkey_mask = sig_mkey_mask();
2961 }
2962
2963
2964 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
2965 void **seg, int *size)
2966 {
2967 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
2968 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
2969 u32 pdn = get_pd(qp)->pdn;
2970 u32 klm_oct_size;
2971 int region_len, ret;
2972
2973 if (unlikely(wr->wr.num_sge != 1) ||
2974 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
2975 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
2976 unlikely(!sig_mr->sig->sig_status_checked))
2977 return -EINVAL;
2978
2979 /* length of the protected region, data + protection */
2980 region_len = wr->wr.sg_list->length;
2981 if (wr->prot &&
2982 (wr->prot->lkey != wr->wr.sg_list->lkey ||
2983 wr->prot->addr != wr->wr.sg_list->addr ||
2984 wr->prot->length != wr->wr.sg_list->length))
2985 region_len += wr->prot->length;
2986
2987 /**
2988 * KLM octoword size - if protection was provided
2989 * then we use strided block format (3 octowords),
2990 * else we use single KLM (1 octoword)
2991 **/
2992 klm_oct_size = wr->prot ? 3 : 1;
2993
2994 set_sig_umr_segment(*seg, klm_oct_size);
2995 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2996 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2997 if (unlikely((*seg == qp->sq.qend)))
2998 *seg = mlx5_get_send_wqe(qp, 0);
2999
3000 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3001 *seg += sizeof(struct mlx5_mkey_seg);
3002 *size += sizeof(struct mlx5_mkey_seg) / 16;
3003 if (unlikely((*seg == qp->sq.qend)))
3004 *seg = mlx5_get_send_wqe(qp, 0);
3005
3006 ret = set_sig_data_segment(wr, qp, seg, size);
3007 if (ret)
3008 return ret;
3009
3010 sig_mr->sig->sig_status_checked = false;
3011 return 0;
3012 }
3013
3014 static int set_psv_wr(struct ib_sig_domain *domain,
3015 u32 psv_idx, void **seg, int *size)
3016 {
3017 struct mlx5_seg_set_psv *psv_seg = *seg;
3018
3019 memset(psv_seg, 0, sizeof(*psv_seg));
3020 psv_seg->psv_num = cpu_to_be32(psv_idx);
3021 switch (domain->sig_type) {
3022 case IB_SIG_TYPE_NONE:
3023 break;
3024 case IB_SIG_TYPE_T10_DIF:
3025 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3026 domain->sig.dif.app_tag);
3027 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3028 break;
3029 default:
3030 pr_err("Bad signature type given.\n");
3031 return 1;
3032 }
3033
3034 *seg += sizeof(*psv_seg);
3035 *size += sizeof(*psv_seg) / 16;
3036
3037 return 0;
3038 }
3039
3040 static int set_reg_wr(struct mlx5_ib_qp *qp,
3041 struct ib_reg_wr *wr,
3042 void **seg, int *size)
3043 {
3044 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3045 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3046
3047 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3048 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3049 "Invalid IB_SEND_INLINE send flag\n");
3050 return -EINVAL;
3051 }
3052
3053 set_reg_umr_seg(*seg, mr);
3054 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3055 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3056 if (unlikely((*seg == qp->sq.qend)))
3057 *seg = mlx5_get_send_wqe(qp, 0);
3058
3059 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3060 *seg += sizeof(struct mlx5_mkey_seg);
3061 *size += sizeof(struct mlx5_mkey_seg) / 16;
3062 if (unlikely((*seg == qp->sq.qend)))
3063 *seg = mlx5_get_send_wqe(qp, 0);
3064
3065 set_reg_data_seg(*seg, mr, pd);
3066 *seg += sizeof(struct mlx5_wqe_data_seg);
3067 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3068
3069 return 0;
3070 }
3071
3072 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3073 {
3074 set_linv_umr_seg(*seg);
3075 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3076 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3077 if (unlikely((*seg == qp->sq.qend)))
3078 *seg = mlx5_get_send_wqe(qp, 0);
3079 set_linv_mkey_seg(*seg);
3080 *seg += sizeof(struct mlx5_mkey_seg);
3081 *size += sizeof(struct mlx5_mkey_seg) / 16;
3082 if (unlikely((*seg == qp->sq.qend)))
3083 *seg = mlx5_get_send_wqe(qp, 0);
3084 }
3085
3086 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3087 {
3088 __be32 *p = NULL;
3089 int tidx = idx;
3090 int i, j;
3091
3092 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3093 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3094 if ((i & 0xf) == 0) {
3095 void *buf = mlx5_get_send_wqe(qp, tidx);
3096 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3097 p = buf;
3098 j = 0;
3099 }
3100 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3101 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3102 be32_to_cpu(p[j + 3]));
3103 }
3104 }
3105
3106 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3107 unsigned bytecnt, struct mlx5_ib_qp *qp)
3108 {
3109 while (bytecnt > 0) {
3110 __iowrite64_copy(dst++, src++, 8);
3111 __iowrite64_copy(dst++, src++, 8);
3112 __iowrite64_copy(dst++, src++, 8);
3113 __iowrite64_copy(dst++, src++, 8);
3114 __iowrite64_copy(dst++, src++, 8);
3115 __iowrite64_copy(dst++, src++, 8);
3116 __iowrite64_copy(dst++, src++, 8);
3117 __iowrite64_copy(dst++, src++, 8);
3118 bytecnt -= 64;
3119 if (unlikely(src == qp->sq.qend))
3120 src = mlx5_get_send_wqe(qp, 0);
3121 }
3122 }
3123
3124 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3125 {
3126 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3127 wr->send_flags & IB_SEND_FENCE))
3128 return MLX5_FENCE_MODE_STRONG_ORDERING;
3129
3130 if (unlikely(fence)) {
3131 if (wr->send_flags & IB_SEND_FENCE)
3132 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3133 else
3134 return fence;
3135
3136 } else {
3137 return 0;
3138 }
3139 }
3140
3141 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3142 struct mlx5_wqe_ctrl_seg **ctrl,
3143 struct ib_send_wr *wr, unsigned *idx,
3144 int *size, int nreq)
3145 {
3146 int err = 0;
3147
3148 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3149 err = -ENOMEM;
3150 return err;
3151 }
3152
3153 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3154 *seg = mlx5_get_send_wqe(qp, *idx);
3155 *ctrl = *seg;
3156 *(uint32_t *)(*seg + 8) = 0;
3157 (*ctrl)->imm = send_ieth(wr);
3158 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3159 (wr->send_flags & IB_SEND_SIGNALED ?
3160 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3161 (wr->send_flags & IB_SEND_SOLICITED ?
3162 MLX5_WQE_CTRL_SOLICITED : 0);
3163
3164 *seg += sizeof(**ctrl);
3165 *size = sizeof(**ctrl) / 16;
3166
3167 return err;
3168 }
3169
3170 static void finish_wqe(struct mlx5_ib_qp *qp,
3171 struct mlx5_wqe_ctrl_seg *ctrl,
3172 u8 size, unsigned idx, u64 wr_id,
3173 int nreq, u8 fence, u8 next_fence,
3174 u32 mlx5_opcode)
3175 {
3176 u8 opmod = 0;
3177
3178 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3179 mlx5_opcode | ((u32)opmod << 24));
3180 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3181 ctrl->fm_ce_se |= fence;
3182 qp->fm_cache = next_fence;
3183 if (unlikely(qp->wq_sig))
3184 ctrl->signature = wq_sig(ctrl);
3185
3186 qp->sq.wrid[idx] = wr_id;
3187 qp->sq.w_list[idx].opcode = mlx5_opcode;
3188 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3189 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3190 qp->sq.w_list[idx].next = qp->sq.cur_post;
3191 }
3192
3193
3194 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3195 struct ib_send_wr **bad_wr)
3196 {
3197 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3198 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3199 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3200 struct mlx5_ib_mr *mr;
3201 struct mlx5_wqe_data_seg *dpseg;
3202 struct mlx5_wqe_xrc_seg *xrc;
3203 struct mlx5_bf *bf = qp->bf;
3204 int uninitialized_var(size);
3205 void *qend = qp->sq.qend;
3206 unsigned long flags;
3207 unsigned idx;
3208 int err = 0;
3209 int inl = 0;
3210 int num_sge;
3211 void *seg;
3212 int nreq;
3213 int i;
3214 u8 next_fence = 0;
3215 u8 fence;
3216
3217 spin_lock_irqsave(&qp->sq.lock, flags);
3218
3219 for (nreq = 0; wr; nreq++, wr = wr->next) {
3220 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3221 mlx5_ib_warn(dev, "\n");
3222 err = -EINVAL;
3223 *bad_wr = wr;
3224 goto out;
3225 }
3226
3227 fence = qp->fm_cache;
3228 num_sge = wr->num_sge;
3229 if (unlikely(num_sge > qp->sq.max_gs)) {
3230 mlx5_ib_warn(dev, "\n");
3231 err = -ENOMEM;
3232 *bad_wr = wr;
3233 goto out;
3234 }
3235
3236 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3237 if (err) {
3238 mlx5_ib_warn(dev, "\n");
3239 err = -ENOMEM;
3240 *bad_wr = wr;
3241 goto out;
3242 }
3243
3244 switch (ibqp->qp_type) {
3245 case IB_QPT_XRC_INI:
3246 xrc = seg;
3247 seg += sizeof(*xrc);
3248 size += sizeof(*xrc) / 16;
3249 /* fall through */
3250 case IB_QPT_RC:
3251 switch (wr->opcode) {
3252 case IB_WR_RDMA_READ:
3253 case IB_WR_RDMA_WRITE:
3254 case IB_WR_RDMA_WRITE_WITH_IMM:
3255 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3256 rdma_wr(wr)->rkey);
3257 seg += sizeof(struct mlx5_wqe_raddr_seg);
3258 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3259 break;
3260
3261 case IB_WR_ATOMIC_CMP_AND_SWP:
3262 case IB_WR_ATOMIC_FETCH_AND_ADD:
3263 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3264 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3265 err = -ENOSYS;
3266 *bad_wr = wr;
3267 goto out;
3268
3269 case IB_WR_LOCAL_INV:
3270 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3271 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3272 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3273 set_linv_wr(qp, &seg, &size);
3274 num_sge = 0;
3275 break;
3276
3277 case IB_WR_REG_MR:
3278 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3279 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3280 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3281 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3282 if (err) {
3283 *bad_wr = wr;
3284 goto out;
3285 }
3286 num_sge = 0;
3287 break;
3288
3289 case IB_WR_REG_SIG_MR:
3290 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3291 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3292
3293 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3294 err = set_sig_umr_wr(wr, qp, &seg, &size);
3295 if (err) {
3296 mlx5_ib_warn(dev, "\n");
3297 *bad_wr = wr;
3298 goto out;
3299 }
3300
3301 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3302 nreq, get_fence(fence, wr),
3303 next_fence, MLX5_OPCODE_UMR);
3304 /*
3305 * SET_PSV WQEs are not signaled and solicited
3306 * on error
3307 */
3308 wr->send_flags &= ~IB_SEND_SIGNALED;
3309 wr->send_flags |= IB_SEND_SOLICITED;
3310 err = begin_wqe(qp, &seg, &ctrl, wr,
3311 &idx, &size, nreq);
3312 if (err) {
3313 mlx5_ib_warn(dev, "\n");
3314 err = -ENOMEM;
3315 *bad_wr = wr;
3316 goto out;
3317 }
3318
3319 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3320 mr->sig->psv_memory.psv_idx, &seg,
3321 &size);
3322 if (err) {
3323 mlx5_ib_warn(dev, "\n");
3324 *bad_wr = wr;
3325 goto out;
3326 }
3327
3328 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3329 nreq, get_fence(fence, wr),
3330 next_fence, MLX5_OPCODE_SET_PSV);
3331 err = begin_wqe(qp, &seg, &ctrl, wr,
3332 &idx, &size, nreq);
3333 if (err) {
3334 mlx5_ib_warn(dev, "\n");
3335 err = -ENOMEM;
3336 *bad_wr = wr;
3337 goto out;
3338 }
3339
3340 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3341 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3342 mr->sig->psv_wire.psv_idx, &seg,
3343 &size);
3344 if (err) {
3345 mlx5_ib_warn(dev, "\n");
3346 *bad_wr = wr;
3347 goto out;
3348 }
3349
3350 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3351 nreq, get_fence(fence, wr),
3352 next_fence, MLX5_OPCODE_SET_PSV);
3353 num_sge = 0;
3354 goto skip_psv;
3355
3356 default:
3357 break;
3358 }
3359 break;
3360
3361 case IB_QPT_UC:
3362 switch (wr->opcode) {
3363 case IB_WR_RDMA_WRITE:
3364 case IB_WR_RDMA_WRITE_WITH_IMM:
3365 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3366 rdma_wr(wr)->rkey);
3367 seg += sizeof(struct mlx5_wqe_raddr_seg);
3368 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3369 break;
3370
3371 default:
3372 break;
3373 }
3374 break;
3375
3376 case IB_QPT_UD:
3377 case IB_QPT_SMI:
3378 case IB_QPT_GSI:
3379 set_datagram_seg(seg, wr);
3380 seg += sizeof(struct mlx5_wqe_datagram_seg);
3381 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3382 if (unlikely((seg == qend)))
3383 seg = mlx5_get_send_wqe(qp, 0);
3384 break;
3385
3386 case MLX5_IB_QPT_REG_UMR:
3387 if (wr->opcode != MLX5_IB_WR_UMR) {
3388 err = -EINVAL;
3389 mlx5_ib_warn(dev, "bad opcode\n");
3390 goto out;
3391 }
3392 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
3393 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
3394 set_reg_umr_segment(seg, wr);
3395 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3396 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3397 if (unlikely((seg == qend)))
3398 seg = mlx5_get_send_wqe(qp, 0);
3399 set_reg_mkey_segment(seg, wr);
3400 seg += sizeof(struct mlx5_mkey_seg);
3401 size += sizeof(struct mlx5_mkey_seg) / 16;
3402 if (unlikely((seg == qend)))
3403 seg = mlx5_get_send_wqe(qp, 0);
3404 break;
3405
3406 default:
3407 break;
3408 }
3409
3410 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3411 int uninitialized_var(sz);
3412
3413 err = set_data_inl_seg(qp, wr, seg, &sz);
3414 if (unlikely(err)) {
3415 mlx5_ib_warn(dev, "\n");
3416 *bad_wr = wr;
3417 goto out;
3418 }
3419 inl = 1;
3420 size += sz;
3421 } else {
3422 dpseg = seg;
3423 for (i = 0; i < num_sge; i++) {
3424 if (unlikely(dpseg == qend)) {
3425 seg = mlx5_get_send_wqe(qp, 0);
3426 dpseg = seg;
3427 }
3428 if (likely(wr->sg_list[i].length)) {
3429 set_data_ptr_seg(dpseg, wr->sg_list + i);
3430 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3431 dpseg++;
3432 }
3433 }
3434 }
3435
3436 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3437 get_fence(fence, wr), next_fence,
3438 mlx5_ib_opcode[wr->opcode]);
3439 skip_psv:
3440 if (0)
3441 dump_wqe(qp, idx, size);
3442 }
3443
3444 out:
3445 if (likely(nreq)) {
3446 qp->sq.head += nreq;
3447
3448 /* Make sure that descriptors are written before
3449 * updating doorbell record and ringing the doorbell
3450 */
3451 wmb();
3452
3453 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
3454
3455 /* Make sure doorbell record is visible to the HCA before
3456 * we hit doorbell */
3457 wmb();
3458
3459 if (bf->need_lock)
3460 spin_lock(&bf->lock);
3461 else
3462 __acquire(&bf->lock);
3463
3464 /* TBD enable WC */
3465 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
3466 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
3467 /* wc_wmb(); */
3468 } else {
3469 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
3470 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
3471 /* Make sure doorbells don't leak out of SQ spinlock
3472 * and reach the HCA out of order.
3473 */
3474 mmiowb();
3475 }
3476 bf->offset ^= bf->buf_size;
3477 if (bf->need_lock)
3478 spin_unlock(&bf->lock);
3479 else
3480 __release(&bf->lock);
3481 }
3482
3483 spin_unlock_irqrestore(&qp->sq.lock, flags);
3484
3485 return err;
3486 }
3487
3488 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
3489 {
3490 sig->signature = calc_sig(sig, size);
3491 }
3492
3493 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3494 struct ib_recv_wr **bad_wr)
3495 {
3496 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3497 struct mlx5_wqe_data_seg *scat;
3498 struct mlx5_rwqe_sig *sig;
3499 unsigned long flags;
3500 int err = 0;
3501 int nreq;
3502 int ind;
3503 int i;
3504
3505 spin_lock_irqsave(&qp->rq.lock, flags);
3506
3507 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3508
3509 for (nreq = 0; wr; nreq++, wr = wr->next) {
3510 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3511 err = -ENOMEM;
3512 *bad_wr = wr;
3513 goto out;
3514 }
3515
3516 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3517 err = -EINVAL;
3518 *bad_wr = wr;
3519 goto out;
3520 }
3521
3522 scat = get_recv_wqe(qp, ind);
3523 if (qp->wq_sig)
3524 scat++;
3525
3526 for (i = 0; i < wr->num_sge; i++)
3527 set_data_ptr_seg(scat + i, wr->sg_list + i);
3528
3529 if (i < qp->rq.max_gs) {
3530 scat[i].byte_count = 0;
3531 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
3532 scat[i].addr = 0;
3533 }
3534
3535 if (qp->wq_sig) {
3536 sig = (struct mlx5_rwqe_sig *)scat;
3537 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
3538 }
3539
3540 qp->rq.wrid[ind] = wr->wr_id;
3541
3542 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3543 }
3544
3545 out:
3546 if (likely(nreq)) {
3547 qp->rq.head += nreq;
3548
3549 /* Make sure that descriptors are written before
3550 * doorbell record.
3551 */
3552 wmb();
3553
3554 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3555 }
3556
3557 spin_unlock_irqrestore(&qp->rq.lock, flags);
3558
3559 return err;
3560 }
3561
3562 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
3563 {
3564 switch (mlx5_state) {
3565 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
3566 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
3567 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
3568 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
3569 case MLX5_QP_STATE_SQ_DRAINING:
3570 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
3571 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
3572 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
3573 default: return -1;
3574 }
3575 }
3576
3577 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
3578 {
3579 switch (mlx5_mig_state) {
3580 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
3581 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
3582 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3583 default: return -1;
3584 }
3585 }
3586
3587 static int to_ib_qp_access_flags(int mlx5_flags)
3588 {
3589 int ib_flags = 0;
3590
3591 if (mlx5_flags & MLX5_QP_BIT_RRE)
3592 ib_flags |= IB_ACCESS_REMOTE_READ;
3593 if (mlx5_flags & MLX5_QP_BIT_RWE)
3594 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3595 if (mlx5_flags & MLX5_QP_BIT_RAE)
3596 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3597
3598 return ib_flags;
3599 }
3600
3601 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3602 struct mlx5_qp_path *path)
3603 {
3604 struct mlx5_core_dev *dev = ibdev->mdev;
3605
3606 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3607 ib_ah_attr->port_num = path->port;
3608
3609 if (ib_ah_attr->port_num == 0 ||
3610 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
3611 return;
3612
3613 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
3614
3615 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3616 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3617 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3618 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3619 if (ib_ah_attr->ah_flags) {
3620 ib_ah_attr->grh.sgid_index = path->mgid_index;
3621 ib_ah_attr->grh.hop_limit = path->hop_limit;
3622 ib_ah_attr->grh.traffic_class =
3623 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3624 ib_ah_attr->grh.flow_label =
3625 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3626 memcpy(ib_ah_attr->grh.dgid.raw,
3627 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3628 }
3629 }
3630
3631 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
3632 struct mlx5_ib_sq *sq,
3633 u8 *sq_state)
3634 {
3635 void *out;
3636 void *sqc;
3637 int inlen;
3638 int err;
3639
3640 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
3641 out = mlx5_vzalloc(inlen);
3642 if (!out)
3643 return -ENOMEM;
3644
3645 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
3646 if (err)
3647 goto out;
3648
3649 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
3650 *sq_state = MLX5_GET(sqc, sqc, state);
3651 sq->state = *sq_state;
3652
3653 out:
3654 kvfree(out);
3655 return err;
3656 }
3657
3658 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
3659 struct mlx5_ib_rq *rq,
3660 u8 *rq_state)
3661 {
3662 void *out;
3663 void *rqc;
3664 int inlen;
3665 int err;
3666
3667 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
3668 out = mlx5_vzalloc(inlen);
3669 if (!out)
3670 return -ENOMEM;
3671
3672 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
3673 if (err)
3674 goto out;
3675
3676 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3677 *rq_state = MLX5_GET(rqc, rqc, state);
3678 rq->state = *rq_state;
3679
3680 out:
3681 kvfree(out);
3682 return err;
3683 }
3684
3685 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
3686 struct mlx5_ib_qp *qp, u8 *qp_state)
3687 {
3688 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
3689 [MLX5_RQC_STATE_RST] = {
3690 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3691 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3692 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
3693 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
3694 },
3695 [MLX5_RQC_STATE_RDY] = {
3696 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3697 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3698 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
3699 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
3700 },
3701 [MLX5_RQC_STATE_ERR] = {
3702 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3703 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3704 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
3705 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
3706 },
3707 [MLX5_RQ_STATE_NA] = {
3708 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3709 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3710 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
3711 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
3712 },
3713 };
3714
3715 *qp_state = sqrq_trans[rq_state][sq_state];
3716
3717 if (*qp_state == MLX5_QP_STATE_BAD) {
3718 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
3719 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
3720 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
3721 return -EINVAL;
3722 }
3723
3724 if (*qp_state == MLX5_QP_STATE)
3725 *qp_state = qp->state;
3726
3727 return 0;
3728 }
3729
3730 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
3731 struct mlx5_ib_qp *qp,
3732 u8 *raw_packet_qp_state)
3733 {
3734 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3735 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3736 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3737 int err;
3738 u8 sq_state = MLX5_SQ_STATE_NA;
3739 u8 rq_state = MLX5_RQ_STATE_NA;
3740
3741 if (qp->sq.wqe_cnt) {
3742 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
3743 if (err)
3744 return err;
3745 }
3746
3747 if (qp->rq.wqe_cnt) {
3748 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
3749 if (err)
3750 return err;
3751 }
3752
3753 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
3754 raw_packet_qp_state);
3755 }
3756
3757 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3758 struct ib_qp_attr *qp_attr)
3759 {
3760 struct mlx5_query_qp_mbox_out *outb;
3761 struct mlx5_qp_context *context;
3762 int mlx5_state;
3763 int err = 0;
3764
3765 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
3766 if (!outb)
3767 return -ENOMEM;
3768
3769 context = &outb->ctx;
3770 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
3771 sizeof(*outb));
3772 if (err)
3773 goto out;
3774
3775 mlx5_state = be32_to_cpu(context->flags) >> 28;
3776
3777 qp->state = to_ib_qp_state(mlx5_state);
3778 qp_attr->path_mtu = context->mtu_msgmax >> 5;
3779 qp_attr->path_mig_state =
3780 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
3781 qp_attr->qkey = be32_to_cpu(context->qkey);
3782 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
3783 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
3784 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
3785 qp_attr->qp_access_flags =
3786 to_ib_qp_access_flags(be32_to_cpu(context->params2));
3787
3788 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3789 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
3790 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
3791 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
3792 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3793 }
3794
3795 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
3796 qp_attr->port_num = context->pri_path.port;
3797
3798 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3799 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
3800
3801 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
3802
3803 qp_attr->max_dest_rd_atomic =
3804 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
3805 qp_attr->min_rnr_timer =
3806 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
3807 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
3808 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
3809 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
3810 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
3811
3812 out:
3813 kfree(outb);
3814 return err;
3815 }
3816
3817 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3818 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3819 {
3820 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3821 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3822 int err = 0;
3823 u8 raw_packet_qp_state;
3824
3825 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3826 /*
3827 * Wait for any outstanding page faults, in case the user frees memory
3828 * based upon this query's result.
3829 */
3830 flush_workqueue(mlx5_ib_page_fault_wq);
3831 #endif
3832
3833 mutex_lock(&qp->mutex);
3834
3835 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3836 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
3837 if (err)
3838 goto out;
3839 qp->state = raw_packet_qp_state;
3840 qp_attr->port_num = 1;
3841 } else {
3842 err = query_qp_attr(dev, qp, qp_attr);
3843 if (err)
3844 goto out;
3845 }
3846
3847 qp_attr->qp_state = qp->state;
3848 qp_attr->cur_qp_state = qp_attr->qp_state;
3849 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3850 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3851
3852 if (!ibqp->uobject) {
3853 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3854 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3855 } else {
3856 qp_attr->cap.max_send_wr = 0;
3857 qp_attr->cap.max_send_sge = 0;
3858 }
3859
3860 /* We don't support inline sends for kernel QPs (yet), and we
3861 * don't know what userspace's value should be.
3862 */
3863 qp_attr->cap.max_inline_data = 0;
3864
3865 qp_init_attr->cap = qp_attr->cap;
3866
3867 qp_init_attr->create_flags = 0;
3868 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3869 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3870
3871 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
3872 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
3873 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
3874 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
3875 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
3876 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
3877
3878 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
3879 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3880
3881 out:
3882 mutex_unlock(&qp->mutex);
3883 return err;
3884 }
3885
3886 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
3887 struct ib_ucontext *context,
3888 struct ib_udata *udata)
3889 {
3890 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3891 struct mlx5_ib_xrcd *xrcd;
3892 int err;
3893
3894 if (!MLX5_CAP_GEN(dev->mdev, xrc))
3895 return ERR_PTR(-ENOSYS);
3896
3897 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
3898 if (!xrcd)
3899 return ERR_PTR(-ENOMEM);
3900
3901 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
3902 if (err) {
3903 kfree(xrcd);
3904 return ERR_PTR(-ENOMEM);
3905 }
3906
3907 return &xrcd->ibxrcd;
3908 }
3909
3910 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
3911 {
3912 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
3913 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
3914 int err;
3915
3916 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
3917 if (err) {
3918 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
3919 return err;
3920 }
3921
3922 kfree(xrcd);
3923
3924 return 0;
3925 }
Linux kernel - Deliverables
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