2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
36 #include <linux/init.h>
37 #include <linux/hardirq.h>
41 #include "mthca_dev.h"
42 #include "mthca_cmd.h"
43 #include "mthca_memfree.h"
46 MTHCA_MAX_DIRECT_CQ_SIZE
= 4 * PAGE_SIZE
50 MTHCA_CQ_ENTRY_SIZE
= 0x20
54 * Must be packed because start is 64 bits but only aligned to 32 bits.
56 struct mthca_cq_context
{
60 u32 error_eqn
; /* Tavor only */
64 u32 last_notified_index
;
65 u32 solicit_producer_index
;
69 u32 ci_db
; /* Arbel only */
70 u32 state_db
; /* Arbel only */
72 } __attribute__((packed
));
74 #define MTHCA_CQ_STATUS_OK ( 0 << 28)
75 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
76 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
77 #define MTHCA_CQ_FLAG_TR ( 1 << 18)
78 #define MTHCA_CQ_FLAG_OI ( 1 << 17)
79 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
80 #define MTHCA_CQ_STATE_ARMED ( 1 << 8)
81 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
82 #define MTHCA_EQ_STATE_FIRED (10 << 8)
85 MTHCA_ERROR_CQE_OPCODE_MASK
= 0xfe
89 SYNDROME_LOCAL_LENGTH_ERR
= 0x01,
90 SYNDROME_LOCAL_QP_OP_ERR
= 0x02,
91 SYNDROME_LOCAL_EEC_OP_ERR
= 0x03,
92 SYNDROME_LOCAL_PROT_ERR
= 0x04,
93 SYNDROME_WR_FLUSH_ERR
= 0x05,
94 SYNDROME_MW_BIND_ERR
= 0x06,
95 SYNDROME_BAD_RESP_ERR
= 0x10,
96 SYNDROME_LOCAL_ACCESS_ERR
= 0x11,
97 SYNDROME_REMOTE_INVAL_REQ_ERR
= 0x12,
98 SYNDROME_REMOTE_ACCESS_ERR
= 0x13,
99 SYNDROME_REMOTE_OP_ERR
= 0x14,
100 SYNDROME_RETRY_EXC_ERR
= 0x15,
101 SYNDROME_RNR_RETRY_EXC_ERR
= 0x16,
102 SYNDROME_LOCAL_RDD_VIOL_ERR
= 0x20,
103 SYNDROME_REMOTE_INVAL_RD_REQ_ERR
= 0x21,
104 SYNDROME_REMOTE_ABORTED_ERR
= 0x22,
105 SYNDROME_INVAL_EECN_ERR
= 0x23,
106 SYNDROME_INVAL_EEC_STATE_ERR
= 0x24
115 u32 imm_etype_pkey_eec
;
124 struct mthca_err_cqe
{
137 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
138 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
140 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
141 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
142 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
143 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
144 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
146 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
147 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
148 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
150 static inline struct mthca_cqe
*get_cqe(struct mthca_cq
*cq
, int entry
)
153 return cq
->queue
.direct
.buf
+ (entry
* MTHCA_CQ_ENTRY_SIZE
);
155 return cq
->queue
.page_list
[entry
* MTHCA_CQ_ENTRY_SIZE
/ PAGE_SIZE
].buf
156 + (entry
* MTHCA_CQ_ENTRY_SIZE
) % PAGE_SIZE
;
159 static inline struct mthca_cqe
*cqe_sw(struct mthca_cq
*cq
, int i
)
161 struct mthca_cqe
*cqe
= get_cqe(cq
, i
);
162 return MTHCA_CQ_ENTRY_OWNER_HW
& cqe
->owner
? NULL
: cqe
;
165 static inline struct mthca_cqe
*next_cqe_sw(struct mthca_cq
*cq
)
167 return cqe_sw(cq
, cq
->cons_index
& cq
->ibcq
.cqe
);
170 static inline void set_cqe_hw(struct mthca_cqe
*cqe
)
172 cqe
->owner
= MTHCA_CQ_ENTRY_OWNER_HW
;
175 static void dump_cqe(struct mthca_dev
*dev
, void *cqe_ptr
)
177 __be32
*cqe
= cqe_ptr
;
179 (void) cqe
; /* avoid warning if mthca_dbg compiled away... */
180 mthca_dbg(dev
, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
181 be32_to_cpu(cqe
[0]), be32_to_cpu(cqe
[1]), be32_to_cpu(cqe
[2]),
182 be32_to_cpu(cqe
[3]), be32_to_cpu(cqe
[4]), be32_to_cpu(cqe
[5]),
183 be32_to_cpu(cqe
[6]), be32_to_cpu(cqe
[7]));
187 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
188 * should be correct before calling update_cons_index().
190 static inline void update_cons_index(struct mthca_dev
*dev
, struct mthca_cq
*cq
,
195 if (mthca_is_memfree(dev
)) {
196 *cq
->set_ci_db
= cpu_to_be32(cq
->cons_index
);
199 doorbell
[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI
| cq
->cqn
);
200 doorbell
[1] = cpu_to_be32(incr
- 1);
202 mthca_write64(doorbell
,
203 dev
->kar
+ MTHCA_CQ_DOORBELL
,
204 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
208 void mthca_cq_event(struct mthca_dev
*dev
, u32 cqn
)
212 cq
= mthca_array_get(&dev
->cq_table
.cq
, cqn
& (dev
->limits
.num_cqs
- 1));
215 mthca_warn(dev
, "Completion event for bogus CQ %08x\n", cqn
);
221 cq
->ibcq
.comp_handler(&cq
->ibcq
, cq
->ibcq
.cq_context
);
224 void mthca_cq_clean(struct mthca_dev
*dev
, u32 cqn
, u32 qpn
)
227 struct mthca_cqe
*cqe
;
231 spin_lock_irq(&dev
->cq_table
.lock
);
232 cq
= mthca_array_get(&dev
->cq_table
.cq
, cqn
& (dev
->limits
.num_cqs
- 1));
234 atomic_inc(&cq
->refcount
);
235 spin_unlock_irq(&dev
->cq_table
.lock
);
240 spin_lock_irq(&cq
->lock
);
243 * First we need to find the current producer index, so we
244 * know where to start cleaning from. It doesn't matter if HW
245 * adds new entries after this loop -- the QP we're worried
246 * about is already in RESET, so the new entries won't come
247 * from our QP and therefore don't need to be checked.
249 for (prod_index
= cq
->cons_index
;
250 cqe_sw(cq
, prod_index
& cq
->ibcq
.cqe
);
252 if (prod_index
== cq
->cons_index
+ cq
->ibcq
.cqe
)
256 mthca_dbg(dev
, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
257 qpn
, cqn
, cq
->cons_index
, prod_index
);
260 * Now sweep backwards through the CQ, removing CQ entries
261 * that match our QP by copying older entries on top of them.
263 while (prod_index
> cq
->cons_index
) {
264 cqe
= get_cqe(cq
, (prod_index
- 1) & cq
->ibcq
.cqe
);
265 if (cqe
->my_qpn
== cpu_to_be32(qpn
))
268 memcpy(get_cqe(cq
, (prod_index
- 1 + nfreed
) &
271 MTHCA_CQ_ENTRY_SIZE
);
277 cq
->cons_index
+= nfreed
;
278 update_cons_index(dev
, cq
, nfreed
);
281 spin_unlock_irq(&cq
->lock
);
282 if (atomic_dec_and_test(&cq
->refcount
))
286 static int handle_error_cqe(struct mthca_dev
*dev
, struct mthca_cq
*cq
,
287 struct mthca_qp
*qp
, int wqe_index
, int is_send
,
288 struct mthca_err_cqe
*cqe
,
289 struct ib_wc
*entry
, int *free_cqe
)
295 if (cqe
->syndrome
== SYNDROME_LOCAL_QP_OP_ERR
) {
296 mthca_dbg(dev
, "local QP operation err "
297 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
298 be32_to_cpu(cqe
->my_qpn
), be32_to_cpu(cqe
->wqe
),
299 cq
->cqn
, cq
->cons_index
);
304 * For completions in error, only work request ID, status (and
305 * freed resource count for RD) have to be set.
307 switch (cqe
->syndrome
) {
308 case SYNDROME_LOCAL_LENGTH_ERR
:
309 entry
->status
= IB_WC_LOC_LEN_ERR
;
311 case SYNDROME_LOCAL_QP_OP_ERR
:
312 entry
->status
= IB_WC_LOC_QP_OP_ERR
;
314 case SYNDROME_LOCAL_EEC_OP_ERR
:
315 entry
->status
= IB_WC_LOC_EEC_OP_ERR
;
317 case SYNDROME_LOCAL_PROT_ERR
:
318 entry
->status
= IB_WC_LOC_PROT_ERR
;
320 case SYNDROME_WR_FLUSH_ERR
:
321 entry
->status
= IB_WC_WR_FLUSH_ERR
;
323 case SYNDROME_MW_BIND_ERR
:
324 entry
->status
= IB_WC_MW_BIND_ERR
;
326 case SYNDROME_BAD_RESP_ERR
:
327 entry
->status
= IB_WC_BAD_RESP_ERR
;
329 case SYNDROME_LOCAL_ACCESS_ERR
:
330 entry
->status
= IB_WC_LOC_ACCESS_ERR
;
332 case SYNDROME_REMOTE_INVAL_REQ_ERR
:
333 entry
->status
= IB_WC_REM_INV_REQ_ERR
;
335 case SYNDROME_REMOTE_ACCESS_ERR
:
336 entry
->status
= IB_WC_REM_ACCESS_ERR
;
338 case SYNDROME_REMOTE_OP_ERR
:
339 entry
->status
= IB_WC_REM_OP_ERR
;
341 case SYNDROME_RETRY_EXC_ERR
:
342 entry
->status
= IB_WC_RETRY_EXC_ERR
;
344 case SYNDROME_RNR_RETRY_EXC_ERR
:
345 entry
->status
= IB_WC_RNR_RETRY_EXC_ERR
;
347 case SYNDROME_LOCAL_RDD_VIOL_ERR
:
348 entry
->status
= IB_WC_LOC_RDD_VIOL_ERR
;
350 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR
:
351 entry
->status
= IB_WC_REM_INV_RD_REQ_ERR
;
353 case SYNDROME_REMOTE_ABORTED_ERR
:
354 entry
->status
= IB_WC_REM_ABORT_ERR
;
356 case SYNDROME_INVAL_EECN_ERR
:
357 entry
->status
= IB_WC_INV_EECN_ERR
;
359 case SYNDROME_INVAL_EEC_STATE_ERR
:
360 entry
->status
= IB_WC_INV_EEC_STATE_ERR
;
363 entry
->status
= IB_WC_GENERAL_ERR
;
367 err
= mthca_free_err_wqe(dev
, qp
, is_send
, wqe_index
, &dbd
, &new_wqe
);
372 * If we're at the end of the WQE chain, or we've used up our
373 * doorbell count, free the CQE. Otherwise just update it for
374 * the next poll operation.
376 if (!(new_wqe
& cpu_to_be32(0x3f)) || (!cqe
->db_cnt
&& dbd
))
379 cqe
->db_cnt
= cpu_to_be16(be16_to_cpu(cqe
->db_cnt
) - dbd
);
381 cqe
->syndrome
= SYNDROME_WR_FLUSH_ERR
;
388 static inline int mthca_poll_one(struct mthca_dev
*dev
,
390 struct mthca_qp
**cur_qp
,
395 struct mthca_cqe
*cqe
;
402 cqe
= next_cqe_sw(cq
);
407 * Make sure we read CQ entry contents after we've checked the
413 mthca_dbg(dev
, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
414 cq
->cqn
, cq
->cons_index
, be32_to_cpu(cqe
->my_qpn
),
415 be32_to_cpu(cqe
->wqe
));
419 is_error
= (cqe
->opcode
& MTHCA_ERROR_CQE_OPCODE_MASK
) ==
420 MTHCA_ERROR_CQE_OPCODE_MASK
;
421 is_send
= is_error
? cqe
->opcode
& 0x01 : cqe
->is_send
& 0x80;
423 if (!*cur_qp
|| be32_to_cpu(cqe
->my_qpn
) != (*cur_qp
)->qpn
) {
425 * We do not have to take the QP table lock here,
426 * because CQs will be locked while QPs are removed
429 *cur_qp
= mthca_array_get(&dev
->qp_table
.qp
,
430 be32_to_cpu(cqe
->my_qpn
) &
431 (dev
->limits
.num_qps
- 1));
433 mthca_warn(dev
, "CQ entry for unknown QP %06x\n",
434 be32_to_cpu(cqe
->my_qpn
) & 0xffffff);
440 entry
->qp_num
= (*cur_qp
)->qpn
;
444 wqe_index
= ((be32_to_cpu(cqe
->wqe
) - (*cur_qp
)->send_wqe_offset
)
446 entry
->wr_id
= (*cur_qp
)->wrid
[wqe_index
+
450 wqe_index
= be32_to_cpu(cqe
->wqe
) >> wq
->wqe_shift
;
451 entry
->wr_id
= (*cur_qp
)->wrid
[wqe_index
];
454 if (wq
->last_comp
< wqe_index
)
455 wq
->tail
+= wqe_index
- wq
->last_comp
;
457 wq
->tail
+= wqe_index
+ wq
->max
- wq
->last_comp
;
459 wq
->last_comp
= wqe_index
;
462 mthca_dbg(dev
, "%s completion for QP %06x, index %d (nr %d)\n",
463 is_send
? "Send" : "Receive",
464 (*cur_qp
)->qpn
, wqe_index
, wq
->max
);
467 err
= handle_error_cqe(dev
, cq
, *cur_qp
, wqe_index
, is_send
,
468 (struct mthca_err_cqe
*) cqe
,
475 switch (cqe
->opcode
) {
476 case MTHCA_OPCODE_RDMA_WRITE
:
477 entry
->opcode
= IB_WC_RDMA_WRITE
;
479 case MTHCA_OPCODE_RDMA_WRITE_IMM
:
480 entry
->opcode
= IB_WC_RDMA_WRITE
;
481 entry
->wc_flags
|= IB_WC_WITH_IMM
;
483 case MTHCA_OPCODE_SEND
:
484 entry
->opcode
= IB_WC_SEND
;
486 case MTHCA_OPCODE_SEND_IMM
:
487 entry
->opcode
= IB_WC_SEND
;
488 entry
->wc_flags
|= IB_WC_WITH_IMM
;
490 case MTHCA_OPCODE_RDMA_READ
:
491 entry
->opcode
= IB_WC_RDMA_READ
;
492 entry
->byte_len
= be32_to_cpu(cqe
->byte_cnt
);
494 case MTHCA_OPCODE_ATOMIC_CS
:
495 entry
->opcode
= IB_WC_COMP_SWAP
;
496 entry
->byte_len
= be32_to_cpu(cqe
->byte_cnt
);
498 case MTHCA_OPCODE_ATOMIC_FA
:
499 entry
->opcode
= IB_WC_FETCH_ADD
;
500 entry
->byte_len
= be32_to_cpu(cqe
->byte_cnt
);
502 case MTHCA_OPCODE_BIND_MW
:
503 entry
->opcode
= IB_WC_BIND_MW
;
506 entry
->opcode
= MTHCA_OPCODE_INVALID
;
510 entry
->byte_len
= be32_to_cpu(cqe
->byte_cnt
);
511 switch (cqe
->opcode
& 0x1f) {
512 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE
:
513 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE
:
514 entry
->wc_flags
= IB_WC_WITH_IMM
;
515 entry
->imm_data
= cqe
->imm_etype_pkey_eec
;
516 entry
->opcode
= IB_WC_RECV
;
518 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE
:
519 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE
:
520 entry
->wc_flags
= IB_WC_WITH_IMM
;
521 entry
->imm_data
= cqe
->imm_etype_pkey_eec
;
522 entry
->opcode
= IB_WC_RECV_RDMA_WITH_IMM
;
526 entry
->opcode
= IB_WC_RECV
;
529 entry
->slid
= be16_to_cpu(cqe
->rlid
);
530 entry
->sl
= be16_to_cpu(cqe
->sl_g_mlpath
) >> 12;
531 entry
->src_qp
= be32_to_cpu(cqe
->rqpn
) & 0xffffff;
532 entry
->dlid_path_bits
= be16_to_cpu(cqe
->sl_g_mlpath
) & 0x7f;
533 entry
->pkey_index
= be32_to_cpu(cqe
->imm_etype_pkey_eec
) >> 16;
534 entry
->wc_flags
|= be16_to_cpu(cqe
->sl_g_mlpath
) & 0x80 ?
538 entry
->status
= IB_WC_SUCCESS
;
541 if (likely(free_cqe
)) {
550 int mthca_poll_cq(struct ib_cq
*ibcq
, int num_entries
,
553 struct mthca_dev
*dev
= to_mdev(ibcq
->device
);
554 struct mthca_cq
*cq
= to_mcq(ibcq
);
555 struct mthca_qp
*qp
= NULL
;
561 spin_lock_irqsave(&cq
->lock
, flags
);
563 for (npolled
= 0; npolled
< num_entries
; ++npolled
) {
564 err
= mthca_poll_one(dev
, cq
, &qp
,
565 &freed
, entry
+ npolled
);
572 update_cons_index(dev
, cq
, freed
);
575 spin_unlock_irqrestore(&cq
->lock
, flags
);
577 return err
== 0 || err
== -EAGAIN
? npolled
: err
;
580 int mthca_tavor_arm_cq(struct ib_cq
*cq
, enum ib_cq_notify notify
)
584 doorbell
[0] = cpu_to_be32((notify
== IB_CQ_SOLICITED
?
585 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL
:
586 MTHCA_TAVOR_CQ_DB_REQ_NOT
) |
588 doorbell
[1] = 0xffffffff;
590 mthca_write64(doorbell
,
591 to_mdev(cq
->device
)->kar
+ MTHCA_CQ_DOORBELL
,
592 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq
->device
)->doorbell_lock
));
597 int mthca_arbel_arm_cq(struct ib_cq
*ibcq
, enum ib_cq_notify notify
)
599 struct mthca_cq
*cq
= to_mcq(ibcq
);
605 ci
= cpu_to_be32(cq
->cons_index
);
608 doorbell
[1] = cpu_to_be32((cq
->cqn
<< 8) | (2 << 5) | (sn
<< 3) |
609 (notify
== IB_CQ_SOLICITED
? 1 : 2));
611 mthca_write_db_rec(doorbell
, cq
->arm_db
);
614 * Make sure that the doorbell record in host memory is
615 * written before ringing the doorbell via PCI MMIO.
619 doorbell
[0] = cpu_to_be32((sn
<< 28) |
620 (notify
== IB_CQ_SOLICITED
?
621 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL
:
622 MTHCA_ARBEL_CQ_DB_REQ_NOT
) |
626 mthca_write64(doorbell
,
627 to_mdev(ibcq
->device
)->kar
+ MTHCA_CQ_DOORBELL
,
628 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq
->device
)->doorbell_lock
));
633 static void mthca_free_cq_buf(struct mthca_dev
*dev
, struct mthca_cq
*cq
)
639 dma_free_coherent(&dev
->pdev
->dev
,
640 (cq
->ibcq
.cqe
+ 1) * MTHCA_CQ_ENTRY_SIZE
,
641 cq
->queue
.direct
.buf
,
642 pci_unmap_addr(&cq
->queue
.direct
,
645 size
= (cq
->ibcq
.cqe
+ 1) * MTHCA_CQ_ENTRY_SIZE
;
646 for (i
= 0; i
< (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
; ++i
)
647 if (cq
->queue
.page_list
[i
].buf
)
648 dma_free_coherent(&dev
->pdev
->dev
, PAGE_SIZE
,
649 cq
->queue
.page_list
[i
].buf
,
650 pci_unmap_addr(&cq
->queue
.page_list
[i
],
653 kfree(cq
->queue
.page_list
);
657 static int mthca_alloc_cq_buf(struct mthca_dev
*dev
, int size
,
662 u64
*dma_list
= NULL
;
666 if (size
<= MTHCA_MAX_DIRECT_CQ_SIZE
) {
669 shift
= get_order(size
) + PAGE_SHIFT
;
671 cq
->queue
.direct
.buf
= dma_alloc_coherent(&dev
->pdev
->dev
,
672 size
, &t
, GFP_KERNEL
);
673 if (!cq
->queue
.direct
.buf
)
676 pci_unmap_addr_set(&cq
->queue
.direct
, mapping
, t
);
678 memset(cq
->queue
.direct
.buf
, 0, size
);
680 while (t
& ((1 << shift
) - 1)) {
685 dma_list
= kmalloc(npages
* sizeof *dma_list
, GFP_KERNEL
);
689 for (i
= 0; i
< npages
; ++i
)
690 dma_list
[i
] = t
+ i
* (1 << shift
);
693 npages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
696 dma_list
= kmalloc(npages
* sizeof *dma_list
, GFP_KERNEL
);
700 cq
->queue
.page_list
= kmalloc(npages
* sizeof *cq
->queue
.page_list
,
702 if (!cq
->queue
.page_list
)
705 for (i
= 0; i
< npages
; ++i
)
706 cq
->queue
.page_list
[i
].buf
= NULL
;
708 for (i
= 0; i
< npages
; ++i
) {
709 cq
->queue
.page_list
[i
].buf
=
710 dma_alloc_coherent(&dev
->pdev
->dev
, PAGE_SIZE
,
712 if (!cq
->queue
.page_list
[i
].buf
)
716 pci_unmap_addr_set(&cq
->queue
.page_list
[i
], mapping
, t
);
718 memset(cq
->queue
.page_list
[i
].buf
, 0, PAGE_SIZE
);
722 err
= mthca_mr_alloc_phys(dev
, dev
->driver_pd
.pd_num
,
723 dma_list
, shift
, npages
,
725 MTHCA_MPT_FLAG_LOCAL_WRITE
|
726 MTHCA_MPT_FLAG_LOCAL_READ
,
736 mthca_free_cq_buf(dev
, cq
);
744 int mthca_init_cq(struct mthca_dev
*dev
, int nent
,
747 int size
= nent
* MTHCA_CQ_ENTRY_SIZE
;
748 struct mthca_mailbox
*mailbox
;
749 struct mthca_cq_context
*cq_context
;
756 cq
->ibcq
.cqe
= nent
- 1;
758 cq
->cqn
= mthca_alloc(&dev
->cq_table
.alloc
);
762 if (mthca_is_memfree(dev
)) {
765 err
= mthca_table_get(dev
, dev
->cq_table
.table
, cq
->cqn
);
771 cq
->set_ci_db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_CQ_SET_CI
,
772 cq
->cqn
, &cq
->set_ci_db
);
773 if (cq
->set_ci_db_index
< 0)
776 cq
->arm_db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_CQ_ARM
,
777 cq
->cqn
, &cq
->arm_db
);
778 if (cq
->arm_db_index
< 0)
782 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
786 cq_context
= mailbox
->buf
;
788 err
= mthca_alloc_cq_buf(dev
, size
, cq
);
790 goto err_out_mailbox
;
792 for (i
= 0; i
< nent
; ++i
)
793 set_cqe_hw(get_cqe(cq
, i
));
795 spin_lock_init(&cq
->lock
);
796 atomic_set(&cq
->refcount
, 1);
797 init_waitqueue_head(&cq
->wait
);
799 memset(cq_context
, 0, sizeof *cq_context
);
800 cq_context
->flags
= cpu_to_be32(MTHCA_CQ_STATUS_OK
|
801 MTHCA_CQ_STATE_DISARMED
|
803 cq_context
->start
= cpu_to_be64(0);
804 cq_context
->logsize_usrpage
= cpu_to_be32((ffs(nent
) - 1) << 24 |
805 dev
->driver_uar
.index
);
806 cq_context
->error_eqn
= cpu_to_be32(dev
->eq_table
.eq
[MTHCA_EQ_ASYNC
].eqn
);
807 cq_context
->comp_eqn
= cpu_to_be32(dev
->eq_table
.eq
[MTHCA_EQ_COMP
].eqn
);
808 cq_context
->pd
= cpu_to_be32(dev
->driver_pd
.pd_num
);
809 cq_context
->lkey
= cpu_to_be32(cq
->mr
.ibmr
.lkey
);
810 cq_context
->cqn
= cpu_to_be32(cq
->cqn
);
812 if (mthca_is_memfree(dev
)) {
813 cq_context
->ci_db
= cpu_to_be32(cq
->set_ci_db_index
);
814 cq_context
->state_db
= cpu_to_be32(cq
->arm_db_index
);
817 err
= mthca_SW2HW_CQ(dev
, mailbox
, cq
->cqn
, &status
);
819 mthca_warn(dev
, "SW2HW_CQ failed (%d)\n", err
);
820 goto err_out_free_mr
;
824 mthca_warn(dev
, "SW2HW_CQ returned status 0x%02x\n",
827 goto err_out_free_mr
;
830 spin_lock_irq(&dev
->cq_table
.lock
);
831 if (mthca_array_set(&dev
->cq_table
.cq
,
832 cq
->cqn
& (dev
->limits
.num_cqs
- 1),
834 spin_unlock_irq(&dev
->cq_table
.lock
);
835 goto err_out_free_mr
;
837 spin_unlock_irq(&dev
->cq_table
.lock
);
841 mthca_free_mailbox(dev
, mailbox
);
846 mthca_free_mr(dev
, &cq
->mr
);
847 mthca_free_cq_buf(dev
, cq
);
850 mthca_free_mailbox(dev
, mailbox
);
853 if (mthca_is_memfree(dev
))
854 mthca_free_db(dev
, MTHCA_DB_TYPE_CQ_ARM
, cq
->arm_db_index
);
857 if (mthca_is_memfree(dev
))
858 mthca_free_db(dev
, MTHCA_DB_TYPE_CQ_SET_CI
, cq
->set_ci_db_index
);
861 mthca_table_put(dev
, dev
->cq_table
.table
, cq
->cqn
);
864 mthca_free(&dev
->cq_table
.alloc
, cq
->cqn
);
869 void mthca_free_cq(struct mthca_dev
*dev
,
872 struct mthca_mailbox
*mailbox
;
878 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
879 if (IS_ERR(mailbox
)) {
880 mthca_warn(dev
, "No memory for mailbox to free CQ.\n");
884 err
= mthca_HW2SW_CQ(dev
, mailbox
, cq
->cqn
, &status
);
886 mthca_warn(dev
, "HW2SW_CQ failed (%d)\n", err
);
888 mthca_warn(dev
, "HW2SW_CQ returned status 0x%02x\n", status
);
891 u32
*ctx
= mailbox
->buf
;
894 printk(KERN_ERR
"context for CQN %x (cons index %x, next sw %d)\n",
895 cq
->cqn
, cq
->cons_index
, !!next_cqe_sw(cq
));
896 for (j
= 0; j
< 16; ++j
)
897 printk(KERN_ERR
"[%2x] %08x\n", j
* 4, be32_to_cpu(ctx
[j
]));
900 spin_lock_irq(&dev
->cq_table
.lock
);
901 mthca_array_clear(&dev
->cq_table
.cq
,
902 cq
->cqn
& (dev
->limits
.num_cqs
- 1));
903 spin_unlock_irq(&dev
->cq_table
.lock
);
905 if (dev
->mthca_flags
& MTHCA_FLAG_MSI_X
)
906 synchronize_irq(dev
->eq_table
.eq
[MTHCA_EQ_COMP
].msi_x_vector
);
908 synchronize_irq(dev
->pdev
->irq
);
910 atomic_dec(&cq
->refcount
);
911 wait_event(cq
->wait
, !atomic_read(&cq
->refcount
));
913 mthca_free_mr(dev
, &cq
->mr
);
914 mthca_free_cq_buf(dev
, cq
);
916 if (mthca_is_memfree(dev
)) {
917 mthca_free_db(dev
, MTHCA_DB_TYPE_CQ_ARM
, cq
->arm_db_index
);
918 mthca_free_db(dev
, MTHCA_DB_TYPE_CQ_SET_CI
, cq
->set_ci_db_index
);
921 mthca_table_put(dev
, dev
->cq_table
.table
, cq
->cqn
);
922 mthca_free(&dev
->cq_table
.alloc
, cq
->cqn
);
923 mthca_free_mailbox(dev
, mailbox
);
926 int __devinit
mthca_init_cq_table(struct mthca_dev
*dev
)
930 spin_lock_init(&dev
->cq_table
.lock
);
932 err
= mthca_alloc_init(&dev
->cq_table
.alloc
,
935 dev
->limits
.reserved_cqs
);
939 err
= mthca_array_init(&dev
->cq_table
.cq
,
940 dev
->limits
.num_cqs
);
942 mthca_alloc_cleanup(&dev
->cq_table
.alloc
);
947 void __devexit
mthca_cleanup_cq_table(struct mthca_dev
*dev
)
949 mthca_array_cleanup(&dev
->cq_table
.cq
, dev
->limits
.num_cqs
);
950 mthca_alloc_cleanup(&dev
->cq_table
.alloc
);