2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
52 MTHCA_MAX_DIRECT_QP_SIZE
= 4 * PAGE_SIZE
,
53 MTHCA_ACK_REQ_FREQ
= 10,
54 MTHCA_FLIGHT_LIMIT
= 9,
55 MTHCA_UD_HEADER_SIZE
= 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE
= 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE
= 16 /* inline data segment chunk */
61 MTHCA_QP_STATE_RST
= 0,
62 MTHCA_QP_STATE_INIT
= 1,
63 MTHCA_QP_STATE_RTR
= 2,
64 MTHCA_QP_STATE_RTS
= 3,
65 MTHCA_QP_STATE_SQE
= 4,
66 MTHCA_QP_STATE_SQD
= 5,
67 MTHCA_QP_STATE_ERR
= 6,
68 MTHCA_QP_STATE_DRAINING
= 7
80 MTHCA_QP_PM_MIGRATED
= 0x3,
81 MTHCA_QP_PM_ARMED
= 0x0,
82 MTHCA_QP_PM_REARM
= 0x1
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE
= 1 << 8,
89 MTHCA_QP_BIT_SRE
= 1 << 15,
90 MTHCA_QP_BIT_SWE
= 1 << 14,
91 MTHCA_QP_BIT_SAE
= 1 << 13,
92 MTHCA_QP_BIT_SIC
= 1 << 4,
93 MTHCA_QP_BIT_SSC
= 1 << 3,
95 MTHCA_QP_BIT_RRE
= 1 << 15,
96 MTHCA_QP_BIT_RWE
= 1 << 14,
97 MTHCA_QP_BIT_RAE
= 1 << 13,
98 MTHCA_QP_BIT_RIC
= 1 << 4,
99 MTHCA_QP_BIT_RSC
= 1 << 3
102 struct mthca_qp_path
{
111 __be32 sl_tclass_flowlabel
;
113 } __attribute__((packed
));
115 struct mthca_qp_context
{
117 __be32 tavor_sched_queue
; /* Reserved on Arbel */
119 u8 rq_size_stride
; /* Reserved on Tavor */
120 u8 sq_size_stride
; /* Reserved on Tavor */
121 u8 rlkey_arbel_sched_queue
; /* Reserved on Tavor */
126 struct mthca_qp_path pri_path
;
127 struct mthca_qp_path alt_path
;
134 __be32 next_send_psn
;
136 __be32 snd_wqe_base_l
; /* Next send WQE on Tavor */
137 __be32 snd_db_index
; /* (debugging only entries) */
138 __be32 last_acked_psn
;
141 __be32 rnr_nextrecvpsn
;
144 __be32 rcv_wqe_base_l
; /* Next recv WQE on Tavor */
145 __be32 rcv_db_index
; /* (debugging only entries) */
149 __be16 rq_wqe_counter
; /* reserved on Tavor */
150 __be16 sq_wqe_counter
; /* reserved on Tavor */
152 } __attribute__((packed
));
154 struct mthca_qp_param
{
155 __be32 opt_param_mask
;
157 struct mthca_qp_context context
;
159 } __attribute__((packed
));
162 MTHCA_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
163 MTHCA_QP_OPTPAR_RRE
= 1 << 1,
164 MTHCA_QP_OPTPAR_RAE
= 1 << 2,
165 MTHCA_QP_OPTPAR_RWE
= 1 << 3,
166 MTHCA_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
167 MTHCA_QP_OPTPAR_Q_KEY
= 1 << 5,
168 MTHCA_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
169 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
170 MTHCA_QP_OPTPAR_SRA_MAX
= 1 << 8,
171 MTHCA_QP_OPTPAR_RRA_MAX
= 1 << 9,
172 MTHCA_QP_OPTPAR_PM_STATE
= 1 << 10,
173 MTHCA_QP_OPTPAR_PORT_NUM
= 1 << 11,
174 MTHCA_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
175 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
= 1 << 13,
176 MTHCA_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
177 MTHCA_QP_OPTPAR_RNR_RETRY
= 1 << 15,
178 MTHCA_QP_OPTPAR_SCHED_QUEUE
= 1 << 16
181 static const u8 mthca_opcode
[] = {
182 [IB_WR_SEND
] = MTHCA_OPCODE_SEND
,
183 [IB_WR_SEND_WITH_IMM
] = MTHCA_OPCODE_SEND_IMM
,
184 [IB_WR_RDMA_WRITE
] = MTHCA_OPCODE_RDMA_WRITE
,
185 [IB_WR_RDMA_WRITE_WITH_IMM
] = MTHCA_OPCODE_RDMA_WRITE_IMM
,
186 [IB_WR_RDMA_READ
] = MTHCA_OPCODE_RDMA_READ
,
187 [IB_WR_ATOMIC_CMP_AND_SWP
] = MTHCA_OPCODE_ATOMIC_CS
,
188 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MTHCA_OPCODE_ATOMIC_FA
,
191 static int is_sqp(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
193 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
194 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 3;
197 static int is_qp0(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
199 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
200 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 1;
203 static void *get_recv_wqe(struct mthca_qp
*qp
, int n
)
206 return qp
->queue
.direct
.buf
+ (n
<< qp
->rq
.wqe_shift
);
208 return qp
->queue
.page_list
[(n
<< qp
->rq
.wqe_shift
) >> PAGE_SHIFT
].buf
+
209 ((n
<< qp
->rq
.wqe_shift
) & (PAGE_SIZE
- 1));
212 static void *get_send_wqe(struct mthca_qp
*qp
, int n
)
215 return qp
->queue
.direct
.buf
+ qp
->send_wqe_offset
+
216 (n
<< qp
->sq
.wqe_shift
);
218 return qp
->queue
.page_list
[(qp
->send_wqe_offset
+
219 (n
<< qp
->sq
.wqe_shift
)) >>
221 ((qp
->send_wqe_offset
+ (n
<< qp
->sq
.wqe_shift
)) &
225 static void mthca_wq_init(struct mthca_wq
*wq
)
227 spin_lock_init(&wq
->lock
);
229 wq
->last_comp
= wq
->max
- 1;
234 void mthca_qp_event(struct mthca_dev
*dev
, u32 qpn
,
235 enum ib_event_type event_type
)
238 struct ib_event event
;
240 spin_lock(&dev
->qp_table
.lock
);
241 qp
= mthca_array_get(&dev
->qp_table
.qp
, qpn
& (dev
->limits
.num_qps
- 1));
243 atomic_inc(&qp
->refcount
);
244 spin_unlock(&dev
->qp_table
.lock
);
247 mthca_warn(dev
, "Async event for bogus QP %08x\n", qpn
);
251 if (event_type
== IB_EVENT_PATH_MIG
)
252 qp
->port
= qp
->alt_port
;
254 event
.device
= &dev
->ib_dev
;
255 event
.event
= event_type
;
256 event
.element
.qp
= &qp
->ibqp
;
257 if (qp
->ibqp
.event_handler
)
258 qp
->ibqp
.event_handler(&event
, qp
->ibqp
.qp_context
);
260 if (atomic_dec_and_test(&qp
->refcount
))
264 static int to_mthca_state(enum ib_qp_state ib_state
)
267 case IB_QPS_RESET
: return MTHCA_QP_STATE_RST
;
268 case IB_QPS_INIT
: return MTHCA_QP_STATE_INIT
;
269 case IB_QPS_RTR
: return MTHCA_QP_STATE_RTR
;
270 case IB_QPS_RTS
: return MTHCA_QP_STATE_RTS
;
271 case IB_QPS_SQD
: return MTHCA_QP_STATE_SQD
;
272 case IB_QPS_SQE
: return MTHCA_QP_STATE_SQE
;
273 case IB_QPS_ERR
: return MTHCA_QP_STATE_ERR
;
278 enum { RC
, UC
, UD
, RD
, RDEE
, MLX
, NUM_TRANS
};
280 static int to_mthca_st(int transport
)
283 case RC
: return MTHCA_QP_ST_RC
;
284 case UC
: return MTHCA_QP_ST_UC
;
285 case UD
: return MTHCA_QP_ST_UD
;
286 case RD
: return MTHCA_QP_ST_RD
;
287 case MLX
: return MTHCA_QP_ST_MLX
;
292 static void store_attrs(struct mthca_sqp
*sqp
, struct ib_qp_attr
*attr
,
295 if (attr_mask
& IB_QP_PKEY_INDEX
)
296 sqp
->pkey_index
= attr
->pkey_index
;
297 if (attr_mask
& IB_QP_QKEY
)
298 sqp
->qkey
= attr
->qkey
;
299 if (attr_mask
& IB_QP_SQ_PSN
)
300 sqp
->send_psn
= attr
->sq_psn
;
303 static void init_port(struct mthca_dev
*dev
, int port
)
307 struct mthca_init_ib_param param
;
309 memset(¶m
, 0, sizeof param
);
311 param
.port_width
= dev
->limits
.port_width_cap
;
312 param
.vl_cap
= dev
->limits
.vl_cap
;
313 param
.mtu_cap
= dev
->limits
.mtu_cap
;
314 param
.gid_cap
= dev
->limits
.gid_table_len
;
315 param
.pkey_cap
= dev
->limits
.pkey_table_len
;
317 err
= mthca_INIT_IB(dev
, ¶m
, port
, &status
);
319 mthca_warn(dev
, "INIT_IB failed, return code %d.\n", err
);
321 mthca_warn(dev
, "INIT_IB returned status %02x.\n", status
);
324 static __be32
get_hw_access_flags(struct mthca_qp
*qp
, struct ib_qp_attr
*attr
,
329 u32 hw_access_flags
= 0;
331 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
332 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
334 dest_rd_atomic
= qp
->resp_depth
;
336 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
337 access_flags
= attr
->qp_access_flags
;
339 access_flags
= qp
->atomic_rd_en
;
342 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
344 if (access_flags
& IB_ACCESS_REMOTE_READ
)
345 hw_access_flags
|= MTHCA_QP_BIT_RRE
;
346 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
347 hw_access_flags
|= MTHCA_QP_BIT_RAE
;
348 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
349 hw_access_flags
|= MTHCA_QP_BIT_RWE
;
351 return cpu_to_be32(hw_access_flags
);
354 static inline enum ib_qp_state
to_ib_qp_state(int mthca_state
)
356 switch (mthca_state
) {
357 case MTHCA_QP_STATE_RST
: return IB_QPS_RESET
;
358 case MTHCA_QP_STATE_INIT
: return IB_QPS_INIT
;
359 case MTHCA_QP_STATE_RTR
: return IB_QPS_RTR
;
360 case MTHCA_QP_STATE_RTS
: return IB_QPS_RTS
;
361 case MTHCA_QP_STATE_DRAINING
:
362 case MTHCA_QP_STATE_SQD
: return IB_QPS_SQD
;
363 case MTHCA_QP_STATE_SQE
: return IB_QPS_SQE
;
364 case MTHCA_QP_STATE_ERR
: return IB_QPS_ERR
;
369 static inline enum ib_mig_state
to_ib_mig_state(int mthca_mig_state
)
371 switch (mthca_mig_state
) {
372 case 0: return IB_MIG_ARMED
;
373 case 1: return IB_MIG_REARM
;
374 case 3: return IB_MIG_MIGRATED
;
379 static int to_ib_qp_access_flags(int mthca_flags
)
383 if (mthca_flags
& MTHCA_QP_BIT_RRE
)
384 ib_flags
|= IB_ACCESS_REMOTE_READ
;
385 if (mthca_flags
& MTHCA_QP_BIT_RWE
)
386 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
387 if (mthca_flags
& MTHCA_QP_BIT_RAE
)
388 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
393 static void to_ib_ah_attr(struct mthca_dev
*dev
, struct ib_ah_attr
*ib_ah_attr
,
394 struct mthca_qp_path
*path
)
396 memset(ib_ah_attr
, 0, sizeof *path
);
397 ib_ah_attr
->port_num
= (be32_to_cpu(path
->port_pkey
) >> 24) & 0x3;
399 if (ib_ah_attr
->port_num
== 0 || ib_ah_attr
->port_num
> dev
->limits
.num_ports
)
402 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
403 ib_ah_attr
->sl
= be32_to_cpu(path
->sl_tclass_flowlabel
) >> 28;
404 ib_ah_attr
->src_path_bits
= path
->g_mylmc
& 0x7f;
405 ib_ah_attr
->static_rate
= mthca_rate_to_ib(dev
,
406 path
->static_rate
& 0x7,
407 ib_ah_attr
->port_num
);
408 ib_ah_attr
->ah_flags
= (path
->g_mylmc
& (1 << 7)) ? IB_AH_GRH
: 0;
409 if (ib_ah_attr
->ah_flags
) {
410 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
& (dev
->limits
.gid_table_len
- 1);
411 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
412 ib_ah_attr
->grh
.traffic_class
=
413 (be32_to_cpu(path
->sl_tclass_flowlabel
) >> 20) & 0xff;
414 ib_ah_attr
->grh
.flow_label
=
415 be32_to_cpu(path
->sl_tclass_flowlabel
) & 0xfffff;
416 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
417 path
->rgid
, sizeof ib_ah_attr
->grh
.dgid
.raw
);
421 int mthca_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
422 struct ib_qp_init_attr
*qp_init_attr
)
424 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
425 struct mthca_qp
*qp
= to_mqp(ibqp
);
427 struct mthca_mailbox
*mailbox
;
428 struct mthca_qp_param
*qp_param
;
429 struct mthca_qp_context
*context
;
433 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
435 return PTR_ERR(mailbox
);
437 err
= mthca_QUERY_QP(dev
, qp
->qpn
, 0, mailbox
, &status
);
441 mthca_warn(dev
, "QUERY_QP returned status %02x\n", status
);
446 qp_param
= mailbox
->buf
;
447 context
= &qp_param
->context
;
448 mthca_state
= be32_to_cpu(context
->flags
) >> 28;
450 qp_attr
->qp_state
= to_ib_qp_state(mthca_state
);
451 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
452 qp_attr
->path_mtu
= context
->mtu_msgmax
>> 5;
453 qp_attr
->path_mig_state
=
454 to_ib_mig_state((be32_to_cpu(context
->flags
) >> 11) & 0x3);
455 qp_attr
->qkey
= be32_to_cpu(context
->qkey
);
456 qp_attr
->rq_psn
= be32_to_cpu(context
->rnr_nextrecvpsn
) & 0xffffff;
457 qp_attr
->sq_psn
= be32_to_cpu(context
->next_send_psn
) & 0xffffff;
458 qp_attr
->dest_qp_num
= be32_to_cpu(context
->remote_qpn
) & 0xffffff;
459 qp_attr
->qp_access_flags
=
460 to_ib_qp_access_flags(be32_to_cpu(context
->params2
));
461 qp_attr
->cap
.max_send_wr
= qp
->sq
.max
;
462 qp_attr
->cap
.max_recv_wr
= qp
->rq
.max
;
463 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
464 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
465 qp_attr
->cap
.max_inline_data
= qp
->max_inline_data
;
467 if (qp
->transport
== RC
|| qp
->transport
== UC
) {
468 to_ib_ah_attr(dev
, &qp_attr
->ah_attr
, &context
->pri_path
);
469 to_ib_ah_attr(dev
, &qp_attr
->alt_ah_attr
, &context
->alt_path
);
472 qp_attr
->pkey_index
= be32_to_cpu(context
->pri_path
.port_pkey
) & 0x7f;
473 qp_attr
->alt_pkey_index
= be32_to_cpu(context
->alt_path
.port_pkey
) & 0x7f;
475 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
476 qp_attr
->sq_draining
= mthca_state
== MTHCA_QP_STATE_DRAINING
;
478 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
->params1
) >> 21) & 0x7);
480 qp_attr
->max_dest_rd_atomic
=
481 1 << ((be32_to_cpu(context
->params2
) >> 21) & 0x7);
482 qp_attr
->min_rnr_timer
=
483 (be32_to_cpu(context
->rnr_nextrecvpsn
) >> 24) & 0x1f;
484 qp_attr
->port_num
= qp_attr
->ah_attr
.port_num
;
485 qp_attr
->timeout
= context
->pri_path
.ackto
>> 3;
486 qp_attr
->retry_cnt
= (be32_to_cpu(context
->params1
) >> 16) & 0x7;
487 qp_attr
->rnr_retry
= context
->pri_path
.rnr_retry
>> 5;
488 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
489 qp_attr
->alt_timeout
= context
->alt_path
.ackto
>> 3;
490 qp_init_attr
->cap
= qp_attr
->cap
;
493 mthca_free_mailbox(dev
, mailbox
);
497 static int mthca_path_set(struct mthca_dev
*dev
, struct ib_ah_attr
*ah
,
498 struct mthca_qp_path
*path
, u8 port
)
500 path
->g_mylmc
= ah
->src_path_bits
& 0x7f;
501 path
->rlid
= cpu_to_be16(ah
->dlid
);
502 path
->static_rate
= mthca_get_rate(dev
, ah
->static_rate
, port
);
504 if (ah
->ah_flags
& IB_AH_GRH
) {
505 if (ah
->grh
.sgid_index
>= dev
->limits
.gid_table_len
) {
506 mthca_dbg(dev
, "sgid_index (%u) too large. max is %d\n",
507 ah
->grh
.sgid_index
, dev
->limits
.gid_table_len
-1);
511 path
->g_mylmc
|= 1 << 7;
512 path
->mgid_index
= ah
->grh
.sgid_index
;
513 path
->hop_limit
= ah
->grh
.hop_limit
;
514 path
->sl_tclass_flowlabel
=
515 cpu_to_be32((ah
->sl
<< 28) |
516 (ah
->grh
.traffic_class
<< 20) |
517 (ah
->grh
.flow_label
));
518 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
520 path
->sl_tclass_flowlabel
= cpu_to_be32(ah
->sl
<< 28);
525 int mthca_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
, int attr_mask
)
527 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
528 struct mthca_qp
*qp
= to_mqp(ibqp
);
529 enum ib_qp_state cur_state
, new_state
;
530 struct mthca_mailbox
*mailbox
;
531 struct mthca_qp_param
*qp_param
;
532 struct mthca_qp_context
*qp_context
;
537 if (attr_mask
& IB_QP_CUR_STATE
) {
538 cur_state
= attr
->cur_qp_state
;
540 spin_lock_irq(&qp
->sq
.lock
);
541 spin_lock(&qp
->rq
.lock
);
542 cur_state
= qp
->state
;
543 spin_unlock(&qp
->rq
.lock
);
544 spin_unlock_irq(&qp
->sq
.lock
);
547 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
549 if (!ib_modify_qp_is_ok(cur_state
, new_state
, ibqp
->qp_type
, attr_mask
)) {
550 mthca_dbg(dev
, "Bad QP transition (transport %d) "
551 "%d->%d with attr 0x%08x\n",
552 qp
->transport
, cur_state
, new_state
,
557 if ((attr_mask
& IB_QP_PKEY_INDEX
) &&
558 attr
->pkey_index
>= dev
->limits
.pkey_table_len
) {
559 mthca_dbg(dev
, "P_Key index (%u) too large. max is %d\n",
560 attr
->pkey_index
, dev
->limits
.pkey_table_len
-1);
564 if ((attr_mask
& IB_QP_PORT
) &&
565 (attr
->port_num
== 0 || attr
->port_num
> dev
->limits
.num_ports
)) {
566 mthca_dbg(dev
, "Port number (%u) is invalid\n", attr
->port_num
);
570 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
571 attr
->max_rd_atomic
> dev
->limits
.max_qp_init_rdma
) {
572 mthca_dbg(dev
, "Max rdma_atomic as initiator %u too large (max is %d)\n",
573 attr
->max_rd_atomic
, dev
->limits
.max_qp_init_rdma
);
577 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
578 attr
->max_dest_rd_atomic
> 1 << dev
->qp_table
.rdb_shift
) {
579 mthca_dbg(dev
, "Max rdma_atomic as responder %u too large (max %d)\n",
580 attr
->max_dest_rd_atomic
, 1 << dev
->qp_table
.rdb_shift
);
584 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
586 return PTR_ERR(mailbox
);
587 qp_param
= mailbox
->buf
;
588 qp_context
= &qp_param
->context
;
589 memset(qp_param
, 0, sizeof *qp_param
);
591 qp_context
->flags
= cpu_to_be32((to_mthca_state(new_state
) << 28) |
592 (to_mthca_st(qp
->transport
) << 16));
593 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_BIT_DE
);
594 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
595 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
597 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE
);
598 switch (attr
->path_mig_state
) {
599 case IB_MIG_MIGRATED
:
600 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
603 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_REARM
<< 11);
606 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_ARMED
<< 11);
611 /* leave tavor_sched_queue as 0 */
613 if (qp
->transport
== MLX
|| qp
->transport
== UD
)
614 qp_context
->mtu_msgmax
= (IB_MTU_2048
<< 5) | 11;
615 else if (attr_mask
& IB_QP_PATH_MTU
) {
616 if (attr
->path_mtu
< IB_MTU_256
|| attr
->path_mtu
> IB_MTU_2048
) {
617 mthca_dbg(dev
, "path MTU (%u) is invalid\n",
621 qp_context
->mtu_msgmax
= (attr
->path_mtu
<< 5) | 31;
624 if (mthca_is_memfree(dev
)) {
626 qp_context
->rq_size_stride
= long_log2(qp
->rq
.max
) << 3;
627 qp_context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
630 qp_context
->sq_size_stride
= long_log2(qp
->sq
.max
) << 3;
631 qp_context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
634 /* leave arbel_sched_queue as 0 */
636 if (qp
->ibqp
.uobject
)
637 qp_context
->usr_page
=
638 cpu_to_be32(to_mucontext(qp
->ibqp
.uobject
->context
)->uar
.index
);
640 qp_context
->usr_page
= cpu_to_be32(dev
->driver_uar
.index
);
641 qp_context
->local_qpn
= cpu_to_be32(qp
->qpn
);
642 if (attr_mask
& IB_QP_DEST_QPN
) {
643 qp_context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
646 if (qp
->transport
== MLX
)
647 qp_context
->pri_path
.port_pkey
|=
648 cpu_to_be32(qp
->port
<< 24);
650 if (attr_mask
& IB_QP_PORT
) {
651 qp_context
->pri_path
.port_pkey
|=
652 cpu_to_be32(attr
->port_num
<< 24);
653 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM
);
657 if (attr_mask
& IB_QP_PKEY_INDEX
) {
658 qp_context
->pri_path
.port_pkey
|=
659 cpu_to_be32(attr
->pkey_index
);
660 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX
);
663 if (attr_mask
& IB_QP_RNR_RETRY
) {
664 qp_context
->alt_path
.rnr_retry
= qp_context
->pri_path
.rnr_retry
=
665 attr
->rnr_retry
<< 5;
666 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY
|
667 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
);
670 if (attr_mask
& IB_QP_AV
) {
671 if (mthca_path_set(dev
, &attr
->ah_attr
, &qp_context
->pri_path
,
672 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
))
675 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
);
678 if (attr_mask
& IB_QP_TIMEOUT
) {
679 qp_context
->pri_path
.ackto
= attr
->timeout
<< 3;
680 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT
);
683 if (attr_mask
& IB_QP_ALT_PATH
) {
684 if (attr
->alt_pkey_index
>= dev
->limits
.pkey_table_len
) {
685 mthca_dbg(dev
, "Alternate P_Key index (%u) too large. max is %d\n",
686 attr
->alt_pkey_index
, dev
->limits
.pkey_table_len
-1);
690 if (attr
->alt_port_num
== 0 || attr
->alt_port_num
> dev
->limits
.num_ports
) {
691 mthca_dbg(dev
, "Alternate port number (%u) is invalid\n",
696 if (mthca_path_set(dev
, &attr
->alt_ah_attr
, &qp_context
->alt_path
,
697 attr
->alt_ah_attr
.port_num
))
700 qp_context
->alt_path
.port_pkey
|= cpu_to_be32(attr
->alt_pkey_index
|
701 attr
->alt_port_num
<< 24);
702 qp_context
->alt_path
.ackto
= attr
->alt_timeout
<< 3;
703 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH
);
707 qp_context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pd_num
);
708 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
709 qp_context
->wqe_lkey
= cpu_to_be32(qp
->mr
.ibmr
.lkey
);
710 qp_context
->params1
= cpu_to_be32((MTHCA_ACK_REQ_FREQ
<< 28) |
711 (MTHCA_FLIGHT_LIMIT
<< 24) |
713 if (qp
->sq_policy
== IB_SIGNAL_ALL_WR
)
714 qp_context
->params1
|= cpu_to_be32(MTHCA_QP_BIT_SSC
);
715 if (attr_mask
& IB_QP_RETRY_CNT
) {
716 qp_context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
717 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT
);
720 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
721 if (attr
->max_rd_atomic
) {
722 qp_context
->params1
|=
723 cpu_to_be32(MTHCA_QP_BIT_SRE
|
725 qp_context
->params1
|=
726 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
728 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX
);
731 if (attr_mask
& IB_QP_SQ_PSN
)
732 qp_context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
733 qp_context
->cqn_snd
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->cqn
);
735 if (mthca_is_memfree(dev
)) {
736 qp_context
->snd_wqe_base_l
= cpu_to_be32(qp
->send_wqe_offset
);
737 qp_context
->snd_db_index
= cpu_to_be32(qp
->sq
.db_index
);
740 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
741 if (attr
->max_dest_rd_atomic
)
742 qp_context
->params2
|=
743 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
745 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX
);
748 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
)) {
749 qp_context
->params2
|= get_hw_access_flags(qp
, attr
, attr_mask
);
750 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
751 MTHCA_QP_OPTPAR_RRE
|
752 MTHCA_QP_OPTPAR_RAE
);
755 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RSC
);
758 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RIC
);
760 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
761 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
762 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT
);
764 if (attr_mask
& IB_QP_RQ_PSN
)
765 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
767 qp_context
->ra_buff_indx
=
768 cpu_to_be32(dev
->qp_table
.rdb_base
+
769 ((qp
->qpn
& (dev
->limits
.num_qps
- 1)) * MTHCA_RDB_ENTRY_SIZE
<<
770 dev
->qp_table
.rdb_shift
));
772 qp_context
->cqn_rcv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->cqn
);
774 if (mthca_is_memfree(dev
))
775 qp_context
->rcv_db_index
= cpu_to_be32(qp
->rq
.db_index
);
777 if (attr_mask
& IB_QP_QKEY
) {
778 qp_context
->qkey
= cpu_to_be32(attr
->qkey
);
779 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY
);
783 qp_context
->srqn
= cpu_to_be32(1 << 24 |
784 to_msrq(ibqp
->srq
)->srqn
);
786 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
787 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&&
788 attr
->en_sqd_async_notify
)
791 err
= mthca_MODIFY_QP(dev
, cur_state
, new_state
, qp
->qpn
, 0,
792 mailbox
, sqd_event
, &status
);
796 mthca_warn(dev
, "modify QP %d->%d returned status %02x.\n",
797 cur_state
, new_state
, status
);
802 qp
->state
= new_state
;
803 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
804 qp
->atomic_rd_en
= attr
->qp_access_flags
;
805 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
806 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
807 if (attr_mask
& IB_QP_PORT
)
808 qp
->port
= attr
->port_num
;
809 if (attr_mask
& IB_QP_ALT_PATH
)
810 qp
->alt_port
= attr
->alt_port_num
;
813 store_attrs(to_msqp(qp
), attr
, attr_mask
);
816 * If we moved QP0 to RTR, bring the IB link up; if we moved
817 * QP0 to RESET or ERROR, bring the link back down.
819 if (is_qp0(dev
, qp
)) {
820 if (cur_state
!= IB_QPS_RTR
&&
821 new_state
== IB_QPS_RTR
)
822 init_port(dev
, qp
->port
);
824 if (cur_state
!= IB_QPS_RESET
&&
825 cur_state
!= IB_QPS_ERR
&&
826 (new_state
== IB_QPS_RESET
||
827 new_state
== IB_QPS_ERR
))
828 mthca_CLOSE_IB(dev
, qp
->port
, &status
);
832 * If we moved a kernel QP to RESET, clean up all old CQ
833 * entries and reinitialize the QP.
835 if (new_state
== IB_QPS_RESET
&& !qp
->ibqp
.uobject
) {
836 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
837 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
838 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
839 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
840 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
842 mthca_wq_init(&qp
->sq
);
843 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
845 mthca_wq_init(&qp
->rq
);
846 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
848 if (mthca_is_memfree(dev
)) {
855 mthca_free_mailbox(dev
, mailbox
);
859 static int mthca_max_data_size(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int desc_sz
)
862 * Calculate the maximum size of WQE s/g segments, excluding
863 * the next segment and other non-data segments.
865 int max_data_size
= desc_sz
- sizeof (struct mthca_next_seg
);
867 switch (qp
->transport
) {
869 max_data_size
-= 2 * sizeof (struct mthca_data_seg
);
873 if (mthca_is_memfree(dev
))
874 max_data_size
-= sizeof (struct mthca_arbel_ud_seg
);
876 max_data_size
-= sizeof (struct mthca_tavor_ud_seg
);
880 max_data_size
-= sizeof (struct mthca_raddr_seg
);
884 return max_data_size
;
887 static inline int mthca_max_inline_data(struct mthca_pd
*pd
, int max_data_size
)
889 /* We don't support inline data for kernel QPs (yet). */
890 return pd
->ibpd
.uobject
? max_data_size
- MTHCA_INLINE_HEADER_SIZE
: 0;
893 static void mthca_adjust_qp_caps(struct mthca_dev
*dev
,
897 int max_data_size
= mthca_max_data_size(dev
, qp
,
898 min(dev
->limits
.max_desc_sz
,
899 1 << qp
->sq
.wqe_shift
));
901 qp
->max_inline_data
= mthca_max_inline_data(pd
, max_data_size
);
903 qp
->sq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
904 max_data_size
/ sizeof (struct mthca_data_seg
));
905 qp
->rq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
906 (min(dev
->limits
.max_desc_sz
, 1 << qp
->rq
.wqe_shift
) -
907 sizeof (struct mthca_next_seg
)) /
908 sizeof (struct mthca_data_seg
));
912 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
913 * rq.max_gs and sq.max_gs must all be assigned.
914 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
915 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
918 static int mthca_alloc_wqe_buf(struct mthca_dev
*dev
,
925 size
= sizeof (struct mthca_next_seg
) +
926 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
);
928 if (size
> dev
->limits
.max_desc_sz
)
931 for (qp
->rq
.wqe_shift
= 6; 1 << qp
->rq
.wqe_shift
< size
;
935 size
= qp
->sq
.max_gs
* sizeof (struct mthca_data_seg
);
936 switch (qp
->transport
) {
938 size
+= 2 * sizeof (struct mthca_data_seg
);
942 size
+= mthca_is_memfree(dev
) ?
943 sizeof (struct mthca_arbel_ud_seg
) :
944 sizeof (struct mthca_tavor_ud_seg
);
948 size
+= sizeof (struct mthca_raddr_seg
);
952 size
+= sizeof (struct mthca_raddr_seg
);
954 * An atomic op will require an atomic segment, a
955 * remote address segment and one scatter entry.
957 size
= max_t(int, size
,
958 sizeof (struct mthca_atomic_seg
) +
959 sizeof (struct mthca_raddr_seg
) +
960 sizeof (struct mthca_data_seg
));
967 /* Make sure that we have enough space for a bind request */
968 size
= max_t(int, size
, sizeof (struct mthca_bind_seg
));
970 size
+= sizeof (struct mthca_next_seg
);
972 if (size
> dev
->limits
.max_desc_sz
)
975 for (qp
->sq
.wqe_shift
= 6; 1 << qp
->sq
.wqe_shift
< size
;
979 qp
->send_wqe_offset
= ALIGN(qp
->rq
.max
<< qp
->rq
.wqe_shift
,
980 1 << qp
->sq
.wqe_shift
);
983 * If this is a userspace QP, we don't actually have to
984 * allocate anything. All we need is to calculate the WQE
985 * sizes and the send_wqe_offset, so we're done now.
987 if (pd
->ibpd
.uobject
)
990 size
= PAGE_ALIGN(qp
->send_wqe_offset
+
991 (qp
->sq
.max
<< qp
->sq
.wqe_shift
));
993 qp
->wrid
= kmalloc((qp
->rq
.max
+ qp
->sq
.max
) * sizeof (u64
),
998 err
= mthca_buf_alloc(dev
, size
, MTHCA_MAX_DIRECT_QP_SIZE
,
999 &qp
->queue
, &qp
->is_direct
, pd
, 0, &qp
->mr
);
1010 static void mthca_free_wqe_buf(struct mthca_dev
*dev
,
1011 struct mthca_qp
*qp
)
1013 mthca_buf_free(dev
, PAGE_ALIGN(qp
->send_wqe_offset
+
1014 (qp
->sq
.max
<< qp
->sq
.wqe_shift
)),
1015 &qp
->queue
, qp
->is_direct
, &qp
->mr
);
1019 static int mthca_map_memfree(struct mthca_dev
*dev
,
1020 struct mthca_qp
*qp
)
1024 if (mthca_is_memfree(dev
)) {
1025 ret
= mthca_table_get(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1029 ret
= mthca_table_get(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1033 ret
= mthca_table_get(dev
, dev
->qp_table
.rdb_table
,
1034 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1043 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1046 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1051 static void mthca_unmap_memfree(struct mthca_dev
*dev
,
1052 struct mthca_qp
*qp
)
1054 mthca_table_put(dev
, dev
->qp_table
.rdb_table
,
1055 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1056 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1057 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1060 static int mthca_alloc_memfree(struct mthca_dev
*dev
,
1061 struct mthca_qp
*qp
)
1065 if (mthca_is_memfree(dev
)) {
1066 qp
->rq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_RQ
,
1067 qp
->qpn
, &qp
->rq
.db
);
1068 if (qp
->rq
.db_index
< 0)
1071 qp
->sq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_SQ
,
1072 qp
->qpn
, &qp
->sq
.db
);
1073 if (qp
->sq
.db_index
< 0)
1074 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1080 static void mthca_free_memfree(struct mthca_dev
*dev
,
1081 struct mthca_qp
*qp
)
1083 if (mthca_is_memfree(dev
)) {
1084 mthca_free_db(dev
, MTHCA_DB_TYPE_SQ
, qp
->sq
.db_index
);
1085 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1089 static int mthca_alloc_qp_common(struct mthca_dev
*dev
,
1090 struct mthca_pd
*pd
,
1091 struct mthca_cq
*send_cq
,
1092 struct mthca_cq
*recv_cq
,
1093 enum ib_sig_type send_policy
,
1094 struct mthca_qp
*qp
)
1099 atomic_set(&qp
->refcount
, 1);
1100 init_waitqueue_head(&qp
->wait
);
1101 qp
->state
= IB_QPS_RESET
;
1102 qp
->atomic_rd_en
= 0;
1104 qp
->sq_policy
= send_policy
;
1105 mthca_wq_init(&qp
->sq
);
1106 mthca_wq_init(&qp
->rq
);
1108 ret
= mthca_map_memfree(dev
, qp
);
1112 ret
= mthca_alloc_wqe_buf(dev
, pd
, qp
);
1114 mthca_unmap_memfree(dev
, qp
);
1118 mthca_adjust_qp_caps(dev
, pd
, qp
);
1121 * If this is a userspace QP, we're done now. The doorbells
1122 * will be allocated and buffers will be initialized in
1125 if (pd
->ibpd
.uobject
)
1128 ret
= mthca_alloc_memfree(dev
, qp
);
1130 mthca_free_wqe_buf(dev
, qp
);
1131 mthca_unmap_memfree(dev
, qp
);
1135 if (mthca_is_memfree(dev
)) {
1136 struct mthca_next_seg
*next
;
1137 struct mthca_data_seg
*scatter
;
1138 int size
= (sizeof (struct mthca_next_seg
) +
1139 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
)) / 16;
1141 for (i
= 0; i
< qp
->rq
.max
; ++i
) {
1142 next
= get_recv_wqe(qp
, i
);
1143 next
->nda_op
= cpu_to_be32(((i
+ 1) & (qp
->rq
.max
- 1)) <<
1145 next
->ee_nds
= cpu_to_be32(size
);
1147 for (scatter
= (void *) (next
+ 1);
1148 (void *) scatter
< (void *) next
+ (1 << qp
->rq
.wqe_shift
);
1150 scatter
->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
1153 for (i
= 0; i
< qp
->sq
.max
; ++i
) {
1154 next
= get_send_wqe(qp
, i
);
1155 next
->nda_op
= cpu_to_be32((((i
+ 1) & (qp
->sq
.max
- 1)) <<
1157 qp
->send_wqe_offset
);
1161 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
1162 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
1167 static int mthca_set_qp_size(struct mthca_dev
*dev
, struct ib_qp_cap
*cap
,
1168 struct mthca_pd
*pd
, struct mthca_qp
*qp
)
1170 int max_data_size
= mthca_max_data_size(dev
, qp
, dev
->limits
.max_desc_sz
);
1172 /* Sanity check QP size before proceeding */
1173 if (cap
->max_send_wr
> dev
->limits
.max_wqes
||
1174 cap
->max_recv_wr
> dev
->limits
.max_wqes
||
1175 cap
->max_send_sge
> dev
->limits
.max_sg
||
1176 cap
->max_recv_sge
> dev
->limits
.max_sg
||
1177 cap
->max_inline_data
> mthca_max_inline_data(pd
, max_data_size
))
1181 * For MLX transport we need 2 extra S/G entries:
1182 * one for the header and one for the checksum at the end
1184 if (qp
->transport
== MLX
&& cap
->max_recv_sge
+ 2 > dev
->limits
.max_sg
)
1187 if (mthca_is_memfree(dev
)) {
1188 qp
->rq
.max
= cap
->max_recv_wr
?
1189 roundup_pow_of_two(cap
->max_recv_wr
) : 0;
1190 qp
->sq
.max
= cap
->max_send_wr
?
1191 roundup_pow_of_two(cap
->max_send_wr
) : 0;
1193 qp
->rq
.max
= cap
->max_recv_wr
;
1194 qp
->sq
.max
= cap
->max_send_wr
;
1197 qp
->rq
.max_gs
= cap
->max_recv_sge
;
1198 qp
->sq
.max_gs
= max_t(int, cap
->max_send_sge
,
1199 ALIGN(cap
->max_inline_data
+ MTHCA_INLINE_HEADER_SIZE
,
1200 MTHCA_INLINE_CHUNK_SIZE
) /
1201 sizeof (struct mthca_data_seg
));
1206 int mthca_alloc_qp(struct mthca_dev
*dev
,
1207 struct mthca_pd
*pd
,
1208 struct mthca_cq
*send_cq
,
1209 struct mthca_cq
*recv_cq
,
1210 enum ib_qp_type type
,
1211 enum ib_sig_type send_policy
,
1212 struct ib_qp_cap
*cap
,
1213 struct mthca_qp
*qp
)
1218 case IB_QPT_RC
: qp
->transport
= RC
; break;
1219 case IB_QPT_UC
: qp
->transport
= UC
; break;
1220 case IB_QPT_UD
: qp
->transport
= UD
; break;
1221 default: return -EINVAL
;
1224 err
= mthca_set_qp_size(dev
, cap
, pd
, qp
);
1228 qp
->qpn
= mthca_alloc(&dev
->qp_table
.alloc
);
1232 /* initialize port to zero for error-catching. */
1235 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1238 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1242 spin_lock_irq(&dev
->qp_table
.lock
);
1243 mthca_array_set(&dev
->qp_table
.qp
,
1244 qp
->qpn
& (dev
->limits
.num_qps
- 1), qp
);
1245 spin_unlock_irq(&dev
->qp_table
.lock
);
1250 int mthca_alloc_sqp(struct mthca_dev
*dev
,
1251 struct mthca_pd
*pd
,
1252 struct mthca_cq
*send_cq
,
1253 struct mthca_cq
*recv_cq
,
1254 enum ib_sig_type send_policy
,
1255 struct ib_qp_cap
*cap
,
1258 struct mthca_sqp
*sqp
)
1260 u32 mqpn
= qpn
* 2 + dev
->qp_table
.sqp_start
+ port
- 1;
1263 sqp
->qp
.transport
= MLX
;
1264 err
= mthca_set_qp_size(dev
, cap
, pd
, &sqp
->qp
);
1268 sqp
->header_buf_size
= sqp
->qp
.sq
.max
* MTHCA_UD_HEADER_SIZE
;
1269 sqp
->header_buf
= dma_alloc_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1270 &sqp
->header_dma
, GFP_KERNEL
);
1271 if (!sqp
->header_buf
)
1274 spin_lock_irq(&dev
->qp_table
.lock
);
1275 if (mthca_array_get(&dev
->qp_table
.qp
, mqpn
))
1278 mthca_array_set(&dev
->qp_table
.qp
, mqpn
, sqp
);
1279 spin_unlock_irq(&dev
->qp_table
.lock
);
1284 sqp
->qp
.port
= port
;
1286 sqp
->qp
.transport
= MLX
;
1288 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1289 send_policy
, &sqp
->qp
);
1293 atomic_inc(&pd
->sqp_count
);
1299 * Lock CQs here, so that CQ polling code can do QP lookup
1300 * without taking a lock.
1302 spin_lock_irq(&send_cq
->lock
);
1303 if (send_cq
!= recv_cq
)
1304 spin_lock(&recv_cq
->lock
);
1306 spin_lock(&dev
->qp_table
.lock
);
1307 mthca_array_clear(&dev
->qp_table
.qp
, mqpn
);
1308 spin_unlock(&dev
->qp_table
.lock
);
1310 if (send_cq
!= recv_cq
)
1311 spin_unlock(&recv_cq
->lock
);
1312 spin_unlock_irq(&send_cq
->lock
);
1315 dma_free_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1316 sqp
->header_buf
, sqp
->header_dma
);
1321 void mthca_free_qp(struct mthca_dev
*dev
,
1322 struct mthca_qp
*qp
)
1325 struct mthca_cq
*send_cq
;
1326 struct mthca_cq
*recv_cq
;
1328 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1329 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
1332 * Lock CQs here, so that CQ polling code can do QP lookup
1333 * without taking a lock.
1335 spin_lock_irq(&send_cq
->lock
);
1336 if (send_cq
!= recv_cq
)
1337 spin_lock(&recv_cq
->lock
);
1339 spin_lock(&dev
->qp_table
.lock
);
1340 mthca_array_clear(&dev
->qp_table
.qp
,
1341 qp
->qpn
& (dev
->limits
.num_qps
- 1));
1342 spin_unlock(&dev
->qp_table
.lock
);
1344 if (send_cq
!= recv_cq
)
1345 spin_unlock(&recv_cq
->lock
);
1346 spin_unlock_irq(&send_cq
->lock
);
1348 atomic_dec(&qp
->refcount
);
1349 wait_event(qp
->wait
, !atomic_read(&qp
->refcount
));
1351 if (qp
->state
!= IB_QPS_RESET
)
1352 mthca_MODIFY_QP(dev
, qp
->state
, IB_QPS_RESET
, qp
->qpn
, 0,
1356 * If this is a userspace QP, the buffers, MR, CQs and so on
1357 * will be cleaned up in userspace, so all we have to do is
1358 * unref the mem-free tables and free the QPN in our table.
1360 if (!qp
->ibqp
.uobject
) {
1361 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
1362 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1363 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
1364 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
1365 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1367 mthca_free_memfree(dev
, qp
);
1368 mthca_free_wqe_buf(dev
, qp
);
1371 mthca_unmap_memfree(dev
, qp
);
1373 if (is_sqp(dev
, qp
)) {
1374 atomic_dec(&(to_mpd(qp
->ibqp
.pd
)->sqp_count
));
1375 dma_free_coherent(&dev
->pdev
->dev
,
1376 to_msqp(qp
)->header_buf_size
,
1377 to_msqp(qp
)->header_buf
,
1378 to_msqp(qp
)->header_dma
);
1380 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1383 /* Create UD header for an MLX send and build a data segment for it */
1384 static int build_mlx_header(struct mthca_dev
*dev
, struct mthca_sqp
*sqp
,
1385 int ind
, struct ib_send_wr
*wr
,
1386 struct mthca_mlx_seg
*mlx
,
1387 struct mthca_data_seg
*data
)
1393 ib_ud_header_init(256, /* assume a MAD */
1394 mthca_ah_grh_present(to_mah(wr
->wr
.ud
.ah
)),
1397 err
= mthca_read_ah(dev
, to_mah(wr
->wr
.ud
.ah
), &sqp
->ud_header
);
1400 mlx
->flags
&= ~cpu_to_be32(MTHCA_NEXT_SOLICIT
| 1);
1401 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MTHCA_MLX_VL15
: 0) |
1402 (sqp
->ud_header
.lrh
.destination_lid
==
1403 IB_LID_PERMISSIVE
? MTHCA_MLX_SLR
: 0) |
1404 (sqp
->ud_header
.lrh
.service_level
<< 8));
1405 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1408 switch (wr
->opcode
) {
1410 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1411 sqp
->ud_header
.immediate_present
= 0;
1413 case IB_WR_SEND_WITH_IMM
:
1414 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1415 sqp
->ud_header
.immediate_present
= 1;
1416 sqp
->ud_header
.immediate_data
= wr
->imm_data
;
1422 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1423 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1424 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1425 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1426 if (!sqp
->qp
.ibqp
.qp_num
)
1427 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->qp
.port
,
1428 sqp
->pkey_index
, &pkey
);
1430 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->qp
.port
,
1431 wr
->wr
.ud
.pkey_index
, &pkey
);
1432 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1433 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1434 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1435 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1436 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1437 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1439 header_size
= ib_ud_header_pack(&sqp
->ud_header
,
1441 ind
* MTHCA_UD_HEADER_SIZE
);
1443 data
->byte_count
= cpu_to_be32(header_size
);
1444 data
->lkey
= cpu_to_be32(to_mpd(sqp
->qp
.ibqp
.pd
)->ntmr
.ibmr
.lkey
);
1445 data
->addr
= cpu_to_be64(sqp
->header_dma
+
1446 ind
* MTHCA_UD_HEADER_SIZE
);
1451 static inline int mthca_wq_overflow(struct mthca_wq
*wq
, int nreq
,
1452 struct ib_cq
*ib_cq
)
1455 struct mthca_cq
*cq
;
1457 cur
= wq
->head
- wq
->tail
;
1458 if (likely(cur
+ nreq
< wq
->max
))
1462 spin_lock(&cq
->lock
);
1463 cur
= wq
->head
- wq
->tail
;
1464 spin_unlock(&cq
->lock
);
1466 return cur
+ nreq
>= wq
->max
;
1469 int mthca_tavor_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1470 struct ib_send_wr
**bad_wr
)
1472 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1473 struct mthca_qp
*qp
= to_mqp(ibqp
);
1476 unsigned long flags
;
1486 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1488 /* XXX check that state is OK to post send */
1490 ind
= qp
->sq
.next_ind
;
1492 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1493 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1494 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1495 " %d max, %d nreq)\n", qp
->qpn
,
1496 qp
->sq
.head
, qp
->sq
.tail
,
1503 wqe
= get_send_wqe(qp
, ind
);
1504 prev_wqe
= qp
->sq
.last
;
1507 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1508 ((struct mthca_next_seg
*) wqe
)->ee_nds
= 0;
1509 ((struct mthca_next_seg
*) wqe
)->flags
=
1510 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1511 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1512 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1513 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1515 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1516 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1517 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1519 wqe
+= sizeof (struct mthca_next_seg
);
1520 size
= sizeof (struct mthca_next_seg
) / 16;
1522 switch (qp
->transport
) {
1524 switch (wr
->opcode
) {
1525 case IB_WR_ATOMIC_CMP_AND_SWP
:
1526 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1527 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1528 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1529 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1530 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1531 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1533 wqe
+= sizeof (struct mthca_raddr_seg
);
1535 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1536 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1537 cpu_to_be64(wr
->wr
.atomic
.swap
);
1538 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1539 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1541 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1542 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1543 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1546 wqe
+= sizeof (struct mthca_atomic_seg
);
1547 size
+= (sizeof (struct mthca_raddr_seg
) +
1548 sizeof (struct mthca_atomic_seg
)) / 16;
1551 case IB_WR_RDMA_WRITE
:
1552 case IB_WR_RDMA_WRITE_WITH_IMM
:
1553 case IB_WR_RDMA_READ
:
1554 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1555 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1556 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1557 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1558 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1559 wqe
+= sizeof (struct mthca_raddr_seg
);
1560 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1564 /* No extra segments required for sends */
1571 switch (wr
->opcode
) {
1572 case IB_WR_RDMA_WRITE
:
1573 case IB_WR_RDMA_WRITE_WITH_IMM
:
1574 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1575 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1576 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1577 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1578 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1579 wqe
+= sizeof (struct mthca_raddr_seg
);
1580 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1584 /* No extra segments required for sends */
1591 ((struct mthca_tavor_ud_seg
*) wqe
)->lkey
=
1592 cpu_to_be32(to_mah(wr
->wr
.ud
.ah
)->key
);
1593 ((struct mthca_tavor_ud_seg
*) wqe
)->av_addr
=
1594 cpu_to_be64(to_mah(wr
->wr
.ud
.ah
)->avdma
);
1595 ((struct mthca_tavor_ud_seg
*) wqe
)->dqpn
=
1596 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1597 ((struct mthca_tavor_ud_seg
*) wqe
)->qkey
=
1598 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1600 wqe
+= sizeof (struct mthca_tavor_ud_seg
);
1601 size
+= sizeof (struct mthca_tavor_ud_seg
) / 16;
1605 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1606 wqe
- sizeof (struct mthca_next_seg
),
1612 wqe
+= sizeof (struct mthca_data_seg
);
1613 size
+= sizeof (struct mthca_data_seg
) / 16;
1617 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1618 mthca_err(dev
, "too many gathers\n");
1624 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1625 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1626 cpu_to_be32(wr
->sg_list
[i
].length
);
1627 ((struct mthca_data_seg
*) wqe
)->lkey
=
1628 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1629 ((struct mthca_data_seg
*) wqe
)->addr
=
1630 cpu_to_be64(wr
->sg_list
[i
].addr
);
1631 wqe
+= sizeof (struct mthca_data_seg
);
1632 size
+= sizeof (struct mthca_data_seg
) / 16;
1635 /* Add one more inline data segment for ICRC */
1636 if (qp
->transport
== MLX
) {
1637 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1638 cpu_to_be32((1 << 31) | 4);
1639 ((u32
*) wqe
)[1] = 0;
1640 wqe
+= sizeof (struct mthca_data_seg
);
1641 size
+= sizeof (struct mthca_data_seg
) / 16;
1644 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1646 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1647 mthca_err(dev
, "opcode invalid\n");
1653 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1654 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1655 qp
->send_wqe_offset
) |
1656 mthca_opcode
[wr
->opcode
]);
1658 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1659 cpu_to_be32((size0
? 0 : MTHCA_NEXT_DBD
) | size
|
1660 ((wr
->send_flags
& IB_SEND_FENCE
) ?
1661 MTHCA_NEXT_FENCE
: 0));
1665 op0
= mthca_opcode
[wr
->opcode
];
1669 if (unlikely(ind
>= qp
->sq
.max
))
1677 doorbell
[0] = cpu_to_be32(((qp
->sq
.next_ind
<< qp
->sq
.wqe_shift
) +
1678 qp
->send_wqe_offset
) | f0
| op0
);
1679 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1683 mthca_write64(doorbell
,
1684 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1685 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1688 qp
->sq
.next_ind
= ind
;
1689 qp
->sq
.head
+= nreq
;
1691 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1695 int mthca_tavor_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1696 struct ib_recv_wr
**bad_wr
)
1698 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1699 struct mthca_qp
*qp
= to_mqp(ibqp
);
1701 unsigned long flags
;
1711 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1713 /* XXX check that state is OK to post receive */
1715 ind
= qp
->rq
.next_ind
;
1717 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1718 if (unlikely(nreq
== MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
)) {
1721 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1722 doorbell
[1] = cpu_to_be32(qp
->qpn
<< 8);
1726 mthca_write64(doorbell
,
1727 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1728 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1730 qp
->rq
.head
+= MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
;
1734 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1735 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
1736 " %d max, %d nreq)\n", qp
->qpn
,
1737 qp
->rq
.head
, qp
->rq
.tail
,
1744 wqe
= get_recv_wqe(qp
, ind
);
1745 prev_wqe
= qp
->rq
.last
;
1748 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1749 ((struct mthca_next_seg
*) wqe
)->ee_nds
=
1750 cpu_to_be32(MTHCA_NEXT_DBD
);
1751 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
1753 wqe
+= sizeof (struct mthca_next_seg
);
1754 size
= sizeof (struct mthca_next_seg
) / 16;
1756 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1762 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1763 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1764 cpu_to_be32(wr
->sg_list
[i
].length
);
1765 ((struct mthca_data_seg
*) wqe
)->lkey
=
1766 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1767 ((struct mthca_data_seg
*) wqe
)->addr
=
1768 cpu_to_be64(wr
->sg_list
[i
].addr
);
1769 wqe
+= sizeof (struct mthca_data_seg
);
1770 size
+= sizeof (struct mthca_data_seg
) / 16;
1773 qp
->wrid
[ind
] = wr
->wr_id
;
1775 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1776 cpu_to_be32((ind
<< qp
->rq
.wqe_shift
) | 1);
1778 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1779 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
1785 if (unlikely(ind
>= qp
->rq
.max
))
1791 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1792 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | nreq
);
1796 mthca_write64(doorbell
,
1797 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1798 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1801 qp
->rq
.next_ind
= ind
;
1802 qp
->rq
.head
+= nreq
;
1804 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1808 int mthca_arbel_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1809 struct ib_send_wr
**bad_wr
)
1811 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1812 struct mthca_qp
*qp
= to_mqp(ibqp
);
1816 unsigned long flags
;
1826 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1828 /* XXX check that state is OK to post send */
1830 ind
= qp
->sq
.head
& (qp
->sq
.max
- 1);
1832 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1833 if (unlikely(nreq
== MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
)) {
1836 doorbell
[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
<< 24) |
1837 ((qp
->sq
.head
& 0xffff) << 8) |
1839 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1841 qp
->sq
.head
+= MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
;
1845 * Make sure that descriptors are written before
1849 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
1852 * Make sure doorbell record is written before we
1853 * write MMIO send doorbell.
1856 mthca_write64(doorbell
,
1857 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1858 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1861 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1862 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1863 " %d max, %d nreq)\n", qp
->qpn
,
1864 qp
->sq
.head
, qp
->sq
.tail
,
1871 wqe
= get_send_wqe(qp
, ind
);
1872 prev_wqe
= qp
->sq
.last
;
1875 ((struct mthca_next_seg
*) wqe
)->flags
=
1876 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1877 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1878 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1879 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1881 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1882 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1883 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1885 wqe
+= sizeof (struct mthca_next_seg
);
1886 size
= sizeof (struct mthca_next_seg
) / 16;
1888 switch (qp
->transport
) {
1890 switch (wr
->opcode
) {
1891 case IB_WR_ATOMIC_CMP_AND_SWP
:
1892 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1893 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1894 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1895 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1896 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1897 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1899 wqe
+= sizeof (struct mthca_raddr_seg
);
1901 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1902 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1903 cpu_to_be64(wr
->wr
.atomic
.swap
);
1904 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1905 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1907 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1908 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1909 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1912 wqe
+= sizeof (struct mthca_atomic_seg
);
1913 size
+= (sizeof (struct mthca_raddr_seg
) +
1914 sizeof (struct mthca_atomic_seg
)) / 16;
1917 case IB_WR_RDMA_READ
:
1918 case IB_WR_RDMA_WRITE
:
1919 case IB_WR_RDMA_WRITE_WITH_IMM
:
1920 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1921 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1922 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1923 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1924 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1925 wqe
+= sizeof (struct mthca_raddr_seg
);
1926 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1930 /* No extra segments required for sends */
1937 switch (wr
->opcode
) {
1938 case IB_WR_RDMA_WRITE
:
1939 case IB_WR_RDMA_WRITE_WITH_IMM
:
1940 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1941 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1942 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1943 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1944 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1945 wqe
+= sizeof (struct mthca_raddr_seg
);
1946 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1950 /* No extra segments required for sends */
1957 memcpy(((struct mthca_arbel_ud_seg
*) wqe
)->av
,
1958 to_mah(wr
->wr
.ud
.ah
)->av
, MTHCA_AV_SIZE
);
1959 ((struct mthca_arbel_ud_seg
*) wqe
)->dqpn
=
1960 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1961 ((struct mthca_arbel_ud_seg
*) wqe
)->qkey
=
1962 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1964 wqe
+= sizeof (struct mthca_arbel_ud_seg
);
1965 size
+= sizeof (struct mthca_arbel_ud_seg
) / 16;
1969 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1970 wqe
- sizeof (struct mthca_next_seg
),
1976 wqe
+= sizeof (struct mthca_data_seg
);
1977 size
+= sizeof (struct mthca_data_seg
) / 16;
1981 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1982 mthca_err(dev
, "too many gathers\n");
1988 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1989 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1990 cpu_to_be32(wr
->sg_list
[i
].length
);
1991 ((struct mthca_data_seg
*) wqe
)->lkey
=
1992 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1993 ((struct mthca_data_seg
*) wqe
)->addr
=
1994 cpu_to_be64(wr
->sg_list
[i
].addr
);
1995 wqe
+= sizeof (struct mthca_data_seg
);
1996 size
+= sizeof (struct mthca_data_seg
) / 16;
1999 /* Add one more inline data segment for ICRC */
2000 if (qp
->transport
== MLX
) {
2001 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2002 cpu_to_be32((1 << 31) | 4);
2003 ((u32
*) wqe
)[1] = 0;
2004 wqe
+= sizeof (struct mthca_data_seg
);
2005 size
+= sizeof (struct mthca_data_seg
) / 16;
2008 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
2010 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
2011 mthca_err(dev
, "opcode invalid\n");
2017 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
2018 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
2019 qp
->send_wqe_offset
) |
2020 mthca_opcode
[wr
->opcode
]);
2022 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
2023 cpu_to_be32(MTHCA_NEXT_DBD
| size
|
2024 ((wr
->send_flags
& IB_SEND_FENCE
) ?
2025 MTHCA_NEXT_FENCE
: 0));
2029 op0
= mthca_opcode
[wr
->opcode
];
2033 if (unlikely(ind
>= qp
->sq
.max
))
2039 doorbell
[0] = cpu_to_be32((nreq
<< 24) |
2040 ((qp
->sq
.head
& 0xffff) << 8) |
2042 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
2044 qp
->sq
.head
+= nreq
;
2047 * Make sure that descriptors are written before
2051 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
2054 * Make sure doorbell record is written before we
2055 * write MMIO send doorbell.
2058 mthca_write64(doorbell
,
2059 dev
->kar
+ MTHCA_SEND_DOORBELL
,
2060 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
2063 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
2067 int mthca_arbel_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
2068 struct ib_recv_wr
**bad_wr
)
2070 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
2071 struct mthca_qp
*qp
= to_mqp(ibqp
);
2072 unsigned long flags
;
2079 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
2081 /* XXX check that state is OK to post receive */
2083 ind
= qp
->rq
.head
& (qp
->rq
.max
- 1);
2085 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
2086 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
2087 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
2088 " %d max, %d nreq)\n", qp
->qpn
,
2089 qp
->rq
.head
, qp
->rq
.tail
,
2096 wqe
= get_recv_wqe(qp
, ind
);
2098 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
2100 wqe
+= sizeof (struct mthca_next_seg
);
2102 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
2108 for (i
= 0; i
< wr
->num_sge
; ++i
) {
2109 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2110 cpu_to_be32(wr
->sg_list
[i
].length
);
2111 ((struct mthca_data_seg
*) wqe
)->lkey
=
2112 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2113 ((struct mthca_data_seg
*) wqe
)->addr
=
2114 cpu_to_be64(wr
->sg_list
[i
].addr
);
2115 wqe
+= sizeof (struct mthca_data_seg
);
2118 if (i
< qp
->rq
.max_gs
) {
2119 ((struct mthca_data_seg
*) wqe
)->byte_count
= 0;
2120 ((struct mthca_data_seg
*) wqe
)->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
2121 ((struct mthca_data_seg
*) wqe
)->addr
= 0;
2124 qp
->wrid
[ind
] = wr
->wr_id
;
2127 if (unlikely(ind
>= qp
->rq
.max
))
2132 qp
->rq
.head
+= nreq
;
2135 * Make sure that descriptors are written before
2139 *qp
->rq
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
2142 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
2146 void mthca_free_err_wqe(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int is_send
,
2147 int index
, int *dbd
, __be32
*new_wqe
)
2149 struct mthca_next_seg
*next
;
2152 * For SRQs, all WQEs generate a CQE, so we're always at the
2153 * end of the doorbell chain.
2161 next
= get_send_wqe(qp
, index
);
2163 next
= get_recv_wqe(qp
, index
);
2165 *dbd
= !!(next
->ee_nds
& cpu_to_be32(MTHCA_NEXT_DBD
));
2166 if (next
->ee_nds
& cpu_to_be32(0x3f))
2167 *new_wqe
= (next
->nda_op
& cpu_to_be32(~0x3f)) |
2168 (next
->ee_nds
& cpu_to_be32(0x3f));
2173 int __devinit
mthca_init_qp_table(struct mthca_dev
*dev
)
2179 spin_lock_init(&dev
->qp_table
.lock
);
2182 * We reserve 2 extra QPs per port for the special QPs. The
2183 * special QP for port 1 has to be even, so round up.
2185 dev
->qp_table
.sqp_start
= (dev
->limits
.reserved_qps
+ 1) & ~1UL;
2186 err
= mthca_alloc_init(&dev
->qp_table
.alloc
,
2187 dev
->limits
.num_qps
,
2189 dev
->qp_table
.sqp_start
+
2190 MTHCA_MAX_PORTS
* 2);
2194 err
= mthca_array_init(&dev
->qp_table
.qp
,
2195 dev
->limits
.num_qps
);
2197 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2201 for (i
= 0; i
< 2; ++i
) {
2202 err
= mthca_CONF_SPECIAL_QP(dev
, i
? IB_QPT_GSI
: IB_QPT_SMI
,
2203 dev
->qp_table
.sqp_start
+ i
* 2,
2208 mthca_warn(dev
, "CONF_SPECIAL_QP returned "
2209 "status %02x, aborting.\n",
2218 for (i
= 0; i
< 2; ++i
)
2219 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2221 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2222 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2227 void mthca_cleanup_qp_table(struct mthca_dev
*dev
)
2232 for (i
= 0; i
< 2; ++i
)
2233 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2235 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2236 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);