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Merge branch 'misc' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc...
[deliverable/linux.git] / drivers / infiniband / hw / mthca / mthca_qp.c
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 *
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 */
37
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
58 };
59
60 enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83 };
84
85 enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100 };
101
102 struct mthca_qp_path {
103 __be32 port_pkey;
104 u8 rnr_retry;
105 u8 g_mylmc;
106 __be16 rlid;
107 u8 ackto;
108 u8 mgid_index;
109 u8 static_rate;
110 u8 hop_limit;
111 __be32 sl_tclass_flowlabel;
112 u8 rgid[16];
113 } __attribute__((packed));
114
115 struct mthca_qp_context {
116 __be32 flags;
117 __be32 tavor_sched_queue; /* Reserved on Arbel */
118 u8 mtu_msgmax;
119 u8 rq_size_stride; /* Reserved on Tavor */
120 u8 sq_size_stride; /* Reserved on Tavor */
121 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
122 __be32 usr_page;
123 __be32 local_qpn;
124 __be32 remote_qpn;
125 u32 reserved1[2];
126 struct mthca_qp_path pri_path;
127 struct mthca_qp_path alt_path;
128 __be32 rdd;
129 __be32 pd;
130 __be32 wqe_base;
131 __be32 wqe_lkey;
132 __be32 params1;
133 __be32 reserved2;
134 __be32 next_send_psn;
135 __be32 cqn_snd;
136 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
137 __be32 snd_db_index; /* (debugging only entries) */
138 __be32 last_acked_psn;
139 __be32 ssn;
140 __be32 params2;
141 __be32 rnr_nextrecvpsn;
142 __be32 ra_buff_indx;
143 __be32 cqn_rcv;
144 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
145 __be32 rcv_db_index; /* (debugging only entries) */
146 __be32 qkey;
147 __be32 srqn;
148 __be32 rmsn;
149 __be16 rq_wqe_counter; /* reserved on Tavor */
150 __be16 sq_wqe_counter; /* reserved on Tavor */
151 u32 reserved3[18];
152 } __attribute__((packed));
153
154 struct mthca_qp_param {
155 __be32 opt_param_mask;
156 u32 reserved1;
157 struct mthca_qp_context context;
158 u32 reserved2[62];
159 } __attribute__((packed));
160
161 enum {
162 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
163 MTHCA_QP_OPTPAR_RRE = 1 << 1,
164 MTHCA_QP_OPTPAR_RAE = 1 << 2,
165 MTHCA_QP_OPTPAR_RWE = 1 << 3,
166 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
167 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
168 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
169 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
170 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
171 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
172 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
173 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
174 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
175 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
176 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
177 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
178 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
179 };
180
181 static const u8 mthca_opcode[] = {
182 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
183 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
184 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
185 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
186 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
187 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
188 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
189 };
190
191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
192 {
193 return qp->qpn >= dev->qp_table.sqp_start &&
194 qp->qpn <= dev->qp_table.sqp_start + 3;
195 }
196
197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
198 {
199 return qp->qpn >= dev->qp_table.sqp_start &&
200 qp->qpn <= dev->qp_table.sqp_start + 1;
201 }
202
203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
204 {
205 if (qp->is_direct)
206 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
207 else
208 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
209 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
210 }
211
212 static void *get_send_wqe(struct mthca_qp *qp, int n)
213 {
214 if (qp->is_direct)
215 return qp->queue.direct.buf + qp->send_wqe_offset +
216 (n << qp->sq.wqe_shift);
217 else
218 return qp->queue.page_list[(qp->send_wqe_offset +
219 (n << qp->sq.wqe_shift)) >>
220 PAGE_SHIFT].buf +
221 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
222 (PAGE_SIZE - 1));
223 }
224
225 static void mthca_wq_init(struct mthca_wq *wq)
226 {
227 spin_lock_init(&wq->lock);
228 wq->next_ind = 0;
229 wq->last_comp = wq->max - 1;
230 wq->head = 0;
231 wq->tail = 0;
232 }
233
234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
235 enum ib_event_type event_type)
236 {
237 struct mthca_qp *qp;
238 struct ib_event event;
239
240 spin_lock(&dev->qp_table.lock);
241 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
242 if (qp)
243 atomic_inc(&qp->refcount);
244 spin_unlock(&dev->qp_table.lock);
245
246 if (!qp) {
247 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
248 return;
249 }
250
251 if (event_type == IB_EVENT_PATH_MIG)
252 qp->port = qp->alt_port;
253
254 event.device = &dev->ib_dev;
255 event.event = event_type;
256 event.element.qp = &qp->ibqp;
257 if (qp->ibqp.event_handler)
258 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
259
260 if (atomic_dec_and_test(&qp->refcount))
261 wake_up(&qp->wait);
262 }
263
264 static int to_mthca_state(enum ib_qp_state ib_state)
265 {
266 switch (ib_state) {
267 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
268 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
269 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
270 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
271 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
272 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
273 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
274 default: return -1;
275 }
276 }
277
278 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
279
280 static int to_mthca_st(int transport)
281 {
282 switch (transport) {
283 case RC: return MTHCA_QP_ST_RC;
284 case UC: return MTHCA_QP_ST_UC;
285 case UD: return MTHCA_QP_ST_UD;
286 case RD: return MTHCA_QP_ST_RD;
287 case MLX: return MTHCA_QP_ST_MLX;
288 default: return -1;
289 }
290 }
291
292 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
293 int attr_mask)
294 {
295 if (attr_mask & IB_QP_PKEY_INDEX)
296 sqp->pkey_index = attr->pkey_index;
297 if (attr_mask & IB_QP_QKEY)
298 sqp->qkey = attr->qkey;
299 if (attr_mask & IB_QP_SQ_PSN)
300 sqp->send_psn = attr->sq_psn;
301 }
302
303 static void init_port(struct mthca_dev *dev, int port)
304 {
305 int err;
306 u8 status;
307 struct mthca_init_ib_param param;
308
309 memset(&param, 0, sizeof param);
310
311 param.port_width = dev->limits.port_width_cap;
312 param.vl_cap = dev->limits.vl_cap;
313 param.mtu_cap = dev->limits.mtu_cap;
314 param.gid_cap = dev->limits.gid_table_len;
315 param.pkey_cap = dev->limits.pkey_table_len;
316
317 err = mthca_INIT_IB(dev, &param, port, &status);
318 if (err)
319 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
320 if (status)
321 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
322 }
323
324 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
325 int attr_mask)
326 {
327 u8 dest_rd_atomic;
328 u32 access_flags;
329 u32 hw_access_flags = 0;
330
331 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
332 dest_rd_atomic = attr->max_dest_rd_atomic;
333 else
334 dest_rd_atomic = qp->resp_depth;
335
336 if (attr_mask & IB_QP_ACCESS_FLAGS)
337 access_flags = attr->qp_access_flags;
338 else
339 access_flags = qp->atomic_rd_en;
340
341 if (!dest_rd_atomic)
342 access_flags &= IB_ACCESS_REMOTE_WRITE;
343
344 if (access_flags & IB_ACCESS_REMOTE_READ)
345 hw_access_flags |= MTHCA_QP_BIT_RRE;
346 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
347 hw_access_flags |= MTHCA_QP_BIT_RAE;
348 if (access_flags & IB_ACCESS_REMOTE_WRITE)
349 hw_access_flags |= MTHCA_QP_BIT_RWE;
350
351 return cpu_to_be32(hw_access_flags);
352 }
353
354 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
355 {
356 switch (mthca_state) {
357 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
358 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
359 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
360 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
361 case MTHCA_QP_STATE_DRAINING:
362 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
363 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
364 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
365 default: return -1;
366 }
367 }
368
369 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
370 {
371 switch (mthca_mig_state) {
372 case 0: return IB_MIG_ARMED;
373 case 1: return IB_MIG_REARM;
374 case 3: return IB_MIG_MIGRATED;
375 default: return -1;
376 }
377 }
378
379 static int to_ib_qp_access_flags(int mthca_flags)
380 {
381 int ib_flags = 0;
382
383 if (mthca_flags & MTHCA_QP_BIT_RRE)
384 ib_flags |= IB_ACCESS_REMOTE_READ;
385 if (mthca_flags & MTHCA_QP_BIT_RWE)
386 ib_flags |= IB_ACCESS_REMOTE_WRITE;
387 if (mthca_flags & MTHCA_QP_BIT_RAE)
388 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
389
390 return ib_flags;
391 }
392
393 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
394 struct mthca_qp_path *path)
395 {
396 memset(ib_ah_attr, 0, sizeof *path);
397 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
398
399 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
400 return;
401
402 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
403 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
404 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
405 ib_ah_attr->static_rate = mthca_rate_to_ib(dev,
406 path->static_rate & 0x7,
407 ib_ah_attr->port_num);
408 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
409 if (ib_ah_attr->ah_flags) {
410 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
411 ib_ah_attr->grh.hop_limit = path->hop_limit;
412 ib_ah_attr->grh.traffic_class =
413 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
414 ib_ah_attr->grh.flow_label =
415 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
416 memcpy(ib_ah_attr->grh.dgid.raw,
417 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
418 }
419 }
420
421 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
422 struct ib_qp_init_attr *qp_init_attr)
423 {
424 struct mthca_dev *dev = to_mdev(ibqp->device);
425 struct mthca_qp *qp = to_mqp(ibqp);
426 int err;
427 struct mthca_mailbox *mailbox;
428 struct mthca_qp_param *qp_param;
429 struct mthca_qp_context *context;
430 int mthca_state;
431 u8 status;
432
433 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
434 if (IS_ERR(mailbox))
435 return PTR_ERR(mailbox);
436
437 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
438 if (err)
439 goto out;
440 if (status) {
441 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
442 err = -EINVAL;
443 goto out;
444 }
445
446 qp_param = mailbox->buf;
447 context = &qp_param->context;
448 mthca_state = be32_to_cpu(context->flags) >> 28;
449
450 qp_attr->qp_state = to_ib_qp_state(mthca_state);
451 qp_attr->cur_qp_state = qp_attr->qp_state;
452 qp_attr->path_mtu = context->mtu_msgmax >> 5;
453 qp_attr->path_mig_state =
454 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
455 qp_attr->qkey = be32_to_cpu(context->qkey);
456 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
457 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
458 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
459 qp_attr->qp_access_flags =
460 to_ib_qp_access_flags(be32_to_cpu(context->params2));
461 qp_attr->cap.max_send_wr = qp->sq.max;
462 qp_attr->cap.max_recv_wr = qp->rq.max;
463 qp_attr->cap.max_send_sge = qp->sq.max_gs;
464 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
465 qp_attr->cap.max_inline_data = qp->max_inline_data;
466
467 if (qp->transport == RC || qp->transport == UC) {
468 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
469 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
470 }
471
472 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
473 qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
474
475 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
476 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
477
478 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
479
480 qp_attr->max_dest_rd_atomic =
481 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
482 qp_attr->min_rnr_timer =
483 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
484 qp_attr->port_num = qp_attr->ah_attr.port_num;
485 qp_attr->timeout = context->pri_path.ackto >> 3;
486 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
487 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
488 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
489 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
490 qp_init_attr->cap = qp_attr->cap;
491
492 out:
493 mthca_free_mailbox(dev, mailbox);
494 return err;
495 }
496
497 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
498 struct mthca_qp_path *path, u8 port)
499 {
500 path->g_mylmc = ah->src_path_bits & 0x7f;
501 path->rlid = cpu_to_be16(ah->dlid);
502 path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
503
504 if (ah->ah_flags & IB_AH_GRH) {
505 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
506 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
507 ah->grh.sgid_index, dev->limits.gid_table_len-1);
508 return -1;
509 }
510
511 path->g_mylmc |= 1 << 7;
512 path->mgid_index = ah->grh.sgid_index;
513 path->hop_limit = ah->grh.hop_limit;
514 path->sl_tclass_flowlabel =
515 cpu_to_be32((ah->sl << 28) |
516 (ah->grh.traffic_class << 20) |
517 (ah->grh.flow_label));
518 memcpy(path->rgid, ah->grh.dgid.raw, 16);
519 } else
520 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
521
522 return 0;
523 }
524
525 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
526 {
527 struct mthca_dev *dev = to_mdev(ibqp->device);
528 struct mthca_qp *qp = to_mqp(ibqp);
529 enum ib_qp_state cur_state, new_state;
530 struct mthca_mailbox *mailbox;
531 struct mthca_qp_param *qp_param;
532 struct mthca_qp_context *qp_context;
533 u32 sqd_event = 0;
534 u8 status;
535 int err;
536
537 if (attr_mask & IB_QP_CUR_STATE) {
538 cur_state = attr->cur_qp_state;
539 } else {
540 spin_lock_irq(&qp->sq.lock);
541 spin_lock(&qp->rq.lock);
542 cur_state = qp->state;
543 spin_unlock(&qp->rq.lock);
544 spin_unlock_irq(&qp->sq.lock);
545 }
546
547 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
548
549 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
550 mthca_dbg(dev, "Bad QP transition (transport %d) "
551 "%d->%d with attr 0x%08x\n",
552 qp->transport, cur_state, new_state,
553 attr_mask);
554 return -EINVAL;
555 }
556
557 if ((attr_mask & IB_QP_PKEY_INDEX) &&
558 attr->pkey_index >= dev->limits.pkey_table_len) {
559 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
560 attr->pkey_index, dev->limits.pkey_table_len-1);
561 return -EINVAL;
562 }
563
564 if ((attr_mask & IB_QP_PORT) &&
565 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
566 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
567 return -EINVAL;
568 }
569
570 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
571 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
572 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
573 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
574 return -EINVAL;
575 }
576
577 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
578 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
579 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
580 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
581 return -EINVAL;
582 }
583
584 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
585 if (IS_ERR(mailbox))
586 return PTR_ERR(mailbox);
587 qp_param = mailbox->buf;
588 qp_context = &qp_param->context;
589 memset(qp_param, 0, sizeof *qp_param);
590
591 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
592 (to_mthca_st(qp->transport) << 16));
593 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
594 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
595 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
596 else {
597 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
598 switch (attr->path_mig_state) {
599 case IB_MIG_MIGRATED:
600 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
601 break;
602 case IB_MIG_REARM:
603 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
604 break;
605 case IB_MIG_ARMED:
606 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
607 break;
608 }
609 }
610
611 /* leave tavor_sched_queue as 0 */
612
613 if (qp->transport == MLX || qp->transport == UD)
614 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
615 else if (attr_mask & IB_QP_PATH_MTU) {
616 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
617 mthca_dbg(dev, "path MTU (%u) is invalid\n",
618 attr->path_mtu);
619 return -EINVAL;
620 }
621 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
622 }
623
624 if (mthca_is_memfree(dev)) {
625 if (qp->rq.max)
626 qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
627 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
628
629 if (qp->sq.max)
630 qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
631 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
632 }
633
634 /* leave arbel_sched_queue as 0 */
635
636 if (qp->ibqp.uobject)
637 qp_context->usr_page =
638 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
639 else
640 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
641 qp_context->local_qpn = cpu_to_be32(qp->qpn);
642 if (attr_mask & IB_QP_DEST_QPN) {
643 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
644 }
645
646 if (qp->transport == MLX)
647 qp_context->pri_path.port_pkey |=
648 cpu_to_be32(qp->port << 24);
649 else {
650 if (attr_mask & IB_QP_PORT) {
651 qp_context->pri_path.port_pkey |=
652 cpu_to_be32(attr->port_num << 24);
653 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
654 }
655 }
656
657 if (attr_mask & IB_QP_PKEY_INDEX) {
658 qp_context->pri_path.port_pkey |=
659 cpu_to_be32(attr->pkey_index);
660 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
661 }
662
663 if (attr_mask & IB_QP_RNR_RETRY) {
664 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
665 attr->rnr_retry << 5;
666 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
667 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
668 }
669
670 if (attr_mask & IB_QP_AV) {
671 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
672 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
673 return -EINVAL;
674
675 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
676 }
677
678 if (attr_mask & IB_QP_TIMEOUT) {
679 qp_context->pri_path.ackto = attr->timeout << 3;
680 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
681 }
682
683 if (attr_mask & IB_QP_ALT_PATH) {
684 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
685 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
686 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
687 return -EINVAL;
688 }
689
690 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
691 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
692 attr->alt_port_num);
693 return -EINVAL;
694 }
695
696 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
697 attr->alt_ah_attr.port_num))
698 return -EINVAL;
699
700 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
701 attr->alt_port_num << 24);
702 qp_context->alt_path.ackto = attr->alt_timeout << 3;
703 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
704 }
705
706 /* leave rdd as 0 */
707 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
708 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
709 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
710 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
711 (MTHCA_FLIGHT_LIMIT << 24) |
712 MTHCA_QP_BIT_SWE);
713 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
714 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
715 if (attr_mask & IB_QP_RETRY_CNT) {
716 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
717 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
718 }
719
720 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
721 if (attr->max_rd_atomic) {
722 qp_context->params1 |=
723 cpu_to_be32(MTHCA_QP_BIT_SRE |
724 MTHCA_QP_BIT_SAE);
725 qp_context->params1 |=
726 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
727 }
728 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
729 }
730
731 if (attr_mask & IB_QP_SQ_PSN)
732 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
733 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
734
735 if (mthca_is_memfree(dev)) {
736 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
737 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
738 }
739
740 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
741 if (attr->max_dest_rd_atomic)
742 qp_context->params2 |=
743 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
744
745 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
746 }
747
748 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
749 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
750 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
751 MTHCA_QP_OPTPAR_RRE |
752 MTHCA_QP_OPTPAR_RAE);
753 }
754
755 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
756
757 if (ibqp->srq)
758 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
759
760 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
761 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
762 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
763 }
764 if (attr_mask & IB_QP_RQ_PSN)
765 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
766
767 qp_context->ra_buff_indx =
768 cpu_to_be32(dev->qp_table.rdb_base +
769 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
770 dev->qp_table.rdb_shift));
771
772 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
773
774 if (mthca_is_memfree(dev))
775 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
776
777 if (attr_mask & IB_QP_QKEY) {
778 qp_context->qkey = cpu_to_be32(attr->qkey);
779 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
780 }
781
782 if (ibqp->srq)
783 qp_context->srqn = cpu_to_be32(1 << 24 |
784 to_msrq(ibqp->srq)->srqn);
785
786 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
787 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
788 attr->en_sqd_async_notify)
789 sqd_event = 1 << 31;
790
791 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
792 mailbox, sqd_event, &status);
793 if (err)
794 goto out;
795 if (status) {
796 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
797 cur_state, new_state, status);
798 err = -EINVAL;
799 goto out;
800 }
801
802 qp->state = new_state;
803 if (attr_mask & IB_QP_ACCESS_FLAGS)
804 qp->atomic_rd_en = attr->qp_access_flags;
805 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
806 qp->resp_depth = attr->max_dest_rd_atomic;
807 if (attr_mask & IB_QP_PORT)
808 qp->port = attr->port_num;
809 if (attr_mask & IB_QP_ALT_PATH)
810 qp->alt_port = attr->alt_port_num;
811
812 if (is_sqp(dev, qp))
813 store_attrs(to_msqp(qp), attr, attr_mask);
814
815 /*
816 * If we moved QP0 to RTR, bring the IB link up; if we moved
817 * QP0 to RESET or ERROR, bring the link back down.
818 */
819 if (is_qp0(dev, qp)) {
820 if (cur_state != IB_QPS_RTR &&
821 new_state == IB_QPS_RTR)
822 init_port(dev, qp->port);
823
824 if (cur_state != IB_QPS_RESET &&
825 cur_state != IB_QPS_ERR &&
826 (new_state == IB_QPS_RESET ||
827 new_state == IB_QPS_ERR))
828 mthca_CLOSE_IB(dev, qp->port, &status);
829 }
830
831 /*
832 * If we moved a kernel QP to RESET, clean up all old CQ
833 * entries and reinitialize the QP.
834 */
835 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
836 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
837 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
838 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
839 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
840 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
841
842 mthca_wq_init(&qp->sq);
843 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
844
845 mthca_wq_init(&qp->rq);
846 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
847
848 if (mthca_is_memfree(dev)) {
849 *qp->sq.db = 0;
850 *qp->rq.db = 0;
851 }
852 }
853
854 out:
855 mthca_free_mailbox(dev, mailbox);
856 return err;
857 }
858
859 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
860 {
861 /*
862 * Calculate the maximum size of WQE s/g segments, excluding
863 * the next segment and other non-data segments.
864 */
865 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
866
867 switch (qp->transport) {
868 case MLX:
869 max_data_size -= 2 * sizeof (struct mthca_data_seg);
870 break;
871
872 case UD:
873 if (mthca_is_memfree(dev))
874 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
875 else
876 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
877 break;
878
879 default:
880 max_data_size -= sizeof (struct mthca_raddr_seg);
881 break;
882 }
883
884 return max_data_size;
885 }
886
887 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
888 {
889 /* We don't support inline data for kernel QPs (yet). */
890 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
891 }
892
893 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
894 struct mthca_pd *pd,
895 struct mthca_qp *qp)
896 {
897 int max_data_size = mthca_max_data_size(dev, qp,
898 min(dev->limits.max_desc_sz,
899 1 << qp->sq.wqe_shift));
900
901 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
902
903 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
904 max_data_size / sizeof (struct mthca_data_seg));
905 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
906 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
907 sizeof (struct mthca_next_seg)) /
908 sizeof (struct mthca_data_seg));
909 }
910
911 /*
912 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
913 * rq.max_gs and sq.max_gs must all be assigned.
914 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
915 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
916 * queue)
917 */
918 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
919 struct mthca_pd *pd,
920 struct mthca_qp *qp)
921 {
922 int size;
923 int err = -ENOMEM;
924
925 size = sizeof (struct mthca_next_seg) +
926 qp->rq.max_gs * sizeof (struct mthca_data_seg);
927
928 if (size > dev->limits.max_desc_sz)
929 return -EINVAL;
930
931 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
932 qp->rq.wqe_shift++)
933 ; /* nothing */
934
935 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
936 switch (qp->transport) {
937 case MLX:
938 size += 2 * sizeof (struct mthca_data_seg);
939 break;
940
941 case UD:
942 size += mthca_is_memfree(dev) ?
943 sizeof (struct mthca_arbel_ud_seg) :
944 sizeof (struct mthca_tavor_ud_seg);
945 break;
946
947 case UC:
948 size += sizeof (struct mthca_raddr_seg);
949 break;
950
951 case RC:
952 size += sizeof (struct mthca_raddr_seg);
953 /*
954 * An atomic op will require an atomic segment, a
955 * remote address segment and one scatter entry.
956 */
957 size = max_t(int, size,
958 sizeof (struct mthca_atomic_seg) +
959 sizeof (struct mthca_raddr_seg) +
960 sizeof (struct mthca_data_seg));
961 break;
962
963 default:
964 break;
965 }
966
967 /* Make sure that we have enough space for a bind request */
968 size = max_t(int, size, sizeof (struct mthca_bind_seg));
969
970 size += sizeof (struct mthca_next_seg);
971
972 if (size > dev->limits.max_desc_sz)
973 return -EINVAL;
974
975 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
976 qp->sq.wqe_shift++)
977 ; /* nothing */
978
979 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
980 1 << qp->sq.wqe_shift);
981
982 /*
983 * If this is a userspace QP, we don't actually have to
984 * allocate anything. All we need is to calculate the WQE
985 * sizes and the send_wqe_offset, so we're done now.
986 */
987 if (pd->ibpd.uobject)
988 return 0;
989
990 size = PAGE_ALIGN(qp->send_wqe_offset +
991 (qp->sq.max << qp->sq.wqe_shift));
992
993 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
994 GFP_KERNEL);
995 if (!qp->wrid)
996 goto err_out;
997
998 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
999 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1000 if (err)
1001 goto err_out;
1002
1003 return 0;
1004
1005 err_out:
1006 kfree(qp->wrid);
1007 return err;
1008 }
1009
1010 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1011 struct mthca_qp *qp)
1012 {
1013 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1014 (qp->sq.max << qp->sq.wqe_shift)),
1015 &qp->queue, qp->is_direct, &qp->mr);
1016 kfree(qp->wrid);
1017 }
1018
1019 static int mthca_map_memfree(struct mthca_dev *dev,
1020 struct mthca_qp *qp)
1021 {
1022 int ret;
1023
1024 if (mthca_is_memfree(dev)) {
1025 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1026 if (ret)
1027 return ret;
1028
1029 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1030 if (ret)
1031 goto err_qpc;
1032
1033 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1034 qp->qpn << dev->qp_table.rdb_shift);
1035 if (ret)
1036 goto err_eqpc;
1037
1038 }
1039
1040 return 0;
1041
1042 err_eqpc:
1043 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1044
1045 err_qpc:
1046 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1047
1048 return ret;
1049 }
1050
1051 static void mthca_unmap_memfree(struct mthca_dev *dev,
1052 struct mthca_qp *qp)
1053 {
1054 mthca_table_put(dev, dev->qp_table.rdb_table,
1055 qp->qpn << dev->qp_table.rdb_shift);
1056 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1057 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1058 }
1059
1060 static int mthca_alloc_memfree(struct mthca_dev *dev,
1061 struct mthca_qp *qp)
1062 {
1063 int ret = 0;
1064
1065 if (mthca_is_memfree(dev)) {
1066 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1067 qp->qpn, &qp->rq.db);
1068 if (qp->rq.db_index < 0)
1069 return ret;
1070
1071 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1072 qp->qpn, &qp->sq.db);
1073 if (qp->sq.db_index < 0)
1074 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1075 }
1076
1077 return ret;
1078 }
1079
1080 static void mthca_free_memfree(struct mthca_dev *dev,
1081 struct mthca_qp *qp)
1082 {
1083 if (mthca_is_memfree(dev)) {
1084 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1085 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1086 }
1087 }
1088
1089 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1090 struct mthca_pd *pd,
1091 struct mthca_cq *send_cq,
1092 struct mthca_cq *recv_cq,
1093 enum ib_sig_type send_policy,
1094 struct mthca_qp *qp)
1095 {
1096 int ret;
1097 int i;
1098
1099 atomic_set(&qp->refcount, 1);
1100 init_waitqueue_head(&qp->wait);
1101 qp->state = IB_QPS_RESET;
1102 qp->atomic_rd_en = 0;
1103 qp->resp_depth = 0;
1104 qp->sq_policy = send_policy;
1105 mthca_wq_init(&qp->sq);
1106 mthca_wq_init(&qp->rq);
1107
1108 ret = mthca_map_memfree(dev, qp);
1109 if (ret)
1110 return ret;
1111
1112 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1113 if (ret) {
1114 mthca_unmap_memfree(dev, qp);
1115 return ret;
1116 }
1117
1118 mthca_adjust_qp_caps(dev, pd, qp);
1119
1120 /*
1121 * If this is a userspace QP, we're done now. The doorbells
1122 * will be allocated and buffers will be initialized in
1123 * userspace.
1124 */
1125 if (pd->ibpd.uobject)
1126 return 0;
1127
1128 ret = mthca_alloc_memfree(dev, qp);
1129 if (ret) {
1130 mthca_free_wqe_buf(dev, qp);
1131 mthca_unmap_memfree(dev, qp);
1132 return ret;
1133 }
1134
1135 if (mthca_is_memfree(dev)) {
1136 struct mthca_next_seg *next;
1137 struct mthca_data_seg *scatter;
1138 int size = (sizeof (struct mthca_next_seg) +
1139 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1140
1141 for (i = 0; i < qp->rq.max; ++i) {
1142 next = get_recv_wqe(qp, i);
1143 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1144 qp->rq.wqe_shift);
1145 next->ee_nds = cpu_to_be32(size);
1146
1147 for (scatter = (void *) (next + 1);
1148 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1149 ++scatter)
1150 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1151 }
1152
1153 for (i = 0; i < qp->sq.max; ++i) {
1154 next = get_send_wqe(qp, i);
1155 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1156 qp->sq.wqe_shift) +
1157 qp->send_wqe_offset);
1158 }
1159 }
1160
1161 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1162 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1163
1164 return 0;
1165 }
1166
1167 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1168 struct mthca_pd *pd, struct mthca_qp *qp)
1169 {
1170 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1171
1172 /* Sanity check QP size before proceeding */
1173 if (cap->max_send_wr > dev->limits.max_wqes ||
1174 cap->max_recv_wr > dev->limits.max_wqes ||
1175 cap->max_send_sge > dev->limits.max_sg ||
1176 cap->max_recv_sge > dev->limits.max_sg ||
1177 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1178 return -EINVAL;
1179
1180 /*
1181 * For MLX transport we need 2 extra S/G entries:
1182 * one for the header and one for the checksum at the end
1183 */
1184 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1185 return -EINVAL;
1186
1187 if (mthca_is_memfree(dev)) {
1188 qp->rq.max = cap->max_recv_wr ?
1189 roundup_pow_of_two(cap->max_recv_wr) : 0;
1190 qp->sq.max = cap->max_send_wr ?
1191 roundup_pow_of_two(cap->max_send_wr) : 0;
1192 } else {
1193 qp->rq.max = cap->max_recv_wr;
1194 qp->sq.max = cap->max_send_wr;
1195 }
1196
1197 qp->rq.max_gs = cap->max_recv_sge;
1198 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1199 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1200 MTHCA_INLINE_CHUNK_SIZE) /
1201 sizeof (struct mthca_data_seg));
1202
1203 return 0;
1204 }
1205
1206 int mthca_alloc_qp(struct mthca_dev *dev,
1207 struct mthca_pd *pd,
1208 struct mthca_cq *send_cq,
1209 struct mthca_cq *recv_cq,
1210 enum ib_qp_type type,
1211 enum ib_sig_type send_policy,
1212 struct ib_qp_cap *cap,
1213 struct mthca_qp *qp)
1214 {
1215 int err;
1216
1217 switch (type) {
1218 case IB_QPT_RC: qp->transport = RC; break;
1219 case IB_QPT_UC: qp->transport = UC; break;
1220 case IB_QPT_UD: qp->transport = UD; break;
1221 default: return -EINVAL;
1222 }
1223
1224 err = mthca_set_qp_size(dev, cap, pd, qp);
1225 if (err)
1226 return err;
1227
1228 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1229 if (qp->qpn == -1)
1230 return -ENOMEM;
1231
1232 /* initialize port to zero for error-catching. */
1233 qp->port = 0;
1234
1235 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1236 send_policy, qp);
1237 if (err) {
1238 mthca_free(&dev->qp_table.alloc, qp->qpn);
1239 return err;
1240 }
1241
1242 spin_lock_irq(&dev->qp_table.lock);
1243 mthca_array_set(&dev->qp_table.qp,
1244 qp->qpn & (dev->limits.num_qps - 1), qp);
1245 spin_unlock_irq(&dev->qp_table.lock);
1246
1247 return 0;
1248 }
1249
1250 int mthca_alloc_sqp(struct mthca_dev *dev,
1251 struct mthca_pd *pd,
1252 struct mthca_cq *send_cq,
1253 struct mthca_cq *recv_cq,
1254 enum ib_sig_type send_policy,
1255 struct ib_qp_cap *cap,
1256 int qpn,
1257 int port,
1258 struct mthca_sqp *sqp)
1259 {
1260 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1261 int err;
1262
1263 sqp->qp.transport = MLX;
1264 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1265 if (err)
1266 return err;
1267
1268 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1269 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1270 &sqp->header_dma, GFP_KERNEL);
1271 if (!sqp->header_buf)
1272 return -ENOMEM;
1273
1274 spin_lock_irq(&dev->qp_table.lock);
1275 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1276 err = -EBUSY;
1277 else
1278 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1279 spin_unlock_irq(&dev->qp_table.lock);
1280
1281 if (err)
1282 goto err_out;
1283
1284 sqp->qp.port = port;
1285 sqp->qp.qpn = mqpn;
1286 sqp->qp.transport = MLX;
1287
1288 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1289 send_policy, &sqp->qp);
1290 if (err)
1291 goto err_out_free;
1292
1293 atomic_inc(&pd->sqp_count);
1294
1295 return 0;
1296
1297 err_out_free:
1298 /*
1299 * Lock CQs here, so that CQ polling code can do QP lookup
1300 * without taking a lock.
1301 */
1302 spin_lock_irq(&send_cq->lock);
1303 if (send_cq != recv_cq)
1304 spin_lock(&recv_cq->lock);
1305
1306 spin_lock(&dev->qp_table.lock);
1307 mthca_array_clear(&dev->qp_table.qp, mqpn);
1308 spin_unlock(&dev->qp_table.lock);
1309
1310 if (send_cq != recv_cq)
1311 spin_unlock(&recv_cq->lock);
1312 spin_unlock_irq(&send_cq->lock);
1313
1314 err_out:
1315 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1316 sqp->header_buf, sqp->header_dma);
1317
1318 return err;
1319 }
1320
1321 void mthca_free_qp(struct mthca_dev *dev,
1322 struct mthca_qp *qp)
1323 {
1324 u8 status;
1325 struct mthca_cq *send_cq;
1326 struct mthca_cq *recv_cq;
1327
1328 send_cq = to_mcq(qp->ibqp.send_cq);
1329 recv_cq = to_mcq(qp->ibqp.recv_cq);
1330
1331 /*
1332 * Lock CQs here, so that CQ polling code can do QP lookup
1333 * without taking a lock.
1334 */
1335 spin_lock_irq(&send_cq->lock);
1336 if (send_cq != recv_cq)
1337 spin_lock(&recv_cq->lock);
1338
1339 spin_lock(&dev->qp_table.lock);
1340 mthca_array_clear(&dev->qp_table.qp,
1341 qp->qpn & (dev->limits.num_qps - 1));
1342 spin_unlock(&dev->qp_table.lock);
1343
1344 if (send_cq != recv_cq)
1345 spin_unlock(&recv_cq->lock);
1346 spin_unlock_irq(&send_cq->lock);
1347
1348 atomic_dec(&qp->refcount);
1349 wait_event(qp->wait, !atomic_read(&qp->refcount));
1350
1351 if (qp->state != IB_QPS_RESET)
1352 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1353 NULL, 0, &status);
1354
1355 /*
1356 * If this is a userspace QP, the buffers, MR, CQs and so on
1357 * will be cleaned up in userspace, so all we have to do is
1358 * unref the mem-free tables and free the QPN in our table.
1359 */
1360 if (!qp->ibqp.uobject) {
1361 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1362 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1363 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1364 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1365 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1366
1367 mthca_free_memfree(dev, qp);
1368 mthca_free_wqe_buf(dev, qp);
1369 }
1370
1371 mthca_unmap_memfree(dev, qp);
1372
1373 if (is_sqp(dev, qp)) {
1374 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1375 dma_free_coherent(&dev->pdev->dev,
1376 to_msqp(qp)->header_buf_size,
1377 to_msqp(qp)->header_buf,
1378 to_msqp(qp)->header_dma);
1379 } else
1380 mthca_free(&dev->qp_table.alloc, qp->qpn);
1381 }
1382
1383 /* Create UD header for an MLX send and build a data segment for it */
1384 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1385 int ind, struct ib_send_wr *wr,
1386 struct mthca_mlx_seg *mlx,
1387 struct mthca_data_seg *data)
1388 {
1389 int header_size;
1390 int err;
1391 u16 pkey;
1392
1393 ib_ud_header_init(256, /* assume a MAD */
1394 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1395 &sqp->ud_header);
1396
1397 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1398 if (err)
1399 return err;
1400 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1401 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1402 (sqp->ud_header.lrh.destination_lid ==
1403 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1404 (sqp->ud_header.lrh.service_level << 8));
1405 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1406 mlx->vcrc = 0;
1407
1408 switch (wr->opcode) {
1409 case IB_WR_SEND:
1410 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1411 sqp->ud_header.immediate_present = 0;
1412 break;
1413 case IB_WR_SEND_WITH_IMM:
1414 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1415 sqp->ud_header.immediate_present = 1;
1416 sqp->ud_header.immediate_data = wr->imm_data;
1417 break;
1418 default:
1419 return -EINVAL;
1420 }
1421
1422 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1423 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1424 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1425 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1426 if (!sqp->qp.ibqp.qp_num)
1427 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1428 sqp->pkey_index, &pkey);
1429 else
1430 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1431 wr->wr.ud.pkey_index, &pkey);
1432 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1433 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1434 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1435 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1436 sqp->qkey : wr->wr.ud.remote_qkey);
1437 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1438
1439 header_size = ib_ud_header_pack(&sqp->ud_header,
1440 sqp->header_buf +
1441 ind * MTHCA_UD_HEADER_SIZE);
1442
1443 data->byte_count = cpu_to_be32(header_size);
1444 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1445 data->addr = cpu_to_be64(sqp->header_dma +
1446 ind * MTHCA_UD_HEADER_SIZE);
1447
1448 return 0;
1449 }
1450
1451 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1452 struct ib_cq *ib_cq)
1453 {
1454 unsigned cur;
1455 struct mthca_cq *cq;
1456
1457 cur = wq->head - wq->tail;
1458 if (likely(cur + nreq < wq->max))
1459 return 0;
1460
1461 cq = to_mcq(ib_cq);
1462 spin_lock(&cq->lock);
1463 cur = wq->head - wq->tail;
1464 spin_unlock(&cq->lock);
1465
1466 return cur + nreq >= wq->max;
1467 }
1468
1469 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1470 struct ib_send_wr **bad_wr)
1471 {
1472 struct mthca_dev *dev = to_mdev(ibqp->device);
1473 struct mthca_qp *qp = to_mqp(ibqp);
1474 void *wqe;
1475 void *prev_wqe;
1476 unsigned long flags;
1477 int err = 0;
1478 int nreq;
1479 int i;
1480 int size;
1481 int size0 = 0;
1482 u32 f0 = 0;
1483 int ind;
1484 u8 op0 = 0;
1485
1486 spin_lock_irqsave(&qp->sq.lock, flags);
1487
1488 /* XXX check that state is OK to post send */
1489
1490 ind = qp->sq.next_ind;
1491
1492 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1493 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1494 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1495 " %d max, %d nreq)\n", qp->qpn,
1496 qp->sq.head, qp->sq.tail,
1497 qp->sq.max, nreq);
1498 err = -ENOMEM;
1499 *bad_wr = wr;
1500 goto out;
1501 }
1502
1503 wqe = get_send_wqe(qp, ind);
1504 prev_wqe = qp->sq.last;
1505 qp->sq.last = wqe;
1506
1507 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1508 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1509 ((struct mthca_next_seg *) wqe)->flags =
1510 ((wr->send_flags & IB_SEND_SIGNALED) ?
1511 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1512 ((wr->send_flags & IB_SEND_SOLICITED) ?
1513 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1514 cpu_to_be32(1);
1515 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1516 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1517 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1518
1519 wqe += sizeof (struct mthca_next_seg);
1520 size = sizeof (struct mthca_next_seg) / 16;
1521
1522 switch (qp->transport) {
1523 case RC:
1524 switch (wr->opcode) {
1525 case IB_WR_ATOMIC_CMP_AND_SWP:
1526 case IB_WR_ATOMIC_FETCH_AND_ADD:
1527 ((struct mthca_raddr_seg *) wqe)->raddr =
1528 cpu_to_be64(wr->wr.atomic.remote_addr);
1529 ((struct mthca_raddr_seg *) wqe)->rkey =
1530 cpu_to_be32(wr->wr.atomic.rkey);
1531 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1532
1533 wqe += sizeof (struct mthca_raddr_seg);
1534
1535 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1536 ((struct mthca_atomic_seg *) wqe)->swap_add =
1537 cpu_to_be64(wr->wr.atomic.swap);
1538 ((struct mthca_atomic_seg *) wqe)->compare =
1539 cpu_to_be64(wr->wr.atomic.compare_add);
1540 } else {
1541 ((struct mthca_atomic_seg *) wqe)->swap_add =
1542 cpu_to_be64(wr->wr.atomic.compare_add);
1543 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1544 }
1545
1546 wqe += sizeof (struct mthca_atomic_seg);
1547 size += (sizeof (struct mthca_raddr_seg) +
1548 sizeof (struct mthca_atomic_seg)) / 16;
1549 break;
1550
1551 case IB_WR_RDMA_WRITE:
1552 case IB_WR_RDMA_WRITE_WITH_IMM:
1553 case IB_WR_RDMA_READ:
1554 ((struct mthca_raddr_seg *) wqe)->raddr =
1555 cpu_to_be64(wr->wr.rdma.remote_addr);
1556 ((struct mthca_raddr_seg *) wqe)->rkey =
1557 cpu_to_be32(wr->wr.rdma.rkey);
1558 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1559 wqe += sizeof (struct mthca_raddr_seg);
1560 size += sizeof (struct mthca_raddr_seg) / 16;
1561 break;
1562
1563 default:
1564 /* No extra segments required for sends */
1565 break;
1566 }
1567
1568 break;
1569
1570 case UC:
1571 switch (wr->opcode) {
1572 case IB_WR_RDMA_WRITE:
1573 case IB_WR_RDMA_WRITE_WITH_IMM:
1574 ((struct mthca_raddr_seg *) wqe)->raddr =
1575 cpu_to_be64(wr->wr.rdma.remote_addr);
1576 ((struct mthca_raddr_seg *) wqe)->rkey =
1577 cpu_to_be32(wr->wr.rdma.rkey);
1578 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1579 wqe += sizeof (struct mthca_raddr_seg);
1580 size += sizeof (struct mthca_raddr_seg) / 16;
1581 break;
1582
1583 default:
1584 /* No extra segments required for sends */
1585 break;
1586 }
1587
1588 break;
1589
1590 case UD:
1591 ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1592 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1593 ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1594 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1595 ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1596 cpu_to_be32(wr->wr.ud.remote_qpn);
1597 ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1598 cpu_to_be32(wr->wr.ud.remote_qkey);
1599
1600 wqe += sizeof (struct mthca_tavor_ud_seg);
1601 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1602 break;
1603
1604 case MLX:
1605 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1606 wqe - sizeof (struct mthca_next_seg),
1607 wqe);
1608 if (err) {
1609 *bad_wr = wr;
1610 goto out;
1611 }
1612 wqe += sizeof (struct mthca_data_seg);
1613 size += sizeof (struct mthca_data_seg) / 16;
1614 break;
1615 }
1616
1617 if (wr->num_sge > qp->sq.max_gs) {
1618 mthca_err(dev, "too many gathers\n");
1619 err = -EINVAL;
1620 *bad_wr = wr;
1621 goto out;
1622 }
1623
1624 for (i = 0; i < wr->num_sge; ++i) {
1625 ((struct mthca_data_seg *) wqe)->byte_count =
1626 cpu_to_be32(wr->sg_list[i].length);
1627 ((struct mthca_data_seg *) wqe)->lkey =
1628 cpu_to_be32(wr->sg_list[i].lkey);
1629 ((struct mthca_data_seg *) wqe)->addr =
1630 cpu_to_be64(wr->sg_list[i].addr);
1631 wqe += sizeof (struct mthca_data_seg);
1632 size += sizeof (struct mthca_data_seg) / 16;
1633 }
1634
1635 /* Add one more inline data segment for ICRC */
1636 if (qp->transport == MLX) {
1637 ((struct mthca_data_seg *) wqe)->byte_count =
1638 cpu_to_be32((1 << 31) | 4);
1639 ((u32 *) wqe)[1] = 0;
1640 wqe += sizeof (struct mthca_data_seg);
1641 size += sizeof (struct mthca_data_seg) / 16;
1642 }
1643
1644 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1645
1646 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1647 mthca_err(dev, "opcode invalid\n");
1648 err = -EINVAL;
1649 *bad_wr = wr;
1650 goto out;
1651 }
1652
1653 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1654 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1655 qp->send_wqe_offset) |
1656 mthca_opcode[wr->opcode]);
1657 wmb();
1658 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1659 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1660 ((wr->send_flags & IB_SEND_FENCE) ?
1661 MTHCA_NEXT_FENCE : 0));
1662
1663 if (!size0) {
1664 size0 = size;
1665 op0 = mthca_opcode[wr->opcode];
1666 }
1667
1668 ++ind;
1669 if (unlikely(ind >= qp->sq.max))
1670 ind -= qp->sq.max;
1671 }
1672
1673 out:
1674 if (likely(nreq)) {
1675 __be32 doorbell[2];
1676
1677 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1678 qp->send_wqe_offset) | f0 | op0);
1679 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1680
1681 wmb();
1682
1683 mthca_write64(doorbell,
1684 dev->kar + MTHCA_SEND_DOORBELL,
1685 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1686 }
1687
1688 qp->sq.next_ind = ind;
1689 qp->sq.head += nreq;
1690
1691 spin_unlock_irqrestore(&qp->sq.lock, flags);
1692 return err;
1693 }
1694
1695 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1696 struct ib_recv_wr **bad_wr)
1697 {
1698 struct mthca_dev *dev = to_mdev(ibqp->device);
1699 struct mthca_qp *qp = to_mqp(ibqp);
1700 __be32 doorbell[2];
1701 unsigned long flags;
1702 int err = 0;
1703 int nreq;
1704 int i;
1705 int size;
1706 int size0 = 0;
1707 int ind;
1708 void *wqe;
1709 void *prev_wqe;
1710
1711 spin_lock_irqsave(&qp->rq.lock, flags);
1712
1713 /* XXX check that state is OK to post receive */
1714
1715 ind = qp->rq.next_ind;
1716
1717 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1718 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1719 nreq = 0;
1720
1721 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1722 doorbell[1] = cpu_to_be32(qp->qpn << 8);
1723
1724 wmb();
1725
1726 mthca_write64(doorbell,
1727 dev->kar + MTHCA_RECEIVE_DOORBELL,
1728 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1729
1730 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1731 size0 = 0;
1732 }
1733
1734 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1735 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1736 " %d max, %d nreq)\n", qp->qpn,
1737 qp->rq.head, qp->rq.tail,
1738 qp->rq.max, nreq);
1739 err = -ENOMEM;
1740 *bad_wr = wr;
1741 goto out;
1742 }
1743
1744 wqe = get_recv_wqe(qp, ind);
1745 prev_wqe = qp->rq.last;
1746 qp->rq.last = wqe;
1747
1748 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1749 ((struct mthca_next_seg *) wqe)->ee_nds =
1750 cpu_to_be32(MTHCA_NEXT_DBD);
1751 ((struct mthca_next_seg *) wqe)->flags = 0;
1752
1753 wqe += sizeof (struct mthca_next_seg);
1754 size = sizeof (struct mthca_next_seg) / 16;
1755
1756 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1757 err = -EINVAL;
1758 *bad_wr = wr;
1759 goto out;
1760 }
1761
1762 for (i = 0; i < wr->num_sge; ++i) {
1763 ((struct mthca_data_seg *) wqe)->byte_count =
1764 cpu_to_be32(wr->sg_list[i].length);
1765 ((struct mthca_data_seg *) wqe)->lkey =
1766 cpu_to_be32(wr->sg_list[i].lkey);
1767 ((struct mthca_data_seg *) wqe)->addr =
1768 cpu_to_be64(wr->sg_list[i].addr);
1769 wqe += sizeof (struct mthca_data_seg);
1770 size += sizeof (struct mthca_data_seg) / 16;
1771 }
1772
1773 qp->wrid[ind] = wr->wr_id;
1774
1775 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1776 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1777 wmb();
1778 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1779 cpu_to_be32(MTHCA_NEXT_DBD | size);
1780
1781 if (!size0)
1782 size0 = size;
1783
1784 ++ind;
1785 if (unlikely(ind >= qp->rq.max))
1786 ind -= qp->rq.max;
1787 }
1788
1789 out:
1790 if (likely(nreq)) {
1791 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1792 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1793
1794 wmb();
1795
1796 mthca_write64(doorbell,
1797 dev->kar + MTHCA_RECEIVE_DOORBELL,
1798 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1799 }
1800
1801 qp->rq.next_ind = ind;
1802 qp->rq.head += nreq;
1803
1804 spin_unlock_irqrestore(&qp->rq.lock, flags);
1805 return err;
1806 }
1807
1808 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1809 struct ib_send_wr **bad_wr)
1810 {
1811 struct mthca_dev *dev = to_mdev(ibqp->device);
1812 struct mthca_qp *qp = to_mqp(ibqp);
1813 __be32 doorbell[2];
1814 void *wqe;
1815 void *prev_wqe;
1816 unsigned long flags;
1817 int err = 0;
1818 int nreq;
1819 int i;
1820 int size;
1821 int size0 = 0;
1822 u32 f0 = 0;
1823 int ind;
1824 u8 op0 = 0;
1825
1826 spin_lock_irqsave(&qp->sq.lock, flags);
1827
1828 /* XXX check that state is OK to post send */
1829
1830 ind = qp->sq.head & (qp->sq.max - 1);
1831
1832 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1833 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1834 nreq = 0;
1835
1836 doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1837 ((qp->sq.head & 0xffff) << 8) |
1838 f0 | op0);
1839 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1840
1841 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1842 size0 = 0;
1843
1844 /*
1845 * Make sure that descriptors are written before
1846 * doorbell record.
1847 */
1848 wmb();
1849 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1850
1851 /*
1852 * Make sure doorbell record is written before we
1853 * write MMIO send doorbell.
1854 */
1855 wmb();
1856 mthca_write64(doorbell,
1857 dev->kar + MTHCA_SEND_DOORBELL,
1858 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1859 }
1860
1861 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1862 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1863 " %d max, %d nreq)\n", qp->qpn,
1864 qp->sq.head, qp->sq.tail,
1865 qp->sq.max, nreq);
1866 err = -ENOMEM;
1867 *bad_wr = wr;
1868 goto out;
1869 }
1870
1871 wqe = get_send_wqe(qp, ind);
1872 prev_wqe = qp->sq.last;
1873 qp->sq.last = wqe;
1874
1875 ((struct mthca_next_seg *) wqe)->flags =
1876 ((wr->send_flags & IB_SEND_SIGNALED) ?
1877 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1878 ((wr->send_flags & IB_SEND_SOLICITED) ?
1879 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1880 cpu_to_be32(1);
1881 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1882 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1883 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1884
1885 wqe += sizeof (struct mthca_next_seg);
1886 size = sizeof (struct mthca_next_seg) / 16;
1887
1888 switch (qp->transport) {
1889 case RC:
1890 switch (wr->opcode) {
1891 case IB_WR_ATOMIC_CMP_AND_SWP:
1892 case IB_WR_ATOMIC_FETCH_AND_ADD:
1893 ((struct mthca_raddr_seg *) wqe)->raddr =
1894 cpu_to_be64(wr->wr.atomic.remote_addr);
1895 ((struct mthca_raddr_seg *) wqe)->rkey =
1896 cpu_to_be32(wr->wr.atomic.rkey);
1897 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1898
1899 wqe += sizeof (struct mthca_raddr_seg);
1900
1901 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1902 ((struct mthca_atomic_seg *) wqe)->swap_add =
1903 cpu_to_be64(wr->wr.atomic.swap);
1904 ((struct mthca_atomic_seg *) wqe)->compare =
1905 cpu_to_be64(wr->wr.atomic.compare_add);
1906 } else {
1907 ((struct mthca_atomic_seg *) wqe)->swap_add =
1908 cpu_to_be64(wr->wr.atomic.compare_add);
1909 ((struct mthca_atomic_seg *) wqe)->compare = 0;
1910 }
1911
1912 wqe += sizeof (struct mthca_atomic_seg);
1913 size += (sizeof (struct mthca_raddr_seg) +
1914 sizeof (struct mthca_atomic_seg)) / 16;
1915 break;
1916
1917 case IB_WR_RDMA_READ:
1918 case IB_WR_RDMA_WRITE:
1919 case IB_WR_RDMA_WRITE_WITH_IMM:
1920 ((struct mthca_raddr_seg *) wqe)->raddr =
1921 cpu_to_be64(wr->wr.rdma.remote_addr);
1922 ((struct mthca_raddr_seg *) wqe)->rkey =
1923 cpu_to_be32(wr->wr.rdma.rkey);
1924 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1925 wqe += sizeof (struct mthca_raddr_seg);
1926 size += sizeof (struct mthca_raddr_seg) / 16;
1927 break;
1928
1929 default:
1930 /* No extra segments required for sends */
1931 break;
1932 }
1933
1934 break;
1935
1936 case UC:
1937 switch (wr->opcode) {
1938 case IB_WR_RDMA_WRITE:
1939 case IB_WR_RDMA_WRITE_WITH_IMM:
1940 ((struct mthca_raddr_seg *) wqe)->raddr =
1941 cpu_to_be64(wr->wr.rdma.remote_addr);
1942 ((struct mthca_raddr_seg *) wqe)->rkey =
1943 cpu_to_be32(wr->wr.rdma.rkey);
1944 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1945 wqe += sizeof (struct mthca_raddr_seg);
1946 size += sizeof (struct mthca_raddr_seg) / 16;
1947 break;
1948
1949 default:
1950 /* No extra segments required for sends */
1951 break;
1952 }
1953
1954 break;
1955
1956 case UD:
1957 memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1958 to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1959 ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1960 cpu_to_be32(wr->wr.ud.remote_qpn);
1961 ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1962 cpu_to_be32(wr->wr.ud.remote_qkey);
1963
1964 wqe += sizeof (struct mthca_arbel_ud_seg);
1965 size += sizeof (struct mthca_arbel_ud_seg) / 16;
1966 break;
1967
1968 case MLX:
1969 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1970 wqe - sizeof (struct mthca_next_seg),
1971 wqe);
1972 if (err) {
1973 *bad_wr = wr;
1974 goto out;
1975 }
1976 wqe += sizeof (struct mthca_data_seg);
1977 size += sizeof (struct mthca_data_seg) / 16;
1978 break;
1979 }
1980
1981 if (wr->num_sge > qp->sq.max_gs) {
1982 mthca_err(dev, "too many gathers\n");
1983 err = -EINVAL;
1984 *bad_wr = wr;
1985 goto out;
1986 }
1987
1988 for (i = 0; i < wr->num_sge; ++i) {
1989 ((struct mthca_data_seg *) wqe)->byte_count =
1990 cpu_to_be32(wr->sg_list[i].length);
1991 ((struct mthca_data_seg *) wqe)->lkey =
1992 cpu_to_be32(wr->sg_list[i].lkey);
1993 ((struct mthca_data_seg *) wqe)->addr =
1994 cpu_to_be64(wr->sg_list[i].addr);
1995 wqe += sizeof (struct mthca_data_seg);
1996 size += sizeof (struct mthca_data_seg) / 16;
1997 }
1998
1999 /* Add one more inline data segment for ICRC */
2000 if (qp->transport == MLX) {
2001 ((struct mthca_data_seg *) wqe)->byte_count =
2002 cpu_to_be32((1 << 31) | 4);
2003 ((u32 *) wqe)[1] = 0;
2004 wqe += sizeof (struct mthca_data_seg);
2005 size += sizeof (struct mthca_data_seg) / 16;
2006 }
2007
2008 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2009
2010 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2011 mthca_err(dev, "opcode invalid\n");
2012 err = -EINVAL;
2013 *bad_wr = wr;
2014 goto out;
2015 }
2016
2017 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2018 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2019 qp->send_wqe_offset) |
2020 mthca_opcode[wr->opcode]);
2021 wmb();
2022 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2023 cpu_to_be32(MTHCA_NEXT_DBD | size |
2024 ((wr->send_flags & IB_SEND_FENCE) ?
2025 MTHCA_NEXT_FENCE : 0));
2026
2027 if (!size0) {
2028 size0 = size;
2029 op0 = mthca_opcode[wr->opcode];
2030 }
2031
2032 ++ind;
2033 if (unlikely(ind >= qp->sq.max))
2034 ind -= qp->sq.max;
2035 }
2036
2037 out:
2038 if (likely(nreq)) {
2039 doorbell[0] = cpu_to_be32((nreq << 24) |
2040 ((qp->sq.head & 0xffff) << 8) |
2041 f0 | op0);
2042 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2043
2044 qp->sq.head += nreq;
2045
2046 /*
2047 * Make sure that descriptors are written before
2048 * doorbell record.
2049 */
2050 wmb();
2051 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2052
2053 /*
2054 * Make sure doorbell record is written before we
2055 * write MMIO send doorbell.
2056 */
2057 wmb();
2058 mthca_write64(doorbell,
2059 dev->kar + MTHCA_SEND_DOORBELL,
2060 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2061 }
2062
2063 spin_unlock_irqrestore(&qp->sq.lock, flags);
2064 return err;
2065 }
2066
2067 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2068 struct ib_recv_wr **bad_wr)
2069 {
2070 struct mthca_dev *dev = to_mdev(ibqp->device);
2071 struct mthca_qp *qp = to_mqp(ibqp);
2072 unsigned long flags;
2073 int err = 0;
2074 int nreq;
2075 int ind;
2076 int i;
2077 void *wqe;
2078
2079 spin_lock_irqsave(&qp->rq.lock, flags);
2080
2081 /* XXX check that state is OK to post receive */
2082
2083 ind = qp->rq.head & (qp->rq.max - 1);
2084
2085 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2086 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2087 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2088 " %d max, %d nreq)\n", qp->qpn,
2089 qp->rq.head, qp->rq.tail,
2090 qp->rq.max, nreq);
2091 err = -ENOMEM;
2092 *bad_wr = wr;
2093 goto out;
2094 }
2095
2096 wqe = get_recv_wqe(qp, ind);
2097
2098 ((struct mthca_next_seg *) wqe)->flags = 0;
2099
2100 wqe += sizeof (struct mthca_next_seg);
2101
2102 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2103 err = -EINVAL;
2104 *bad_wr = wr;
2105 goto out;
2106 }
2107
2108 for (i = 0; i < wr->num_sge; ++i) {
2109 ((struct mthca_data_seg *) wqe)->byte_count =
2110 cpu_to_be32(wr->sg_list[i].length);
2111 ((struct mthca_data_seg *) wqe)->lkey =
2112 cpu_to_be32(wr->sg_list[i].lkey);
2113 ((struct mthca_data_seg *) wqe)->addr =
2114 cpu_to_be64(wr->sg_list[i].addr);
2115 wqe += sizeof (struct mthca_data_seg);
2116 }
2117
2118 if (i < qp->rq.max_gs) {
2119 ((struct mthca_data_seg *) wqe)->byte_count = 0;
2120 ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2121 ((struct mthca_data_seg *) wqe)->addr = 0;
2122 }
2123
2124 qp->wrid[ind] = wr->wr_id;
2125
2126 ++ind;
2127 if (unlikely(ind >= qp->rq.max))
2128 ind -= qp->rq.max;
2129 }
2130 out:
2131 if (likely(nreq)) {
2132 qp->rq.head += nreq;
2133
2134 /*
2135 * Make sure that descriptors are written before
2136 * doorbell record.
2137 */
2138 wmb();
2139 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2140 }
2141
2142 spin_unlock_irqrestore(&qp->rq.lock, flags);
2143 return err;
2144 }
2145
2146 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2147 int index, int *dbd, __be32 *new_wqe)
2148 {
2149 struct mthca_next_seg *next;
2150
2151 /*
2152 * For SRQs, all WQEs generate a CQE, so we're always at the
2153 * end of the doorbell chain.
2154 */
2155 if (qp->ibqp.srq) {
2156 *new_wqe = 0;
2157 return;
2158 }
2159
2160 if (is_send)
2161 next = get_send_wqe(qp, index);
2162 else
2163 next = get_recv_wqe(qp, index);
2164
2165 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2166 if (next->ee_nds & cpu_to_be32(0x3f))
2167 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2168 (next->ee_nds & cpu_to_be32(0x3f));
2169 else
2170 *new_wqe = 0;
2171 }
2172
2173 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2174 {
2175 int err;
2176 u8 status;
2177 int i;
2178
2179 spin_lock_init(&dev->qp_table.lock);
2180
2181 /*
2182 * We reserve 2 extra QPs per port for the special QPs. The
2183 * special QP for port 1 has to be even, so round up.
2184 */
2185 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2186 err = mthca_alloc_init(&dev->qp_table.alloc,
2187 dev->limits.num_qps,
2188 (1 << 24) - 1,
2189 dev->qp_table.sqp_start +
2190 MTHCA_MAX_PORTS * 2);
2191 if (err)
2192 return err;
2193
2194 err = mthca_array_init(&dev->qp_table.qp,
2195 dev->limits.num_qps);
2196 if (err) {
2197 mthca_alloc_cleanup(&dev->qp_table.alloc);
2198 return err;
2199 }
2200
2201 for (i = 0; i < 2; ++i) {
2202 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2203 dev->qp_table.sqp_start + i * 2,
2204 &status);
2205 if (err)
2206 goto err_out;
2207 if (status) {
2208 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2209 "status %02x, aborting.\n",
2210 status);
2211 err = -EINVAL;
2212 goto err_out;
2213 }
2214 }
2215 return 0;
2216
2217 err_out:
2218 for (i = 0; i < 2; ++i)
2219 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2220
2221 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2222 mthca_alloc_cleanup(&dev->qp_table.alloc);
2223
2224 return err;
2225 }
2226
2227 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2228 {
2229 int i;
2230 u8 status;
2231
2232 for (i = 0; i < 2; ++i)
2233 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2234
2235 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2236 mthca_alloc_cleanup(&dev->qp_table.alloc);
2237 }
Linux kernel - Deliverables
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