2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
52 MTHCA_MAX_DIRECT_QP_SIZE
= 4 * PAGE_SIZE
,
53 MTHCA_ACK_REQ_FREQ
= 10,
54 MTHCA_FLIGHT_LIMIT
= 9,
55 MTHCA_UD_HEADER_SIZE
= 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE
= 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE
= 16 /* inline data segment chunk */
61 MTHCA_QP_STATE_RST
= 0,
62 MTHCA_QP_STATE_INIT
= 1,
63 MTHCA_QP_STATE_RTR
= 2,
64 MTHCA_QP_STATE_RTS
= 3,
65 MTHCA_QP_STATE_SQE
= 4,
66 MTHCA_QP_STATE_SQD
= 5,
67 MTHCA_QP_STATE_ERR
= 6,
68 MTHCA_QP_STATE_DRAINING
= 7
80 MTHCA_QP_PM_MIGRATED
= 0x3,
81 MTHCA_QP_PM_ARMED
= 0x0,
82 MTHCA_QP_PM_REARM
= 0x1
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE
= 1 << 8,
89 MTHCA_QP_BIT_SRE
= 1 << 15,
90 MTHCA_QP_BIT_SWE
= 1 << 14,
91 MTHCA_QP_BIT_SAE
= 1 << 13,
92 MTHCA_QP_BIT_SIC
= 1 << 4,
93 MTHCA_QP_BIT_SSC
= 1 << 3,
95 MTHCA_QP_BIT_RRE
= 1 << 15,
96 MTHCA_QP_BIT_RWE
= 1 << 14,
97 MTHCA_QP_BIT_RAE
= 1 << 13,
98 MTHCA_QP_BIT_RIC
= 1 << 4,
99 MTHCA_QP_BIT_RSC
= 1 << 3
102 struct mthca_qp_path
{
111 __be32 sl_tclass_flowlabel
;
113 } __attribute__((packed
));
115 struct mthca_qp_context
{
117 __be32 tavor_sched_queue
; /* Reserved on Arbel */
119 u8 rq_size_stride
; /* Reserved on Tavor */
120 u8 sq_size_stride
; /* Reserved on Tavor */
121 u8 rlkey_arbel_sched_queue
; /* Reserved on Tavor */
126 struct mthca_qp_path pri_path
;
127 struct mthca_qp_path alt_path
;
134 __be32 next_send_psn
;
136 __be32 snd_wqe_base_l
; /* Next send WQE on Tavor */
137 __be32 snd_db_index
; /* (debugging only entries) */
138 __be32 last_acked_psn
;
141 __be32 rnr_nextrecvpsn
;
144 __be32 rcv_wqe_base_l
; /* Next recv WQE on Tavor */
145 __be32 rcv_db_index
; /* (debugging only entries) */
149 __be16 rq_wqe_counter
; /* reserved on Tavor */
150 __be16 sq_wqe_counter
; /* reserved on Tavor */
152 } __attribute__((packed
));
154 struct mthca_qp_param
{
155 __be32 opt_param_mask
;
157 struct mthca_qp_context context
;
159 } __attribute__((packed
));
162 MTHCA_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
163 MTHCA_QP_OPTPAR_RRE
= 1 << 1,
164 MTHCA_QP_OPTPAR_RAE
= 1 << 2,
165 MTHCA_QP_OPTPAR_RWE
= 1 << 3,
166 MTHCA_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
167 MTHCA_QP_OPTPAR_Q_KEY
= 1 << 5,
168 MTHCA_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
169 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
170 MTHCA_QP_OPTPAR_SRA_MAX
= 1 << 8,
171 MTHCA_QP_OPTPAR_RRA_MAX
= 1 << 9,
172 MTHCA_QP_OPTPAR_PM_STATE
= 1 << 10,
173 MTHCA_QP_OPTPAR_PORT_NUM
= 1 << 11,
174 MTHCA_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
175 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
= 1 << 13,
176 MTHCA_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
177 MTHCA_QP_OPTPAR_RNR_RETRY
= 1 << 15,
178 MTHCA_QP_OPTPAR_SCHED_QUEUE
= 1 << 16
181 static const u8 mthca_opcode
[] = {
182 [IB_WR_SEND
] = MTHCA_OPCODE_SEND
,
183 [IB_WR_SEND_WITH_IMM
] = MTHCA_OPCODE_SEND_IMM
,
184 [IB_WR_RDMA_WRITE
] = MTHCA_OPCODE_RDMA_WRITE
,
185 [IB_WR_RDMA_WRITE_WITH_IMM
] = MTHCA_OPCODE_RDMA_WRITE_IMM
,
186 [IB_WR_RDMA_READ
] = MTHCA_OPCODE_RDMA_READ
,
187 [IB_WR_ATOMIC_CMP_AND_SWP
] = MTHCA_OPCODE_ATOMIC_CS
,
188 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MTHCA_OPCODE_ATOMIC_FA
,
191 static int is_sqp(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
193 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
194 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 3;
197 static int is_qp0(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
199 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
200 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 1;
203 static void *get_recv_wqe(struct mthca_qp
*qp
, int n
)
206 return qp
->queue
.direct
.buf
+ (n
<< qp
->rq
.wqe_shift
);
208 return qp
->queue
.page_list
[(n
<< qp
->rq
.wqe_shift
) >> PAGE_SHIFT
].buf
+
209 ((n
<< qp
->rq
.wqe_shift
) & (PAGE_SIZE
- 1));
212 static void *get_send_wqe(struct mthca_qp
*qp
, int n
)
215 return qp
->queue
.direct
.buf
+ qp
->send_wqe_offset
+
216 (n
<< qp
->sq
.wqe_shift
);
218 return qp
->queue
.page_list
[(qp
->send_wqe_offset
+
219 (n
<< qp
->sq
.wqe_shift
)) >>
221 ((qp
->send_wqe_offset
+ (n
<< qp
->sq
.wqe_shift
)) &
225 static void mthca_wq_init(struct mthca_wq
*wq
)
227 spin_lock_init(&wq
->lock
);
229 wq
->last_comp
= wq
->max
- 1;
234 void mthca_qp_event(struct mthca_dev
*dev
, u32 qpn
,
235 enum ib_event_type event_type
)
238 struct ib_event event
;
240 spin_lock(&dev
->qp_table
.lock
);
241 qp
= mthca_array_get(&dev
->qp_table
.qp
, qpn
& (dev
->limits
.num_qps
- 1));
243 atomic_inc(&qp
->refcount
);
244 spin_unlock(&dev
->qp_table
.lock
);
247 mthca_warn(dev
, "Async event for bogus QP %08x\n", qpn
);
251 event
.device
= &dev
->ib_dev
;
252 event
.event
= event_type
;
253 event
.element
.qp
= &qp
->ibqp
;
254 if (qp
->ibqp
.event_handler
)
255 qp
->ibqp
.event_handler(&event
, qp
->ibqp
.qp_context
);
257 if (atomic_dec_and_test(&qp
->refcount
))
261 static int to_mthca_state(enum ib_qp_state ib_state
)
264 case IB_QPS_RESET
: return MTHCA_QP_STATE_RST
;
265 case IB_QPS_INIT
: return MTHCA_QP_STATE_INIT
;
266 case IB_QPS_RTR
: return MTHCA_QP_STATE_RTR
;
267 case IB_QPS_RTS
: return MTHCA_QP_STATE_RTS
;
268 case IB_QPS_SQD
: return MTHCA_QP_STATE_SQD
;
269 case IB_QPS_SQE
: return MTHCA_QP_STATE_SQE
;
270 case IB_QPS_ERR
: return MTHCA_QP_STATE_ERR
;
275 enum { RC
, UC
, UD
, RD
, RDEE
, MLX
, NUM_TRANS
};
277 static int to_mthca_st(int transport
)
280 case RC
: return MTHCA_QP_ST_RC
;
281 case UC
: return MTHCA_QP_ST_UC
;
282 case UD
: return MTHCA_QP_ST_UD
;
283 case RD
: return MTHCA_QP_ST_RD
;
284 case MLX
: return MTHCA_QP_ST_MLX
;
289 static void store_attrs(struct mthca_sqp
*sqp
, struct ib_qp_attr
*attr
,
292 if (attr_mask
& IB_QP_PKEY_INDEX
)
293 sqp
->pkey_index
= attr
->pkey_index
;
294 if (attr_mask
& IB_QP_QKEY
)
295 sqp
->qkey
= attr
->qkey
;
296 if (attr_mask
& IB_QP_SQ_PSN
)
297 sqp
->send_psn
= attr
->sq_psn
;
300 static void init_port(struct mthca_dev
*dev
, int port
)
304 struct mthca_init_ib_param param
;
306 memset(¶m
, 0, sizeof param
);
308 param
.port_width
= dev
->limits
.port_width_cap
;
309 param
.vl_cap
= dev
->limits
.vl_cap
;
310 param
.mtu_cap
= dev
->limits
.mtu_cap
;
311 param
.gid_cap
= dev
->limits
.gid_table_len
;
312 param
.pkey_cap
= dev
->limits
.pkey_table_len
;
314 err
= mthca_INIT_IB(dev
, ¶m
, port
, &status
);
316 mthca_warn(dev
, "INIT_IB failed, return code %d.\n", err
);
318 mthca_warn(dev
, "INIT_IB returned status %02x.\n", status
);
321 static __be32
get_hw_access_flags(struct mthca_qp
*qp
, struct ib_qp_attr
*attr
,
326 u32 hw_access_flags
= 0;
328 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
329 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
331 dest_rd_atomic
= qp
->resp_depth
;
333 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
334 access_flags
= attr
->qp_access_flags
;
336 access_flags
= qp
->atomic_rd_en
;
339 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
341 if (access_flags
& IB_ACCESS_REMOTE_READ
)
342 hw_access_flags
|= MTHCA_QP_BIT_RRE
;
343 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
344 hw_access_flags
|= MTHCA_QP_BIT_RAE
;
345 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
346 hw_access_flags
|= MTHCA_QP_BIT_RWE
;
348 return cpu_to_be32(hw_access_flags
);
351 static inline enum ib_qp_state
to_ib_qp_state(int mthca_state
)
353 switch (mthca_state
) {
354 case MTHCA_QP_STATE_RST
: return IB_QPS_RESET
;
355 case MTHCA_QP_STATE_INIT
: return IB_QPS_INIT
;
356 case MTHCA_QP_STATE_RTR
: return IB_QPS_RTR
;
357 case MTHCA_QP_STATE_RTS
: return IB_QPS_RTS
;
358 case MTHCA_QP_STATE_DRAINING
:
359 case MTHCA_QP_STATE_SQD
: return IB_QPS_SQD
;
360 case MTHCA_QP_STATE_SQE
: return IB_QPS_SQE
;
361 case MTHCA_QP_STATE_ERR
: return IB_QPS_ERR
;
366 static inline enum ib_mig_state
to_ib_mig_state(int mthca_mig_state
)
368 switch (mthca_mig_state
) {
369 case 0: return IB_MIG_ARMED
;
370 case 1: return IB_MIG_REARM
;
371 case 3: return IB_MIG_MIGRATED
;
376 static int to_ib_qp_access_flags(int mthca_flags
)
380 if (mthca_flags
& MTHCA_QP_BIT_RRE
)
381 ib_flags
|= IB_ACCESS_REMOTE_READ
;
382 if (mthca_flags
& MTHCA_QP_BIT_RWE
)
383 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
384 if (mthca_flags
& MTHCA_QP_BIT_RAE
)
385 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
390 static void to_ib_ah_attr(struct mthca_dev
*dev
, struct ib_ah_attr
*ib_ah_attr
,
391 struct mthca_qp_path
*path
)
393 memset(ib_ah_attr
, 0, sizeof *path
);
394 ib_ah_attr
->port_num
= (be32_to_cpu(path
->port_pkey
) >> 24) & 0x3;
395 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
396 ib_ah_attr
->sl
= be32_to_cpu(path
->sl_tclass_flowlabel
) >> 28;
397 ib_ah_attr
->src_path_bits
= path
->g_mylmc
& 0x7f;
398 ib_ah_attr
->static_rate
= path
->static_rate
& 0x7;
399 ib_ah_attr
->ah_flags
= (path
->g_mylmc
& (1 << 7)) ? IB_AH_GRH
: 0;
400 if (ib_ah_attr
->ah_flags
) {
401 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
& (dev
->limits
.gid_table_len
- 1);
402 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
403 ib_ah_attr
->grh
.traffic_class
=
404 (be32_to_cpu(path
->sl_tclass_flowlabel
) >> 20) & 0xff;
405 ib_ah_attr
->grh
.flow_label
=
406 be32_to_cpu(path
->sl_tclass_flowlabel
) & 0xfffff;
407 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
408 path
->rgid
, sizeof ib_ah_attr
->grh
.dgid
.raw
);
412 int mthca_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
413 struct ib_qp_init_attr
*qp_init_attr
)
415 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
416 struct mthca_qp
*qp
= to_mqp(ibqp
);
418 struct mthca_mailbox
*mailbox
;
419 struct mthca_qp_param
*qp_param
;
420 struct mthca_qp_context
*context
;
424 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
426 return PTR_ERR(mailbox
);
428 err
= mthca_QUERY_QP(dev
, qp
->qpn
, 0, mailbox
, &status
);
432 mthca_warn(dev
, "QUERY_QP returned status %02x\n", status
);
437 qp_param
= mailbox
->buf
;
438 context
= &qp_param
->context
;
439 mthca_state
= be32_to_cpu(context
->flags
) >> 28;
441 qp_attr
->qp_state
= to_ib_qp_state(mthca_state
);
442 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
443 qp_attr
->path_mtu
= context
->mtu_msgmax
>> 5;
444 qp_attr
->path_mig_state
=
445 to_ib_mig_state((be32_to_cpu(context
->flags
) >> 11) & 0x3);
446 qp_attr
->qkey
= be32_to_cpu(context
->qkey
);
447 qp_attr
->rq_psn
= be32_to_cpu(context
->rnr_nextrecvpsn
) & 0xffffff;
448 qp_attr
->sq_psn
= be32_to_cpu(context
->next_send_psn
) & 0xffffff;
449 qp_attr
->dest_qp_num
= be32_to_cpu(context
->remote_qpn
) & 0xffffff;
450 qp_attr
->qp_access_flags
=
451 to_ib_qp_access_flags(be32_to_cpu(context
->params2
));
452 qp_attr
->cap
.max_send_wr
= qp
->sq
.max
;
453 qp_attr
->cap
.max_recv_wr
= qp
->rq
.max
;
454 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
455 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
456 qp_attr
->cap
.max_inline_data
= qp
->max_inline_data
;
458 to_ib_ah_attr(dev
, &qp_attr
->ah_attr
, &context
->pri_path
);
459 to_ib_ah_attr(dev
, &qp_attr
->alt_ah_attr
, &context
->alt_path
);
461 qp_attr
->pkey_index
= be32_to_cpu(context
->pri_path
.port_pkey
) & 0x7f;
462 qp_attr
->alt_pkey_index
= be32_to_cpu(context
->alt_path
.port_pkey
) & 0x7f;
464 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
465 qp_attr
->sq_draining
= mthca_state
== MTHCA_QP_STATE_DRAINING
;
467 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
->params1
) >> 21) & 0x7);
469 qp_attr
->max_dest_rd_atomic
=
470 1 << ((be32_to_cpu(context
->params2
) >> 21) & 0x7);
471 qp_attr
->min_rnr_timer
=
472 (be32_to_cpu(context
->rnr_nextrecvpsn
) >> 24) & 0x1f;
473 qp_attr
->port_num
= qp_attr
->ah_attr
.port_num
;
474 qp_attr
->timeout
= context
->pri_path
.ackto
>> 3;
475 qp_attr
->retry_cnt
= (be32_to_cpu(context
->params1
) >> 16) & 0x7;
476 qp_attr
->rnr_retry
= context
->pri_path
.rnr_retry
>> 5;
477 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
478 qp_attr
->alt_timeout
= context
->alt_path
.ackto
>> 3;
479 qp_init_attr
->cap
= qp_attr
->cap
;
482 mthca_free_mailbox(dev
, mailbox
);
486 static void mthca_path_set(struct ib_ah_attr
*ah
, struct mthca_qp_path
*path
)
488 path
->g_mylmc
= ah
->src_path_bits
& 0x7f;
489 path
->rlid
= cpu_to_be16(ah
->dlid
);
490 path
->static_rate
= !!ah
->static_rate
;
492 if (ah
->ah_flags
& IB_AH_GRH
) {
493 path
->g_mylmc
|= 1 << 7;
494 path
->mgid_index
= ah
->grh
.sgid_index
;
495 path
->hop_limit
= ah
->grh
.hop_limit
;
496 path
->sl_tclass_flowlabel
=
497 cpu_to_be32((ah
->sl
<< 28) |
498 (ah
->grh
.traffic_class
<< 20) |
499 (ah
->grh
.flow_label
));
500 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
502 path
->sl_tclass_flowlabel
= cpu_to_be32(ah
->sl
<< 28);
505 int mthca_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
, int attr_mask
)
507 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
508 struct mthca_qp
*qp
= to_mqp(ibqp
);
509 enum ib_qp_state cur_state
, new_state
;
510 struct mthca_mailbox
*mailbox
;
511 struct mthca_qp_param
*qp_param
;
512 struct mthca_qp_context
*qp_context
;
517 if (attr_mask
& IB_QP_CUR_STATE
) {
518 cur_state
= attr
->cur_qp_state
;
520 spin_lock_irq(&qp
->sq
.lock
);
521 spin_lock(&qp
->rq
.lock
);
522 cur_state
= qp
->state
;
523 spin_unlock(&qp
->rq
.lock
);
524 spin_unlock_irq(&qp
->sq
.lock
);
527 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
529 if (!ib_modify_qp_is_ok(cur_state
, new_state
, ibqp
->qp_type
, attr_mask
)) {
530 mthca_dbg(dev
, "Bad QP transition (transport %d) "
531 "%d->%d with attr 0x%08x\n",
532 qp
->transport
, cur_state
, new_state
,
537 if ((attr_mask
& IB_QP_PKEY_INDEX
) &&
538 attr
->pkey_index
>= dev
->limits
.pkey_table_len
) {
539 mthca_dbg(dev
, "P_Key index (%u) too large. max is %d\n",
540 attr
->pkey_index
, dev
->limits
.pkey_table_len
-1);
544 if ((attr_mask
& IB_QP_PORT
) &&
545 (attr
->port_num
== 0 || attr
->port_num
> dev
->limits
.num_ports
)) {
546 mthca_dbg(dev
, "Port number (%u) is invalid\n", attr
->port_num
);
550 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
551 attr
->max_rd_atomic
> dev
->limits
.max_qp_init_rdma
) {
552 mthca_dbg(dev
, "Max rdma_atomic as initiator %u too large (max is %d)\n",
553 attr
->max_rd_atomic
, dev
->limits
.max_qp_init_rdma
);
557 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
558 attr
->max_dest_rd_atomic
> 1 << dev
->qp_table
.rdb_shift
) {
559 mthca_dbg(dev
, "Max rdma_atomic as responder %u too large (max %d)\n",
560 attr
->max_dest_rd_atomic
, 1 << dev
->qp_table
.rdb_shift
);
564 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
566 return PTR_ERR(mailbox
);
567 qp_param
= mailbox
->buf
;
568 qp_context
= &qp_param
->context
;
569 memset(qp_param
, 0, sizeof *qp_param
);
571 qp_context
->flags
= cpu_to_be32((to_mthca_state(new_state
) << 28) |
572 (to_mthca_st(qp
->transport
) << 16));
573 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_BIT_DE
);
574 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
575 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
577 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE
);
578 switch (attr
->path_mig_state
) {
579 case IB_MIG_MIGRATED
:
580 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
583 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_REARM
<< 11);
586 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_ARMED
<< 11);
591 /* leave tavor_sched_queue as 0 */
593 if (qp
->transport
== MLX
|| qp
->transport
== UD
)
594 qp_context
->mtu_msgmax
= (IB_MTU_2048
<< 5) | 11;
595 else if (attr_mask
& IB_QP_PATH_MTU
)
596 qp_context
->mtu_msgmax
= (attr
->path_mtu
<< 5) | 31;
598 if (mthca_is_memfree(dev
)) {
600 qp_context
->rq_size_stride
= long_log2(qp
->rq
.max
) << 3;
601 qp_context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
604 qp_context
->sq_size_stride
= long_log2(qp
->sq
.max
) << 3;
605 qp_context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
608 /* leave arbel_sched_queue as 0 */
610 if (qp
->ibqp
.uobject
)
611 qp_context
->usr_page
=
612 cpu_to_be32(to_mucontext(qp
->ibqp
.uobject
->context
)->uar
.index
);
614 qp_context
->usr_page
= cpu_to_be32(dev
->driver_uar
.index
);
615 qp_context
->local_qpn
= cpu_to_be32(qp
->qpn
);
616 if (attr_mask
& IB_QP_DEST_QPN
) {
617 qp_context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
620 if (qp
->transport
== MLX
)
621 qp_context
->pri_path
.port_pkey
|=
622 cpu_to_be32(to_msqp(qp
)->port
<< 24);
624 if (attr_mask
& IB_QP_PORT
) {
625 qp_context
->pri_path
.port_pkey
|=
626 cpu_to_be32(attr
->port_num
<< 24);
627 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM
);
631 if (attr_mask
& IB_QP_PKEY_INDEX
) {
632 qp_context
->pri_path
.port_pkey
|=
633 cpu_to_be32(attr
->pkey_index
);
634 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX
);
637 if (attr_mask
& IB_QP_RNR_RETRY
) {
638 qp_context
->alt_path
.rnr_retry
= qp_context
->pri_path
.rnr_retry
=
639 attr
->rnr_retry
<< 5;
640 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY
|
641 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
);
644 if (attr_mask
& IB_QP_AV
) {
645 mthca_path_set(&attr
->ah_attr
, &qp_context
->pri_path
);
646 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
);
649 if (attr_mask
& IB_QP_TIMEOUT
) {
650 qp_context
->pri_path
.ackto
= attr
->timeout
<< 3;
651 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT
);
654 if (attr_mask
& IB_QP_ALT_PATH
) {
655 if (attr
->alt_pkey_index
>= dev
->limits
.pkey_table_len
) {
656 mthca_dbg(dev
, "Alternate P_Key index (%u) too large. max is %d\n",
657 attr
->alt_pkey_index
, dev
->limits
.pkey_table_len
-1);
661 if (attr
->alt_port_num
== 0 || attr
->alt_port_num
> dev
->limits
.num_ports
) {
662 mthca_dbg(dev
, "Alternate port number (%u) is invalid\n",
667 mthca_path_set(&attr
->alt_ah_attr
, &qp_context
->alt_path
);
668 qp_context
->alt_path
.port_pkey
|= cpu_to_be32(attr
->alt_pkey_index
|
669 attr
->alt_port_num
<< 24);
670 qp_context
->alt_path
.ackto
= attr
->alt_timeout
<< 3;
671 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH
);
675 qp_context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pd_num
);
676 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
677 qp_context
->wqe_lkey
= cpu_to_be32(qp
->mr
.ibmr
.lkey
);
678 qp_context
->params1
= cpu_to_be32((MTHCA_ACK_REQ_FREQ
<< 28) |
679 (MTHCA_FLIGHT_LIMIT
<< 24) |
681 if (qp
->sq_policy
== IB_SIGNAL_ALL_WR
)
682 qp_context
->params1
|= cpu_to_be32(MTHCA_QP_BIT_SSC
);
683 if (attr_mask
& IB_QP_RETRY_CNT
) {
684 qp_context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
685 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT
);
688 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
689 if (attr
->max_rd_atomic
) {
690 qp_context
->params1
|=
691 cpu_to_be32(MTHCA_QP_BIT_SRE
|
693 qp_context
->params1
|=
694 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
696 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX
);
699 if (attr_mask
& IB_QP_SQ_PSN
)
700 qp_context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
701 qp_context
->cqn_snd
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->cqn
);
703 if (mthca_is_memfree(dev
)) {
704 qp_context
->snd_wqe_base_l
= cpu_to_be32(qp
->send_wqe_offset
);
705 qp_context
->snd_db_index
= cpu_to_be32(qp
->sq
.db_index
);
708 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
709 if (attr
->max_dest_rd_atomic
)
710 qp_context
->params2
|=
711 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
713 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX
);
716 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
)) {
717 qp_context
->params2
|= get_hw_access_flags(qp
, attr
, attr_mask
);
718 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
719 MTHCA_QP_OPTPAR_RRE
|
720 MTHCA_QP_OPTPAR_RAE
);
723 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RSC
);
726 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RIC
);
728 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
729 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
730 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT
);
732 if (attr_mask
& IB_QP_RQ_PSN
)
733 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
735 qp_context
->ra_buff_indx
=
736 cpu_to_be32(dev
->qp_table
.rdb_base
+
737 ((qp
->qpn
& (dev
->limits
.num_qps
- 1)) * MTHCA_RDB_ENTRY_SIZE
<<
738 dev
->qp_table
.rdb_shift
));
740 qp_context
->cqn_rcv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->cqn
);
742 if (mthca_is_memfree(dev
))
743 qp_context
->rcv_db_index
= cpu_to_be32(qp
->rq
.db_index
);
745 if (attr_mask
& IB_QP_QKEY
) {
746 qp_context
->qkey
= cpu_to_be32(attr
->qkey
);
747 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY
);
751 qp_context
->srqn
= cpu_to_be32(1 << 24 |
752 to_msrq(ibqp
->srq
)->srqn
);
754 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
755 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&&
756 attr
->en_sqd_async_notify
)
759 err
= mthca_MODIFY_QP(dev
, cur_state
, new_state
, qp
->qpn
, 0,
760 mailbox
, sqd_event
, &status
);
762 mthca_warn(dev
, "modify QP %d->%d returned status %02x.\n",
763 cur_state
, new_state
, status
);
768 qp
->state
= new_state
;
769 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
770 qp
->atomic_rd_en
= attr
->qp_access_flags
;
771 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
772 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
775 mthca_free_mailbox(dev
, mailbox
);
778 store_attrs(to_msqp(qp
), attr
, attr_mask
);
781 * If we moved QP0 to RTR, bring the IB link up; if we moved
782 * QP0 to RESET or ERROR, bring the link back down.
784 if (is_qp0(dev
, qp
)) {
785 if (cur_state
!= IB_QPS_RTR
&&
786 new_state
== IB_QPS_RTR
)
787 init_port(dev
, to_msqp(qp
)->port
);
789 if (cur_state
!= IB_QPS_RESET
&&
790 cur_state
!= IB_QPS_ERR
&&
791 (new_state
== IB_QPS_RESET
||
792 new_state
== IB_QPS_ERR
))
793 mthca_CLOSE_IB(dev
, to_msqp(qp
)->port
, &status
);
797 * If we moved a kernel QP to RESET, clean up all old CQ
798 * entries and reinitialize the QP.
800 if (!err
&& new_state
== IB_QPS_RESET
&& !qp
->ibqp
.uobject
) {
801 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
802 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
803 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
804 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
805 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
807 mthca_wq_init(&qp
->sq
);
808 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
810 mthca_wq_init(&qp
->rq
);
811 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
813 if (mthca_is_memfree(dev
)) {
822 static int mthca_max_data_size(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int desc_sz
)
825 * Calculate the maximum size of WQE s/g segments, excluding
826 * the next segment and other non-data segments.
828 int max_data_size
= desc_sz
- sizeof (struct mthca_next_seg
);
830 switch (qp
->transport
) {
832 max_data_size
-= 2 * sizeof (struct mthca_data_seg
);
836 if (mthca_is_memfree(dev
))
837 max_data_size
-= sizeof (struct mthca_arbel_ud_seg
);
839 max_data_size
-= sizeof (struct mthca_tavor_ud_seg
);
843 max_data_size
-= sizeof (struct mthca_raddr_seg
);
847 return max_data_size
;
850 static inline int mthca_max_inline_data(struct mthca_pd
*pd
, int max_data_size
)
852 /* We don't support inline data for kernel QPs (yet). */
853 return pd
->ibpd
.uobject
? max_data_size
- MTHCA_INLINE_HEADER_SIZE
: 0;
856 static void mthca_adjust_qp_caps(struct mthca_dev
*dev
,
860 int max_data_size
= mthca_max_data_size(dev
, qp
,
861 min(dev
->limits
.max_desc_sz
,
862 1 << qp
->sq
.wqe_shift
));
864 qp
->max_inline_data
= mthca_max_inline_data(pd
, max_data_size
);
866 qp
->sq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
867 max_data_size
/ sizeof (struct mthca_data_seg
));
868 qp
->rq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
869 (min(dev
->limits
.max_desc_sz
, 1 << qp
->rq
.wqe_shift
) -
870 sizeof (struct mthca_next_seg
)) /
871 sizeof (struct mthca_data_seg
));
875 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
876 * rq.max_gs and sq.max_gs must all be assigned.
877 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
878 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
881 static int mthca_alloc_wqe_buf(struct mthca_dev
*dev
,
888 size
= sizeof (struct mthca_next_seg
) +
889 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
);
891 if (size
> dev
->limits
.max_desc_sz
)
894 for (qp
->rq
.wqe_shift
= 6; 1 << qp
->rq
.wqe_shift
< size
;
898 size
= qp
->sq
.max_gs
* sizeof (struct mthca_data_seg
);
899 switch (qp
->transport
) {
901 size
+= 2 * sizeof (struct mthca_data_seg
);
905 size
+= mthca_is_memfree(dev
) ?
906 sizeof (struct mthca_arbel_ud_seg
) :
907 sizeof (struct mthca_tavor_ud_seg
);
911 size
+= sizeof (struct mthca_raddr_seg
);
915 size
+= sizeof (struct mthca_raddr_seg
);
917 * An atomic op will require an atomic segment, a
918 * remote address segment and one scatter entry.
920 size
= max_t(int, size
,
921 sizeof (struct mthca_atomic_seg
) +
922 sizeof (struct mthca_raddr_seg
) +
923 sizeof (struct mthca_data_seg
));
930 /* Make sure that we have enough space for a bind request */
931 size
= max_t(int, size
, sizeof (struct mthca_bind_seg
));
933 size
+= sizeof (struct mthca_next_seg
);
935 if (size
> dev
->limits
.max_desc_sz
)
938 for (qp
->sq
.wqe_shift
= 6; 1 << qp
->sq
.wqe_shift
< size
;
942 qp
->send_wqe_offset
= ALIGN(qp
->rq
.max
<< qp
->rq
.wqe_shift
,
943 1 << qp
->sq
.wqe_shift
);
946 * If this is a userspace QP, we don't actually have to
947 * allocate anything. All we need is to calculate the WQE
948 * sizes and the send_wqe_offset, so we're done now.
950 if (pd
->ibpd
.uobject
)
953 size
= PAGE_ALIGN(qp
->send_wqe_offset
+
954 (qp
->sq
.max
<< qp
->sq
.wqe_shift
));
956 qp
->wrid
= kmalloc((qp
->rq
.max
+ qp
->sq
.max
) * sizeof (u64
),
961 err
= mthca_buf_alloc(dev
, size
, MTHCA_MAX_DIRECT_QP_SIZE
,
962 &qp
->queue
, &qp
->is_direct
, pd
, 0, &qp
->mr
);
973 static void mthca_free_wqe_buf(struct mthca_dev
*dev
,
976 mthca_buf_free(dev
, PAGE_ALIGN(qp
->send_wqe_offset
+
977 (qp
->sq
.max
<< qp
->sq
.wqe_shift
)),
978 &qp
->queue
, qp
->is_direct
, &qp
->mr
);
982 static int mthca_map_memfree(struct mthca_dev
*dev
,
987 if (mthca_is_memfree(dev
)) {
988 ret
= mthca_table_get(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
992 ret
= mthca_table_get(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
996 ret
= mthca_table_get(dev
, dev
->qp_table
.rdb_table
,
997 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1006 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1009 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1014 static void mthca_unmap_memfree(struct mthca_dev
*dev
,
1015 struct mthca_qp
*qp
)
1017 mthca_table_put(dev
, dev
->qp_table
.rdb_table
,
1018 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1019 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1020 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1023 static int mthca_alloc_memfree(struct mthca_dev
*dev
,
1024 struct mthca_qp
*qp
)
1028 if (mthca_is_memfree(dev
)) {
1029 qp
->rq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_RQ
,
1030 qp
->qpn
, &qp
->rq
.db
);
1031 if (qp
->rq
.db_index
< 0)
1034 qp
->sq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_SQ
,
1035 qp
->qpn
, &qp
->sq
.db
);
1036 if (qp
->sq
.db_index
< 0)
1037 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1043 static void mthca_free_memfree(struct mthca_dev
*dev
,
1044 struct mthca_qp
*qp
)
1046 if (mthca_is_memfree(dev
)) {
1047 mthca_free_db(dev
, MTHCA_DB_TYPE_SQ
, qp
->sq
.db_index
);
1048 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1052 static int mthca_alloc_qp_common(struct mthca_dev
*dev
,
1053 struct mthca_pd
*pd
,
1054 struct mthca_cq
*send_cq
,
1055 struct mthca_cq
*recv_cq
,
1056 enum ib_sig_type send_policy
,
1057 struct mthca_qp
*qp
)
1062 atomic_set(&qp
->refcount
, 1);
1063 init_waitqueue_head(&qp
->wait
);
1064 qp
->state
= IB_QPS_RESET
;
1065 qp
->atomic_rd_en
= 0;
1067 qp
->sq_policy
= send_policy
;
1068 mthca_wq_init(&qp
->sq
);
1069 mthca_wq_init(&qp
->rq
);
1071 ret
= mthca_map_memfree(dev
, qp
);
1075 ret
= mthca_alloc_wqe_buf(dev
, pd
, qp
);
1077 mthca_unmap_memfree(dev
, qp
);
1081 mthca_adjust_qp_caps(dev
, pd
, qp
);
1084 * If this is a userspace QP, we're done now. The doorbells
1085 * will be allocated and buffers will be initialized in
1088 if (pd
->ibpd
.uobject
)
1091 ret
= mthca_alloc_memfree(dev
, qp
);
1093 mthca_free_wqe_buf(dev
, qp
);
1094 mthca_unmap_memfree(dev
, qp
);
1098 if (mthca_is_memfree(dev
)) {
1099 struct mthca_next_seg
*next
;
1100 struct mthca_data_seg
*scatter
;
1101 int size
= (sizeof (struct mthca_next_seg
) +
1102 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
)) / 16;
1104 for (i
= 0; i
< qp
->rq
.max
; ++i
) {
1105 next
= get_recv_wqe(qp
, i
);
1106 next
->nda_op
= cpu_to_be32(((i
+ 1) & (qp
->rq
.max
- 1)) <<
1108 next
->ee_nds
= cpu_to_be32(size
);
1110 for (scatter
= (void *) (next
+ 1);
1111 (void *) scatter
< (void *) next
+ (1 << qp
->rq
.wqe_shift
);
1113 scatter
->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
1116 for (i
= 0; i
< qp
->sq
.max
; ++i
) {
1117 next
= get_send_wqe(qp
, i
);
1118 next
->nda_op
= cpu_to_be32((((i
+ 1) & (qp
->sq
.max
- 1)) <<
1120 qp
->send_wqe_offset
);
1124 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
1125 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
1130 static int mthca_set_qp_size(struct mthca_dev
*dev
, struct ib_qp_cap
*cap
,
1131 struct mthca_pd
*pd
, struct mthca_qp
*qp
)
1133 int max_data_size
= mthca_max_data_size(dev
, qp
, dev
->limits
.max_desc_sz
);
1135 /* Sanity check QP size before proceeding */
1136 if (cap
->max_send_wr
> dev
->limits
.max_wqes
||
1137 cap
->max_recv_wr
> dev
->limits
.max_wqes
||
1138 cap
->max_send_sge
> dev
->limits
.max_sg
||
1139 cap
->max_recv_sge
> dev
->limits
.max_sg
||
1140 cap
->max_inline_data
> mthca_max_inline_data(pd
, max_data_size
))
1144 * For MLX transport we need 2 extra S/G entries:
1145 * one for the header and one for the checksum at the end
1147 if (qp
->transport
== MLX
&& cap
->max_recv_sge
+ 2 > dev
->limits
.max_sg
)
1150 if (mthca_is_memfree(dev
)) {
1151 qp
->rq
.max
= cap
->max_recv_wr
?
1152 roundup_pow_of_two(cap
->max_recv_wr
) : 0;
1153 qp
->sq
.max
= cap
->max_send_wr
?
1154 roundup_pow_of_two(cap
->max_send_wr
) : 0;
1156 qp
->rq
.max
= cap
->max_recv_wr
;
1157 qp
->sq
.max
= cap
->max_send_wr
;
1160 qp
->rq
.max_gs
= cap
->max_recv_sge
;
1161 qp
->sq
.max_gs
= max_t(int, cap
->max_send_sge
,
1162 ALIGN(cap
->max_inline_data
+ MTHCA_INLINE_HEADER_SIZE
,
1163 MTHCA_INLINE_CHUNK_SIZE
) /
1164 sizeof (struct mthca_data_seg
));
1169 int mthca_alloc_qp(struct mthca_dev
*dev
,
1170 struct mthca_pd
*pd
,
1171 struct mthca_cq
*send_cq
,
1172 struct mthca_cq
*recv_cq
,
1173 enum ib_qp_type type
,
1174 enum ib_sig_type send_policy
,
1175 struct ib_qp_cap
*cap
,
1176 struct mthca_qp
*qp
)
1180 err
= mthca_set_qp_size(dev
, cap
, pd
, qp
);
1185 case IB_QPT_RC
: qp
->transport
= RC
; break;
1186 case IB_QPT_UC
: qp
->transport
= UC
; break;
1187 case IB_QPT_UD
: qp
->transport
= UD
; break;
1188 default: return -EINVAL
;
1191 qp
->qpn
= mthca_alloc(&dev
->qp_table
.alloc
);
1195 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1198 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1202 spin_lock_irq(&dev
->qp_table
.lock
);
1203 mthca_array_set(&dev
->qp_table
.qp
,
1204 qp
->qpn
& (dev
->limits
.num_qps
- 1), qp
);
1205 spin_unlock_irq(&dev
->qp_table
.lock
);
1210 int mthca_alloc_sqp(struct mthca_dev
*dev
,
1211 struct mthca_pd
*pd
,
1212 struct mthca_cq
*send_cq
,
1213 struct mthca_cq
*recv_cq
,
1214 enum ib_sig_type send_policy
,
1215 struct ib_qp_cap
*cap
,
1218 struct mthca_sqp
*sqp
)
1220 u32 mqpn
= qpn
* 2 + dev
->qp_table
.sqp_start
+ port
- 1;
1223 err
= mthca_set_qp_size(dev
, cap
, pd
, &sqp
->qp
);
1227 sqp
->header_buf_size
= sqp
->qp
.sq
.max
* MTHCA_UD_HEADER_SIZE
;
1228 sqp
->header_buf
= dma_alloc_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1229 &sqp
->header_dma
, GFP_KERNEL
);
1230 if (!sqp
->header_buf
)
1233 spin_lock_irq(&dev
->qp_table
.lock
);
1234 if (mthca_array_get(&dev
->qp_table
.qp
, mqpn
))
1237 mthca_array_set(&dev
->qp_table
.qp
, mqpn
, sqp
);
1238 spin_unlock_irq(&dev
->qp_table
.lock
);
1245 sqp
->qp
.transport
= MLX
;
1247 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1248 send_policy
, &sqp
->qp
);
1252 atomic_inc(&pd
->sqp_count
);
1258 * Lock CQs here, so that CQ polling code can do QP lookup
1259 * without taking a lock.
1261 spin_lock_irq(&send_cq
->lock
);
1262 if (send_cq
!= recv_cq
)
1263 spin_lock(&recv_cq
->lock
);
1265 spin_lock(&dev
->qp_table
.lock
);
1266 mthca_array_clear(&dev
->qp_table
.qp
, mqpn
);
1267 spin_unlock(&dev
->qp_table
.lock
);
1269 if (send_cq
!= recv_cq
)
1270 spin_unlock(&recv_cq
->lock
);
1271 spin_unlock_irq(&send_cq
->lock
);
1274 dma_free_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1275 sqp
->header_buf
, sqp
->header_dma
);
1280 void mthca_free_qp(struct mthca_dev
*dev
,
1281 struct mthca_qp
*qp
)
1284 struct mthca_cq
*send_cq
;
1285 struct mthca_cq
*recv_cq
;
1287 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1288 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
1291 * Lock CQs here, so that CQ polling code can do QP lookup
1292 * without taking a lock.
1294 spin_lock_irq(&send_cq
->lock
);
1295 if (send_cq
!= recv_cq
)
1296 spin_lock(&recv_cq
->lock
);
1298 spin_lock(&dev
->qp_table
.lock
);
1299 mthca_array_clear(&dev
->qp_table
.qp
,
1300 qp
->qpn
& (dev
->limits
.num_qps
- 1));
1301 spin_unlock(&dev
->qp_table
.lock
);
1303 if (send_cq
!= recv_cq
)
1304 spin_unlock(&recv_cq
->lock
);
1305 spin_unlock_irq(&send_cq
->lock
);
1307 atomic_dec(&qp
->refcount
);
1308 wait_event(qp
->wait
, !atomic_read(&qp
->refcount
));
1310 if (qp
->state
!= IB_QPS_RESET
)
1311 mthca_MODIFY_QP(dev
, qp
->state
, IB_QPS_RESET
, qp
->qpn
, 0,
1315 * If this is a userspace QP, the buffers, MR, CQs and so on
1316 * will be cleaned up in userspace, so all we have to do is
1317 * unref the mem-free tables and free the QPN in our table.
1319 if (!qp
->ibqp
.uobject
) {
1320 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
1321 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1322 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
1323 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
1324 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1326 mthca_free_memfree(dev
, qp
);
1327 mthca_free_wqe_buf(dev
, qp
);
1330 mthca_unmap_memfree(dev
, qp
);
1332 if (is_sqp(dev
, qp
)) {
1333 atomic_dec(&(to_mpd(qp
->ibqp
.pd
)->sqp_count
));
1334 dma_free_coherent(&dev
->pdev
->dev
,
1335 to_msqp(qp
)->header_buf_size
,
1336 to_msqp(qp
)->header_buf
,
1337 to_msqp(qp
)->header_dma
);
1339 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1342 /* Create UD header for an MLX send and build a data segment for it */
1343 static int build_mlx_header(struct mthca_dev
*dev
, struct mthca_sqp
*sqp
,
1344 int ind
, struct ib_send_wr
*wr
,
1345 struct mthca_mlx_seg
*mlx
,
1346 struct mthca_data_seg
*data
)
1352 ib_ud_header_init(256, /* assume a MAD */
1353 mthca_ah_grh_present(to_mah(wr
->wr
.ud
.ah
)),
1356 err
= mthca_read_ah(dev
, to_mah(wr
->wr
.ud
.ah
), &sqp
->ud_header
);
1359 mlx
->flags
&= ~cpu_to_be32(MTHCA_NEXT_SOLICIT
| 1);
1360 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MTHCA_MLX_VL15
: 0) |
1361 (sqp
->ud_header
.lrh
.destination_lid
==
1362 IB_LID_PERMISSIVE
? MTHCA_MLX_SLR
: 0) |
1363 (sqp
->ud_header
.lrh
.service_level
<< 8));
1364 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1367 switch (wr
->opcode
) {
1369 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1370 sqp
->ud_header
.immediate_present
= 0;
1372 case IB_WR_SEND_WITH_IMM
:
1373 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1374 sqp
->ud_header
.immediate_present
= 1;
1375 sqp
->ud_header
.immediate_data
= wr
->imm_data
;
1381 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1382 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1383 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1384 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1385 if (!sqp
->qp
.ibqp
.qp_num
)
1386 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1387 sqp
->pkey_index
, &pkey
);
1389 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1390 wr
->wr
.ud
.pkey_index
, &pkey
);
1391 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1392 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1393 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1394 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1395 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1396 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1398 header_size
= ib_ud_header_pack(&sqp
->ud_header
,
1400 ind
* MTHCA_UD_HEADER_SIZE
);
1402 data
->byte_count
= cpu_to_be32(header_size
);
1403 data
->lkey
= cpu_to_be32(to_mpd(sqp
->qp
.ibqp
.pd
)->ntmr
.ibmr
.lkey
);
1404 data
->addr
= cpu_to_be64(sqp
->header_dma
+
1405 ind
* MTHCA_UD_HEADER_SIZE
);
1410 static inline int mthca_wq_overflow(struct mthca_wq
*wq
, int nreq
,
1411 struct ib_cq
*ib_cq
)
1414 struct mthca_cq
*cq
;
1416 cur
= wq
->head
- wq
->tail
;
1417 if (likely(cur
+ nreq
< wq
->max
))
1421 spin_lock(&cq
->lock
);
1422 cur
= wq
->head
- wq
->tail
;
1423 spin_unlock(&cq
->lock
);
1425 return cur
+ nreq
>= wq
->max
;
1428 int mthca_tavor_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1429 struct ib_send_wr
**bad_wr
)
1431 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1432 struct mthca_qp
*qp
= to_mqp(ibqp
);
1435 unsigned long flags
;
1445 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1447 /* XXX check that state is OK to post send */
1449 ind
= qp
->sq
.next_ind
;
1451 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1452 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1453 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1454 " %d max, %d nreq)\n", qp
->qpn
,
1455 qp
->sq
.head
, qp
->sq
.tail
,
1462 wqe
= get_send_wqe(qp
, ind
);
1463 prev_wqe
= qp
->sq
.last
;
1466 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1467 ((struct mthca_next_seg
*) wqe
)->ee_nds
= 0;
1468 ((struct mthca_next_seg
*) wqe
)->flags
=
1469 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1470 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1471 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1472 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1474 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1475 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1476 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1478 wqe
+= sizeof (struct mthca_next_seg
);
1479 size
= sizeof (struct mthca_next_seg
) / 16;
1481 switch (qp
->transport
) {
1483 switch (wr
->opcode
) {
1484 case IB_WR_ATOMIC_CMP_AND_SWP
:
1485 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1486 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1487 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1488 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1489 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1490 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1492 wqe
+= sizeof (struct mthca_raddr_seg
);
1494 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1495 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1496 cpu_to_be64(wr
->wr
.atomic
.swap
);
1497 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1498 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1500 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1501 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1502 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1505 wqe
+= sizeof (struct mthca_atomic_seg
);
1506 size
+= (sizeof (struct mthca_raddr_seg
) +
1507 sizeof (struct mthca_atomic_seg
)) / 16;
1510 case IB_WR_RDMA_WRITE
:
1511 case IB_WR_RDMA_WRITE_WITH_IMM
:
1512 case IB_WR_RDMA_READ
:
1513 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1514 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1515 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1516 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1517 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1518 wqe
+= sizeof (struct mthca_raddr_seg
);
1519 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1523 /* No extra segments required for sends */
1530 switch (wr
->opcode
) {
1531 case IB_WR_RDMA_WRITE
:
1532 case IB_WR_RDMA_WRITE_WITH_IMM
:
1533 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1534 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1535 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1536 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1537 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1538 wqe
+= sizeof (struct mthca_raddr_seg
);
1539 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1543 /* No extra segments required for sends */
1550 ((struct mthca_tavor_ud_seg
*) wqe
)->lkey
=
1551 cpu_to_be32(to_mah(wr
->wr
.ud
.ah
)->key
);
1552 ((struct mthca_tavor_ud_seg
*) wqe
)->av_addr
=
1553 cpu_to_be64(to_mah(wr
->wr
.ud
.ah
)->avdma
);
1554 ((struct mthca_tavor_ud_seg
*) wqe
)->dqpn
=
1555 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1556 ((struct mthca_tavor_ud_seg
*) wqe
)->qkey
=
1557 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1559 wqe
+= sizeof (struct mthca_tavor_ud_seg
);
1560 size
+= sizeof (struct mthca_tavor_ud_seg
) / 16;
1564 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1565 wqe
- sizeof (struct mthca_next_seg
),
1571 wqe
+= sizeof (struct mthca_data_seg
);
1572 size
+= sizeof (struct mthca_data_seg
) / 16;
1576 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1577 mthca_err(dev
, "too many gathers\n");
1583 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1584 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1585 cpu_to_be32(wr
->sg_list
[i
].length
);
1586 ((struct mthca_data_seg
*) wqe
)->lkey
=
1587 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1588 ((struct mthca_data_seg
*) wqe
)->addr
=
1589 cpu_to_be64(wr
->sg_list
[i
].addr
);
1590 wqe
+= sizeof (struct mthca_data_seg
);
1591 size
+= sizeof (struct mthca_data_seg
) / 16;
1594 /* Add one more inline data segment for ICRC */
1595 if (qp
->transport
== MLX
) {
1596 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1597 cpu_to_be32((1 << 31) | 4);
1598 ((u32
*) wqe
)[1] = 0;
1599 wqe
+= sizeof (struct mthca_data_seg
);
1600 size
+= sizeof (struct mthca_data_seg
) / 16;
1603 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1605 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1606 mthca_err(dev
, "opcode invalid\n");
1612 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1613 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1614 qp
->send_wqe_offset
) |
1615 mthca_opcode
[wr
->opcode
]);
1617 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1618 cpu_to_be32((size0
? 0 : MTHCA_NEXT_DBD
) | size
|
1619 ((wr
->send_flags
& IB_SEND_FENCE
) ?
1620 MTHCA_NEXT_FENCE
: 0));
1624 op0
= mthca_opcode
[wr
->opcode
];
1628 if (unlikely(ind
>= qp
->sq
.max
))
1636 doorbell
[0] = cpu_to_be32(((qp
->sq
.next_ind
<< qp
->sq
.wqe_shift
) +
1637 qp
->send_wqe_offset
) | f0
| op0
);
1638 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1642 mthca_write64(doorbell
,
1643 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1644 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1647 qp
->sq
.next_ind
= ind
;
1648 qp
->sq
.head
+= nreq
;
1650 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1654 int mthca_tavor_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1655 struct ib_recv_wr
**bad_wr
)
1657 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1658 struct mthca_qp
*qp
= to_mqp(ibqp
);
1660 unsigned long flags
;
1670 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1672 /* XXX check that state is OK to post receive */
1674 ind
= qp
->rq
.next_ind
;
1676 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1677 if (unlikely(nreq
== MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
)) {
1680 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1681 doorbell
[1] = cpu_to_be32(qp
->qpn
<< 8);
1685 mthca_write64(doorbell
,
1686 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1687 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1689 qp
->rq
.head
+= MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
;
1693 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1694 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
1695 " %d max, %d nreq)\n", qp
->qpn
,
1696 qp
->rq
.head
, qp
->rq
.tail
,
1703 wqe
= get_recv_wqe(qp
, ind
);
1704 prev_wqe
= qp
->rq
.last
;
1707 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1708 ((struct mthca_next_seg
*) wqe
)->ee_nds
=
1709 cpu_to_be32(MTHCA_NEXT_DBD
);
1710 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
1712 wqe
+= sizeof (struct mthca_next_seg
);
1713 size
= sizeof (struct mthca_next_seg
) / 16;
1715 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1721 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1722 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1723 cpu_to_be32(wr
->sg_list
[i
].length
);
1724 ((struct mthca_data_seg
*) wqe
)->lkey
=
1725 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1726 ((struct mthca_data_seg
*) wqe
)->addr
=
1727 cpu_to_be64(wr
->sg_list
[i
].addr
);
1728 wqe
+= sizeof (struct mthca_data_seg
);
1729 size
+= sizeof (struct mthca_data_seg
) / 16;
1732 qp
->wrid
[ind
] = wr
->wr_id
;
1734 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1735 cpu_to_be32((ind
<< qp
->rq
.wqe_shift
) | 1);
1737 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1738 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
1744 if (unlikely(ind
>= qp
->rq
.max
))
1750 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1751 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | nreq
);
1755 mthca_write64(doorbell
,
1756 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1757 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1760 qp
->rq
.next_ind
= ind
;
1761 qp
->rq
.head
+= nreq
;
1763 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1767 int mthca_arbel_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1768 struct ib_send_wr
**bad_wr
)
1770 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1771 struct mthca_qp
*qp
= to_mqp(ibqp
);
1775 unsigned long flags
;
1785 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1787 /* XXX check that state is OK to post send */
1789 ind
= qp
->sq
.head
& (qp
->sq
.max
- 1);
1791 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1792 if (unlikely(nreq
== MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
)) {
1795 doorbell
[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
<< 24) |
1796 ((qp
->sq
.head
& 0xffff) << 8) |
1798 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1800 qp
->sq
.head
+= MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
;
1804 * Make sure that descriptors are written before
1808 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
1811 * Make sure doorbell record is written before we
1812 * write MMIO send doorbell.
1815 mthca_write64(doorbell
,
1816 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1817 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1820 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1821 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1822 " %d max, %d nreq)\n", qp
->qpn
,
1823 qp
->sq
.head
, qp
->sq
.tail
,
1830 wqe
= get_send_wqe(qp
, ind
);
1831 prev_wqe
= qp
->sq
.last
;
1834 ((struct mthca_next_seg
*) wqe
)->flags
=
1835 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1836 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1837 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1838 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1840 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1841 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1842 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1844 wqe
+= sizeof (struct mthca_next_seg
);
1845 size
= sizeof (struct mthca_next_seg
) / 16;
1847 switch (qp
->transport
) {
1849 switch (wr
->opcode
) {
1850 case IB_WR_ATOMIC_CMP_AND_SWP
:
1851 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1852 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1853 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1854 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1855 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1856 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1858 wqe
+= sizeof (struct mthca_raddr_seg
);
1860 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1861 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1862 cpu_to_be64(wr
->wr
.atomic
.swap
);
1863 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1864 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1866 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1867 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1868 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1871 wqe
+= sizeof (struct mthca_atomic_seg
);
1872 size
+= (sizeof (struct mthca_raddr_seg
) +
1873 sizeof (struct mthca_atomic_seg
)) / 16;
1876 case IB_WR_RDMA_READ
:
1877 case IB_WR_RDMA_WRITE
:
1878 case IB_WR_RDMA_WRITE_WITH_IMM
:
1879 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1880 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1881 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1882 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1883 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1884 wqe
+= sizeof (struct mthca_raddr_seg
);
1885 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1889 /* No extra segments required for sends */
1896 switch (wr
->opcode
) {
1897 case IB_WR_RDMA_WRITE
:
1898 case IB_WR_RDMA_WRITE_WITH_IMM
:
1899 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1900 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1901 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1902 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1903 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1904 wqe
+= sizeof (struct mthca_raddr_seg
);
1905 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1909 /* No extra segments required for sends */
1916 memcpy(((struct mthca_arbel_ud_seg
*) wqe
)->av
,
1917 to_mah(wr
->wr
.ud
.ah
)->av
, MTHCA_AV_SIZE
);
1918 ((struct mthca_arbel_ud_seg
*) wqe
)->dqpn
=
1919 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1920 ((struct mthca_arbel_ud_seg
*) wqe
)->qkey
=
1921 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1923 wqe
+= sizeof (struct mthca_arbel_ud_seg
);
1924 size
+= sizeof (struct mthca_arbel_ud_seg
) / 16;
1928 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1929 wqe
- sizeof (struct mthca_next_seg
),
1935 wqe
+= sizeof (struct mthca_data_seg
);
1936 size
+= sizeof (struct mthca_data_seg
) / 16;
1940 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1941 mthca_err(dev
, "too many gathers\n");
1947 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1948 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1949 cpu_to_be32(wr
->sg_list
[i
].length
);
1950 ((struct mthca_data_seg
*) wqe
)->lkey
=
1951 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1952 ((struct mthca_data_seg
*) wqe
)->addr
=
1953 cpu_to_be64(wr
->sg_list
[i
].addr
);
1954 wqe
+= sizeof (struct mthca_data_seg
);
1955 size
+= sizeof (struct mthca_data_seg
) / 16;
1958 /* Add one more inline data segment for ICRC */
1959 if (qp
->transport
== MLX
) {
1960 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1961 cpu_to_be32((1 << 31) | 4);
1962 ((u32
*) wqe
)[1] = 0;
1963 wqe
+= sizeof (struct mthca_data_seg
);
1964 size
+= sizeof (struct mthca_data_seg
) / 16;
1967 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1969 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1970 mthca_err(dev
, "opcode invalid\n");
1976 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1977 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1978 qp
->send_wqe_offset
) |
1979 mthca_opcode
[wr
->opcode
]);
1981 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1982 cpu_to_be32(MTHCA_NEXT_DBD
| size
|
1983 ((wr
->send_flags
& IB_SEND_FENCE
) ?
1984 MTHCA_NEXT_FENCE
: 0));
1988 op0
= mthca_opcode
[wr
->opcode
];
1992 if (unlikely(ind
>= qp
->sq
.max
))
1998 doorbell
[0] = cpu_to_be32((nreq
<< 24) |
1999 ((qp
->sq
.head
& 0xffff) << 8) |
2001 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
2003 qp
->sq
.head
+= nreq
;
2006 * Make sure that descriptors are written before
2010 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
2013 * Make sure doorbell record is written before we
2014 * write MMIO send doorbell.
2017 mthca_write64(doorbell
,
2018 dev
->kar
+ MTHCA_SEND_DOORBELL
,
2019 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
2022 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
2026 int mthca_arbel_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
2027 struct ib_recv_wr
**bad_wr
)
2029 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
2030 struct mthca_qp
*qp
= to_mqp(ibqp
);
2031 unsigned long flags
;
2038 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
2040 /* XXX check that state is OK to post receive */
2042 ind
= qp
->rq
.head
& (qp
->rq
.max
- 1);
2044 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
2045 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
2046 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
2047 " %d max, %d nreq)\n", qp
->qpn
,
2048 qp
->rq
.head
, qp
->rq
.tail
,
2055 wqe
= get_recv_wqe(qp
, ind
);
2057 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
2059 wqe
+= sizeof (struct mthca_next_seg
);
2061 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
2067 for (i
= 0; i
< wr
->num_sge
; ++i
) {
2068 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2069 cpu_to_be32(wr
->sg_list
[i
].length
);
2070 ((struct mthca_data_seg
*) wqe
)->lkey
=
2071 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2072 ((struct mthca_data_seg
*) wqe
)->addr
=
2073 cpu_to_be64(wr
->sg_list
[i
].addr
);
2074 wqe
+= sizeof (struct mthca_data_seg
);
2077 if (i
< qp
->rq
.max_gs
) {
2078 ((struct mthca_data_seg
*) wqe
)->byte_count
= 0;
2079 ((struct mthca_data_seg
*) wqe
)->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
2080 ((struct mthca_data_seg
*) wqe
)->addr
= 0;
2083 qp
->wrid
[ind
] = wr
->wr_id
;
2086 if (unlikely(ind
>= qp
->rq
.max
))
2091 qp
->rq
.head
+= nreq
;
2094 * Make sure that descriptors are written before
2098 *qp
->rq
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
2101 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
2105 void mthca_free_err_wqe(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int is_send
,
2106 int index
, int *dbd
, __be32
*new_wqe
)
2108 struct mthca_next_seg
*next
;
2111 * For SRQs, all WQEs generate a CQE, so we're always at the
2112 * end of the doorbell chain.
2120 next
= get_send_wqe(qp
, index
);
2122 next
= get_recv_wqe(qp
, index
);
2124 *dbd
= !!(next
->ee_nds
& cpu_to_be32(MTHCA_NEXT_DBD
));
2125 if (next
->ee_nds
& cpu_to_be32(0x3f))
2126 *new_wqe
= (next
->nda_op
& cpu_to_be32(~0x3f)) |
2127 (next
->ee_nds
& cpu_to_be32(0x3f));
2132 int __devinit
mthca_init_qp_table(struct mthca_dev
*dev
)
2138 spin_lock_init(&dev
->qp_table
.lock
);
2141 * We reserve 2 extra QPs per port for the special QPs. The
2142 * special QP for port 1 has to be even, so round up.
2144 dev
->qp_table
.sqp_start
= (dev
->limits
.reserved_qps
+ 1) & ~1UL;
2145 err
= mthca_alloc_init(&dev
->qp_table
.alloc
,
2146 dev
->limits
.num_qps
,
2148 dev
->qp_table
.sqp_start
+
2149 MTHCA_MAX_PORTS
* 2);
2153 err
= mthca_array_init(&dev
->qp_table
.qp
,
2154 dev
->limits
.num_qps
);
2156 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2160 for (i
= 0; i
< 2; ++i
) {
2161 err
= mthca_CONF_SPECIAL_QP(dev
, i
? IB_QPT_GSI
: IB_QPT_SMI
,
2162 dev
->qp_table
.sqp_start
+ i
* 2,
2167 mthca_warn(dev
, "CONF_SPECIAL_QP returned "
2168 "status %02x, aborting.\n",
2177 for (i
= 0; i
< 2; ++i
)
2178 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2180 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2181 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2186 void __devexit
mthca_cleanup_qp_table(struct mthca_dev
*dev
)
2191 for (i
= 0; i
< 2; ++i
)
2192 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2194 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2195 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);