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RDMA/ocrdma: Update sli data structure for endianness
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_sli.h
1 /*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28 #ifndef __OCRDMA_SLI_H__
29 #define __OCRDMA_SLI_H__
30
31 #define Bit(_b) (1 << (_b))
32
33 enum {
34 OCRDMA_ASIC_GEN_SKH_R = 0x04,
35 OCRDMA_ASIC_GEN_LANCER = 0x0B
36 };
37
38 enum {
39 OCRDMA_ASIC_REV_A0 = 0x00,
40 OCRDMA_ASIC_REV_B0 = 0x10,
41 OCRDMA_ASIC_REV_C0 = 0x20
42 };
43
44 #define OCRDMA_SUBSYS_ROCE 10
45 enum {
46 OCRDMA_CMD_QUERY_CONFIG = 1,
47 OCRDMA_CMD_ALLOC_PD = 2,
48 OCRDMA_CMD_DEALLOC_PD = 3,
49
50 OCRDMA_CMD_CREATE_AH_TBL = 4,
51 OCRDMA_CMD_DELETE_AH_TBL = 5,
52
53 OCRDMA_CMD_CREATE_QP = 6,
54 OCRDMA_CMD_QUERY_QP = 7,
55 OCRDMA_CMD_MODIFY_QP = 8 ,
56 OCRDMA_CMD_DELETE_QP = 9,
57
58 OCRDMA_CMD_RSVD1 = 10,
59 OCRDMA_CMD_ALLOC_LKEY = 11,
60 OCRDMA_CMD_DEALLOC_LKEY = 12,
61 OCRDMA_CMD_REGISTER_NSMR = 13,
62 OCRDMA_CMD_REREGISTER_NSMR = 14,
63 OCRDMA_CMD_REGISTER_NSMR_CONT = 15,
64 OCRDMA_CMD_QUERY_NSMR = 16,
65 OCRDMA_CMD_ALLOC_MW = 17,
66 OCRDMA_CMD_QUERY_MW = 18,
67
68 OCRDMA_CMD_CREATE_SRQ = 19,
69 OCRDMA_CMD_QUERY_SRQ = 20,
70 OCRDMA_CMD_MODIFY_SRQ = 21,
71 OCRDMA_CMD_DELETE_SRQ = 22,
72
73 OCRDMA_CMD_ATTACH_MCAST = 23,
74 OCRDMA_CMD_DETACH_MCAST = 24,
75
76 OCRDMA_CMD_CREATE_RBQ = 25,
77 OCRDMA_CMD_DESTROY_RBQ = 26,
78
79 OCRDMA_CMD_GET_RDMA_STATS = 27,
80
81 OCRDMA_CMD_MAX
82 };
83
84 #define OCRDMA_SUBSYS_COMMON 1
85 enum {
86 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
87 OCRDMA_CMD_CREATE_CQ = 12,
88 OCRDMA_CMD_CREATE_EQ = 13,
89 OCRDMA_CMD_CREATE_MQ = 21,
90 OCRDMA_CMD_GET_CTRL_ATTRIBUTES = 32,
91 OCRDMA_CMD_GET_FW_VER = 35,
92 OCRDMA_CMD_DELETE_MQ = 53,
93 OCRDMA_CMD_DELETE_CQ = 54,
94 OCRDMA_CMD_DELETE_EQ = 55,
95 OCRDMA_CMD_GET_FW_CONFIG = 58,
96 OCRDMA_CMD_CREATE_MQ_EXT = 90,
97 OCRDMA_CMD_PHY_DETAILS = 102
98 };
99
100 enum {
101 QTYPE_EQ = 1,
102 QTYPE_CQ = 2,
103 QTYPE_MCCQ = 3
104 };
105
106 #define OCRDMA_MAX_SGID (8)
107
108 #define OCRDMA_MAX_QP 2048
109 #define OCRDMA_MAX_CQ 2048
110 #define OCRDMA_MAX_STAG 16384
111
112 enum {
113 OCRDMA_DB_RQ_OFFSET = 0xE0,
114 OCRDMA_DB_GEN2_RQ_OFFSET = 0x100,
115 OCRDMA_DB_SQ_OFFSET = 0x60,
116 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0,
117 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET,
118 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ_OFFSET,
119 OCRDMA_DB_CQ_OFFSET = 0x120,
120 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET,
121 OCRDMA_DB_MQ_OFFSET = 0x140,
122
123 OCRDMA_DB_SQ_SHIFT = 16,
124 OCRDMA_DB_RQ_SHIFT = 24
125 };
126
127 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
128 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
129 /* qid #2 msbits at 12-11 */
130 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1
131 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
132 /* Rearm bit */
133 #define OCRDMA_DB_CQ_REARM_SHIFT (29) /* bit 29 */
134 /* solicited bit */
135 #define OCRDMA_DB_CQ_SOLICIT_SHIFT (31) /* bit 31 */
136
137 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */
138 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */
139 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 at 11-15 */
140
141 /* Clear the interrupt for this eq */
142 #define OCRDMA_EQ_CLR_SHIFT (9) /* bit 9 */
143 /* Must be 1 */
144 #define OCRDMA_EQ_TYPE_SHIFT (10) /* bit 10 */
145 /* Number of event entries processed */
146 #define OCRDMA_NUM_EQE_SHIFT (16) /* bits 16 - 28 */
147 /* Rearm bit */
148 #define OCRDMA_REARM_SHIFT (29) /* bit 29 */
149
150 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */
151 /* Number of entries posted */
152 #define OCRDMA_MQ_NUM_MQE_SHIFT (16) /* bits 16 - 29 */
153
154 #define OCRDMA_MIN_HPAGE_SIZE (4096)
155
156 #define OCRDMA_MIN_Q_PAGE_SIZE (4096)
157 #define OCRDMA_MAX_Q_PAGES (8)
158
159 #define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C
160 #define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF
161 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00
162 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08
163 /*
164 # 0: 4K Bytes
165 # 1: 8K Bytes
166 # 2: 16K Bytes
167 # 3: 32K Bytes
168 # 4: 64K Bytes
169 # 5: 128K Bytes
170 # 6: 256K Bytes
171 # 7: 512K Bytes
172 */
173 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8)
174 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
175
176 #define MAX_OCRDMA_QP_PAGES (8)
177 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
178
179 #define OCRDMA_CREATE_CQ_MAX_PAGES (4)
180 #define OCRDMA_DPP_CQE_SIZE (4)
181
182 #define OCRDMA_GEN2_MAX_CQE 1024
183 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
184 #define OCRDMA_GEN2_WQE_SIZE 256
185 #define OCRDMA_MAX_CQE 4095
186 #define OCRDMA_CQ_PAGE_SIZE 16384
187 #define OCRDMA_WQE_SIZE 128
188 #define OCRDMA_WQE_STRIDE 8
189 #define OCRDMA_WQE_ALIGN_BYTES 16
190
191 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
192
193 enum {
194 OCRDMA_MCH_OPCODE_SHIFT = 0,
195 OCRDMA_MCH_OPCODE_MASK = 0xFF,
196 OCRDMA_MCH_SUBSYS_SHIFT = 8,
197 OCRDMA_MCH_SUBSYS_MASK = 0xFF00
198 };
199
200 /* mailbox cmd header */
201 struct ocrdma_mbx_hdr {
202 u32 subsys_op;
203 u32 timeout; /* in seconds */
204 u32 cmd_len;
205 u32 rsvd_version;
206 };
207
208 enum {
209 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0,
210 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF,
211 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8,
212 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
213
214 OCRDMA_MBX_RSP_STATUS_SHIFT = 0,
215 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF,
216 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8,
217 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
218 };
219
220 /* mailbox cmd response */
221 struct ocrdma_mbx_rsp {
222 u32 subsys_op;
223 u32 status;
224 u32 rsp_len;
225 u32 add_rsp_len;
226 };
227
228 enum {
229 OCRDMA_MQE_EMBEDDED = 1,
230 OCRDMA_MQE_NONEMBEDDED = 0
231 };
232
233 struct ocrdma_mqe_sge {
234 u32 pa_lo;
235 u32 pa_hi;
236 u32 len;
237 };
238
239 enum {
240 OCRDMA_MQE_HDR_EMB_SHIFT = 0,
241 OCRDMA_MQE_HDR_EMB_MASK = Bit(0),
242 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3,
243 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
244 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24,
245 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
246 };
247
248 struct ocrdma_mqe_hdr {
249 u32 spcl_sge_cnt_emb;
250 u32 pyld_len;
251 u32 tag_lo;
252 u32 tag_hi;
253 u32 rsvd3;
254 };
255
256 struct ocrdma_mqe_emb_cmd {
257 struct ocrdma_mbx_hdr mch;
258 u8 pyld[220];
259 };
260
261 struct ocrdma_mqe {
262 struct ocrdma_mqe_hdr hdr;
263 union {
264 struct ocrdma_mqe_emb_cmd emb_req;
265 struct {
266 struct ocrdma_mqe_sge sge[19];
267 } nonemb_req;
268 u8 cmd[236];
269 struct ocrdma_mbx_rsp rsp;
270 } u;
271 };
272
273 #define OCRDMA_EQ_LEN 4096
274 #define OCRDMA_MQ_CQ_LEN 256
275 #define OCRDMA_MQ_LEN 128
276
277 #define PAGE_SHIFT_4K 12
278 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
279
280 /* Returns number of pages spanned by the data starting at the given addr */
281 #define PAGES_4K_SPANNED(_address, size) \
282 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
283 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
284
285 struct ocrdma_delete_q_req {
286 struct ocrdma_mbx_hdr req;
287 u32 id;
288 };
289
290 struct ocrdma_pa {
291 u32 lo;
292 u32 hi;
293 };
294
295 #define MAX_OCRDMA_EQ_PAGES (8)
296 struct ocrdma_create_eq_req {
297 struct ocrdma_mbx_hdr req;
298 u32 num_pages;
299 u32 valid;
300 u32 cnt;
301 u32 delay;
302 u32 rsvd;
303 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
304 };
305
306 enum {
307 OCRDMA_CREATE_EQ_VALID = Bit(29),
308 OCRDMA_CREATE_EQ_CNT_SHIFT = 26,
309 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13,
310 };
311
312 struct ocrdma_create_eq_rsp {
313 struct ocrdma_mbx_rsp rsp;
314 u32 vector_eqid;
315 };
316
317 #define OCRDMA_EQ_MINOR_OTHER (0x1)
318
319 enum {
320 OCRDMA_MCQE_STATUS_SHIFT = 0,
321 OCRDMA_MCQE_STATUS_MASK = 0xFFFF,
322 OCRDMA_MCQE_ESTATUS_SHIFT = 16,
323 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
324 OCRDMA_MCQE_CONS_SHIFT = 27,
325 OCRDMA_MCQE_CONS_MASK = Bit(27),
326 OCRDMA_MCQE_CMPL_SHIFT = 28,
327 OCRDMA_MCQE_CMPL_MASK = Bit(28),
328 OCRDMA_MCQE_AE_SHIFT = 30,
329 OCRDMA_MCQE_AE_MASK = Bit(30),
330 OCRDMA_MCQE_VALID_SHIFT = 31,
331 OCRDMA_MCQE_VALID_MASK = Bit(31)
332 };
333
334 struct ocrdma_mcqe {
335 u32 status;
336 u32 tag_lo;
337 u32 tag_hi;
338 u32 valid_ae_cmpl_cons;
339 };
340
341 enum {
342 OCRDMA_AE_MCQE_QPVALID = Bit(31),
343 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF,
344
345 OCRDMA_AE_MCQE_CQVALID = Bit(31),
346 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF,
347 OCRDMA_AE_MCQE_VALID = Bit(31),
348 OCRDMA_AE_MCQE_AE = Bit(30),
349 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
350 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =
351 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
352 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
353 OCRDMA_AE_MCQE_EVENT_CODE_MASK =
354 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
355 };
356 struct ocrdma_ae_mcqe {
357 u32 qpvalid_qpid;
358 u32 cqvalid_cqid;
359 u32 evt_tag;
360 u32 valid_ae_event;
361 };
362
363 enum {
364 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
365 OCRDMA_AE_PVID_MCQE_ENABLED_MASK = 0xFF,
366 OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
367 OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
368 };
369
370 struct ocrdma_ae_pvid_mcqe {
371 u32 tag_enabled;
372 u32 event_tag;
373 u32 rsvd1;
374 u32 rsvd2;
375 };
376
377 enum {
378 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16,
379 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF <<
380 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
381
382 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8,
383 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF <<
384 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
385 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16,
386 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF <<
387 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
388 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30,
389 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30),
390 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31,
391 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31)
392 };
393
394 struct ocrdma_ae_mpa_mcqe {
395 u32 req_id;
396 u32 w1;
397 u32 w2;
398 u32 valid_ae_event;
399 };
400
401 enum {
402 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0,
403 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF,
404 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16,
405 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF <<
406 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
407
408 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8,
409 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF <<
410 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
411 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16,
412 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF <<
413 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
414 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30,
415 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30),
416 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31,
417 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31)
418 };
419
420 struct ocrdma_ae_qp_mcqe {
421 u32 qp_id_state;
422 u32 w1;
423 u32 w2;
424 u32 valid_ae_event;
425 };
426
427 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
428 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
429
430 enum ocrdma_async_grp5_events {
431 OCRDMA_ASYNC_EVENT_QOS_VALUE = 0x01,
432 OCRDMA_ASYNC_EVENT_COS_VALUE = 0x02,
433 OCRDMA_ASYNC_EVENT_PVID_STATE = 0x03
434 };
435
436 enum OCRDMA_ASYNC_EVENT_TYPE {
437 OCRDMA_CQ_ERROR = 0x00,
438 OCRDMA_CQ_OVERRUN_ERROR = 0x01,
439 OCRDMA_CQ_QPCAT_ERROR = 0x02,
440 OCRDMA_QP_ACCESS_ERROR = 0x03,
441 OCRDMA_QP_COMM_EST_EVENT = 0x04,
442 OCRDMA_SQ_DRAINED_EVENT = 0x05,
443 OCRDMA_DEVICE_FATAL_EVENT = 0x08,
444 OCRDMA_SRQCAT_ERROR = 0x0E,
445 OCRDMA_SRQ_LIMIT_EVENT = 0x0F,
446 OCRDMA_QP_LAST_WQE_EVENT = 0x10
447 };
448
449 /* mailbox command request and responses */
450 enum {
451 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2,
452 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2),
453 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3,
454 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3),
455 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8,
456 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF <<
457 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
458
459 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16,
460 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF <<
461 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
462 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8,
463 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF <<
464 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
465
466 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0,
467 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF,
468 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16,
469 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF <<
470 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
471
472 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0,
473 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF,
474 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16,
475 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF <<
476 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
477
478 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24,
479 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF <<
480 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
481 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16,
482 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF <<
483 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
484 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0,
485 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF <<
486 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
487
488 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16,
489 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF <<
490 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
491 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0,
492 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF <<
493 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
494
495 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16,
496 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF <<
497 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
498 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0,
499 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF <<
500 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
501
502 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0,
503 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF <<
504 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
505
506 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16,
507 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF <<
508 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
509 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0,
510 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF <<
511 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
512
513 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16,
514 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF <<
515 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
516 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0,
517 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF <<
518 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
519
520 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16,
521 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF <<
522 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
523 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0,
524 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF <<
525 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
526 };
527
528 struct ocrdma_mbx_query_config {
529 struct ocrdma_mqe_hdr hdr;
530 struct ocrdma_mbx_rsp rsp;
531 u32 qp_srq_cq_ird_ord;
532 u32 max_pd_ca_ack_delay;
533 u32 max_write_send_sge;
534 u32 max_ird_ord_per_qp;
535 u32 max_shared_ird_ord;
536 u32 max_mr;
537 u32 max_mr_size_hi;
538 u32 max_mr_size_lo;
539 u32 max_num_mr_pbl;
540 u32 max_mw;
541 u32 max_fmr;
542 u32 max_pages_per_frmr;
543 u32 max_mcast_group;
544 u32 max_mcast_qp_attach;
545 u32 max_total_mcast_qp_attach;
546 u32 wqe_rqe_stride_max_dpp_cqs;
547 u32 max_srq_rpir_qps;
548 u32 max_dpp_pds_credits;
549 u32 max_dpp_credits_pds_per_pd;
550 u32 max_wqes_rqes_per_q;
551 u32 max_cq_cqes_per_cq;
552 u32 max_srq_rqe_sge;
553 };
554
555 struct ocrdma_fw_ver_rsp {
556 struct ocrdma_mqe_hdr hdr;
557 struct ocrdma_mbx_rsp rsp;
558
559 u8 running_ver[32];
560 };
561
562 struct ocrdma_fw_conf_rsp {
563 struct ocrdma_mqe_hdr hdr;
564 struct ocrdma_mbx_rsp rsp;
565
566 u32 config_num;
567 u32 asic_revision;
568 u32 phy_port;
569 u32 fn_mode;
570 struct {
571 u32 mode;
572 u32 nic_wqid_base;
573 u32 nic_wq_tot;
574 u32 prot_wqid_base;
575 u32 prot_wq_tot;
576 u32 prot_rqid_base;
577 u32 prot_rqid_tot;
578 u32 rsvd[6];
579 } ulp[2];
580 u32 fn_capabilities;
581 u32 rsvd1;
582 u32 rsvd2;
583 u32 base_eqid;
584 u32 max_eq;
585
586 };
587
588 enum {
589 OCRDMA_FN_MODE_RDMA = 0x4
590 };
591
592 enum {
593 OCRDMA_IF_TYPE_MASK = 0xFFFF0000,
594 OCRDMA_IF_TYPE_SHIFT = 0x10,
595 OCRDMA_PHY_TYPE_MASK = 0x0000FFFF,
596 OCRDMA_FUTURE_DETAILS_MASK = 0xFFFF0000,
597 OCRDMA_FUTURE_DETAILS_SHIFT = 0x10,
598 OCRDMA_EX_PHY_DETAILS_MASK = 0x0000FFFF,
599 OCRDMA_FSPEED_SUPP_MASK = 0xFFFF0000,
600 OCRDMA_FSPEED_SUPP_SHIFT = 0x10,
601 OCRDMA_ASPEED_SUPP_MASK = 0x0000FFFF
602 };
603
604 struct ocrdma_get_phy_info_rsp {
605 struct ocrdma_mqe_hdr hdr;
606 struct ocrdma_mbx_rsp rsp;
607
608 u32 ityp_ptyp;
609 u32 misc_params;
610 u32 ftrdtl_exphydtl;
611 u32 fspeed_aspeed;
612 u32 future_use[2];
613 };
614
615 enum {
616 OCRDMA_PHY_SPEED_ZERO = 0x0,
617 OCRDMA_PHY_SPEED_10MBPS = 0x1,
618 OCRDMA_PHY_SPEED_100MBPS = 0x2,
619 OCRDMA_PHY_SPEED_1GBPS = 0x4,
620 OCRDMA_PHY_SPEED_10GBPS = 0x8,
621 OCRDMA_PHY_SPEED_40GBPS = 0x20
622 };
623
624 enum {
625 OCRDMA_PORT_NUM_MASK = 0x3F,
626 OCRDMA_PT_MASK = 0xC0,
627 OCRDMA_PT_SHIFT = 0x6,
628 OCRDMA_LINK_DUP_MASK = 0x0000FF00,
629 OCRDMA_LINK_DUP_SHIFT = 0x8,
630 OCRDMA_PHY_PS_MASK = 0x00FF0000,
631 OCRDMA_PHY_PS_SHIFT = 0x10,
632 OCRDMA_PHY_PFLT_MASK = 0xFF000000,
633 OCRDMA_PHY_PFLT_SHIFT = 0x18,
634 OCRDMA_QOS_LNKSP_MASK = 0xFFFF0000,
635 OCRDMA_QOS_LNKSP_SHIFT = 0x10,
636 OCRDMA_LLST_MASK = 0xFF,
637 OCRDMA_PLFC_MASK = 0x00000400,
638 OCRDMA_PLFC_SHIFT = 0x8,
639 OCRDMA_PLRFC_MASK = 0x00000200,
640 OCRDMA_PLRFC_SHIFT = 0x8,
641 OCRDMA_PLTFC_MASK = 0x00000100,
642 OCRDMA_PLTFC_SHIFT = 0x8
643 };
644
645 struct ocrdma_get_link_speed_rsp {
646 struct ocrdma_mqe_hdr hdr;
647 struct ocrdma_mbx_rsp rsp;
648
649 u32 pflt_pps_ld_pnum;
650 u32 qos_lsp;
651 u32 res_lls;
652 };
653
654 enum {
655 OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
656 OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
657 OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
658 OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
659 OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
660 OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
661 OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
662 OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
663 OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
664 };
665
666 enum {
667 OCRDMA_CREATE_CQ_VER2 = 2,
668 OCRDMA_CREATE_CQ_VER3 = 3,
669
670 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF,
671 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16,
672 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF,
673
674 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12,
675 OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12),
676 OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14),
677 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15),
678
679 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF,
680 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF
681 };
682
683 enum {
684 OCRDMA_CREATE_CQ_VER0 = 0,
685 OCRDMA_CREATE_CQ_DPP = 1,
686 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24,
687 OCRDMA_CREATE_CQ_EQID_SHIFT = 22,
688
689 OCRDMA_CREATE_CQ_CNT_SHIFT = 27,
690 OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29),
691 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31),
692 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID |
693 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
694 OCRDMA_CREATE_CQ_FLAGS_NODELAY
695 };
696
697 struct ocrdma_create_cq_cmd {
698 struct ocrdma_mbx_hdr req;
699 u32 pgsz_pgcnt;
700 u32 ev_cnt_flags;
701 u32 eqn;
702 u32 pdid_cqecnt;
703 u32 rsvd6;
704 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
705 };
706
707 struct ocrdma_create_cq {
708 struct ocrdma_mqe_hdr hdr;
709 struct ocrdma_create_cq_cmd cmd;
710 };
711
712 enum {
713 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT = 0x10
714 };
715
716 enum {
717 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
718 };
719
720 struct ocrdma_create_cq_cmd_rsp {
721 struct ocrdma_mbx_rsp rsp;
722 u32 cq_id;
723 };
724
725 struct ocrdma_create_cq_rsp {
726 struct ocrdma_mqe_hdr hdr;
727 struct ocrdma_create_cq_cmd_rsp rsp;
728 };
729
730 enum {
731 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22,
732 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,
733 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,
734 OCRDMA_CREATE_MQ_VALID = Bit(31),
735 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0)
736 };
737
738 struct ocrdma_create_mq_req {
739 struct ocrdma_mbx_hdr req;
740 u32 cqid_pages;
741 u32 async_event_bitmap;
742 u32 async_cqid_ringsize;
743 u32 valid;
744 u32 async_cqid_valid;
745 u32 rsvd;
746 struct ocrdma_pa pa[8];
747 };
748
749 struct ocrdma_create_mq_rsp {
750 struct ocrdma_mbx_rsp rsp;
751 u32 id;
752 };
753
754 enum {
755 OCRDMA_DESTROY_CQ_QID_SHIFT = 0,
756 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF,
757 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16,
758 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF <<
759 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
760 };
761
762 struct ocrdma_destroy_cq {
763 struct ocrdma_mqe_hdr hdr;
764 struct ocrdma_mbx_hdr req;
765
766 u32 bypass_flush_qid;
767 };
768
769 struct ocrdma_destroy_cq_rsp {
770 struct ocrdma_mqe_hdr hdr;
771 struct ocrdma_mbx_rsp rsp;
772 };
773
774 enum {
775 OCRDMA_QPT_GSI = 1,
776 OCRDMA_QPT_RC = 2,
777 OCRDMA_QPT_UD = 4,
778 };
779
780 enum {
781 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0,
782 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF,
783 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
784 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
785 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29,
786 OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29),
787
788 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0,
789 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF,
790 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16,
791 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF <<
792 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
793
794 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0,
795 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF,
796 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16,
797 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF <<
798 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
799
800 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0,
801 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0),
802 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1,
803 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1),
804 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2,
805 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2),
806 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3,
807 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3),
808 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4,
809 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4),
810 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5,
811 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5),
812 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6,
813 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6),
814 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7,
815 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7),
816 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8,
817 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8),
818 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,
819 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF <<
820 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
821
822 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0,
823 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF,
824 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16,
825 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF <<
826 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
827
828 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0,
829 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF,
830 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16,
831 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF <<
832 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
833
834 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0,
835 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF,
836 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16,
837 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF <<
838 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
839
840 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0,
841 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF,
842 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16,
843 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF <<
844 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
845
846 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0,
847 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF,
848 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16,
849 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF <<
850 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
851 };
852
853 enum {
854 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16,
855 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1
856 };
857
858 #define MAX_OCRDMA_IRD_PAGES 4
859
860 enum ocrdma_qp_flags {
861 OCRDMA_QP_MW_BIND = 1,
862 OCRDMA_QP_LKEY0 = (1 << 1),
863 OCRDMA_QP_FAST_REG = (1 << 2),
864 OCRDMA_QP_INB_RD = (1 << 6),
865 OCRDMA_QP_INB_WR = (1 << 7),
866 };
867
868 enum ocrdma_qp_state {
869 OCRDMA_QPS_RST = 0,
870 OCRDMA_QPS_INIT = 1,
871 OCRDMA_QPS_RTR = 2,
872 OCRDMA_QPS_RTS = 3,
873 OCRDMA_QPS_SQE = 4,
874 OCRDMA_QPS_SQ_DRAINING = 5,
875 OCRDMA_QPS_ERR = 6,
876 OCRDMA_QPS_SQD = 7
877 };
878
879 struct ocrdma_create_qp_req {
880 struct ocrdma_mqe_hdr hdr;
881 struct ocrdma_mbx_hdr req;
882
883 u32 type_pgsz_pdn;
884 u32 max_wqe_rqe;
885 u32 max_sge_send_write;
886 u32 max_sge_recv_flags;
887 u32 max_ord_ird;
888 u32 num_wq_rq_pages;
889 u32 wqe_rqe_size;
890 u32 wq_rq_cqid;
891 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
892 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
893 u32 dpp_credits_cqid;
894 u32 rpir_lkey;
895 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
896 };
897
898 enum {
899 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0,
900 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF,
901
902 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0,
903 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF,
904 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16,
905 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
906 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
907
908 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0,
909 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF,
910 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16,
911 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF <<
912 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
913
914 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16,
915 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF <<
916 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
917
918 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0,
919 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF,
920 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16,
921 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
922 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
923
924 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0,
925 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF,
926 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16,
927 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF <<
928 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
929
930 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0),
931 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1,
932 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF <<
933 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
934 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16,
935 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF <<
936 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
937 };
938
939 struct ocrdma_create_qp_rsp {
940 struct ocrdma_mqe_hdr hdr;
941 struct ocrdma_mbx_rsp rsp;
942
943 u32 qp_id;
944 u32 max_wqe_rqe;
945 u32 max_sge_send_write;
946 u32 max_sge_recv;
947 u32 max_ord_ird;
948 u32 sq_rq_id;
949 u32 dpp_response;
950 };
951
952 struct ocrdma_destroy_qp {
953 struct ocrdma_mqe_hdr hdr;
954 struct ocrdma_mbx_hdr req;
955 u32 qp_id;
956 };
957
958 struct ocrdma_destroy_qp_rsp {
959 struct ocrdma_mqe_hdr hdr;
960 struct ocrdma_mbx_rsp rsp;
961 };
962
963 enum {
964 OCRDMA_MODIFY_QP_ID_SHIFT = 0,
965 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF,
966
967 OCRDMA_QP_PARA_QPS_VALID = Bit(0),
968 OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1),
969 OCRDMA_QP_PARA_PKEY_VALID = Bit(2),
970 OCRDMA_QP_PARA_QKEY_VALID = Bit(3),
971 OCRDMA_QP_PARA_PMTU_VALID = Bit(4),
972 OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5),
973 OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6),
974 OCRDMA_QP_PARA_RRC_VALID = Bit(7),
975 OCRDMA_QP_PARA_RQPSN_VALID = Bit(8),
976 OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9),
977 OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10),
978 OCRDMA_QP_PARA_RNT_VALID = Bit(11),
979 OCRDMA_QP_PARA_SQPSN_VALID = Bit(12),
980 OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13),
981 OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14),
982 OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15),
983 OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16),
984 OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17),
985 OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18),
986 OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19),
987 OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20),
988 OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21),
989 OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22),
990 OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23),
991 OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24),
992 OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25),
993 OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26),
994
995 OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0),
996 OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1),
997 OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2),
998 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3)
999 };
1000
1001 enum {
1002 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0,
1003 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF,
1004
1005 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0,
1006 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF,
1007 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16,
1008 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF <<
1009 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
1010
1011 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0,
1012 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF,
1013 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16,
1014 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF <<
1015 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
1016
1017 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0),
1018 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1),
1019 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2),
1020 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3),
1021 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4),
1022 OCRDMA_QP_PARAMS_STATE_SHIFT = 5,
1023 OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7),
1024 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8),
1025 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9),
1026 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,
1027 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF <<
1028 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
1029
1030 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0,
1031 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF,
1032 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16,
1033 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF <<
1034 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1035
1036 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0,
1037 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF,
1038 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16,
1039 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF <<
1040 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1041
1042 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0,
1043 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF,
1044 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24,
1045 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF <<
1046 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1047
1048 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0,
1049 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF,
1050 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24,
1051 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF <<
1052 OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1053
1054 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0,
1055 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF,
1056 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24,
1057 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 <<
1058 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1059 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27,
1060 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F <<
1061 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1062
1063 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0,
1064 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF,
1065 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18,
1066 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF <<
1067 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1068
1069 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0,
1070 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF,
1071 OCRDMA_QP_PARAMS_SL_SHIFT = 20,
1072 OCRDMA_QP_PARAMS_SL_MASK = 0xF <<
1073 OCRDMA_QP_PARAMS_SL_SHIFT,
1074 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24,
1075 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 <<
1076 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1077 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27,
1078 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F <<
1079 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1080
1081 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0,
1082 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF,
1083 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16,
1084 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF <<
1085 OCRDMA_QP_PARAMS_VLAN_SHIFT
1086 };
1087
1088 struct ocrdma_qp_params {
1089 u32 id;
1090 u32 max_wqe_rqe;
1091 u32 max_sge_send_write;
1092 u32 max_sge_recv_flags;
1093 u32 max_ord_ird;
1094 u32 wq_rq_cqid;
1095 u32 hop_lmt_rq_psn;
1096 u32 tclass_sq_psn;
1097 u32 ack_to_rnr_rtc_dest_qpn;
1098 u32 path_mtu_pkey_indx;
1099 u32 rnt_rc_sl_fl;
1100 u8 sgid[16];
1101 u8 dgid[16];
1102 u32 dmac_b0_to_b3;
1103 u32 vlan_dmac_b4_to_b5;
1104 u32 qkey;
1105 };
1106
1107
1108 struct ocrdma_modify_qp {
1109 struct ocrdma_mqe_hdr hdr;
1110 struct ocrdma_mbx_hdr req;
1111
1112 struct ocrdma_qp_params params;
1113 u32 flags;
1114 u32 rdma_flags;
1115 u32 num_outstanding_atomic_rd;
1116 };
1117
1118 enum {
1119 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0,
1120 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF,
1121 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16,
1122 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
1123 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1124
1125 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0,
1126 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF,
1127 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16,
1128 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
1129 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1130 };
1131
1132 struct ocrdma_modify_qp_rsp {
1133 struct ocrdma_mqe_hdr hdr;
1134 struct ocrdma_mbx_rsp rsp;
1135
1136 u32 max_wqe_rqe;
1137 u32 max_ord_ird;
1138 };
1139
1140 struct ocrdma_query_qp {
1141 struct ocrdma_mqe_hdr hdr;
1142 struct ocrdma_mbx_hdr req;
1143
1144 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1145 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF
1146 u32 qp_id;
1147 };
1148
1149 struct ocrdma_query_qp_rsp {
1150 struct ocrdma_mqe_hdr hdr;
1151 struct ocrdma_mbx_rsp rsp;
1152 struct ocrdma_qp_params params;
1153 };
1154
1155 enum {
1156 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0,
1157 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF,
1158 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16,
1159 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 <<
1160 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1161
1162 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0,
1163 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16,
1164 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF <<
1165 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1166
1167 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0,
1168 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF,
1169 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16,
1170 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF <<
1171 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1172 };
1173
1174 struct ocrdma_create_srq {
1175 struct ocrdma_mqe_hdr hdr;
1176 struct ocrdma_mbx_hdr req;
1177
1178 u32 pgsz_pdid;
1179 u32 max_sge_rqe;
1180 u32 pages_rqe_sz;
1181 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1182 };
1183
1184 enum {
1185 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0,
1186 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF,
1187
1188 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0,
1189 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF,
1190 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16,
1191 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF <<
1192 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1193 };
1194
1195 struct ocrdma_create_srq_rsp {
1196 struct ocrdma_mqe_hdr hdr;
1197 struct ocrdma_mbx_rsp rsp;
1198
1199 u32 id;
1200 u32 max_sge_rqe_allocated;
1201 };
1202
1203 enum {
1204 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0,
1205 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF,
1206
1207 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1208 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF,
1209 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16,
1210 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF <<
1211 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1212 };
1213
1214 struct ocrdma_modify_srq {
1215 struct ocrdma_mqe_hdr hdr;
1216 struct ocrdma_mbx_rsp rep;
1217
1218 u32 id;
1219 u32 limit_max_rqe;
1220 };
1221
1222 enum {
1223 OCRDMA_QUERY_SRQ_ID_SHIFT = 0,
1224 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF
1225 };
1226
1227 struct ocrdma_query_srq {
1228 struct ocrdma_mqe_hdr hdr;
1229 struct ocrdma_mbx_rsp req;
1230
1231 u32 id;
1232 };
1233
1234 enum {
1235 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0,
1236 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF,
1237 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16,
1238 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF <<
1239 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1240
1241 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1242 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF,
1243 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16,
1244 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF <<
1245 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1246 };
1247
1248 struct ocrdma_query_srq_rsp {
1249 struct ocrdma_mqe_hdr hdr;
1250 struct ocrdma_mbx_rsp req;
1251
1252 u32 max_rqe_pdid;
1253 u32 srq_lmt_max_sge;
1254 };
1255
1256 enum {
1257 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0,
1258 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF
1259 };
1260
1261 struct ocrdma_destroy_srq {
1262 struct ocrdma_mqe_hdr hdr;
1263 struct ocrdma_mbx_rsp req;
1264
1265 u32 id;
1266 };
1267
1268 enum {
1269 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16),
1270 OCRDMA_DPP_PAGE_SIZE = 4096
1271 };
1272
1273 struct ocrdma_alloc_pd {
1274 struct ocrdma_mqe_hdr hdr;
1275 struct ocrdma_mbx_hdr req;
1276 u32 enable_dpp_rsvd;
1277 };
1278
1279 enum {
1280 OCRDMA_ALLOC_PD_RSP_DPP = Bit(16),
1281 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20,
1282 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF,
1283 };
1284
1285 struct ocrdma_alloc_pd_rsp {
1286 struct ocrdma_mqe_hdr hdr;
1287 struct ocrdma_mbx_rsp rsp;
1288 u32 dpp_page_pdid;
1289 };
1290
1291 struct ocrdma_dealloc_pd {
1292 struct ocrdma_mqe_hdr hdr;
1293 struct ocrdma_mbx_hdr req;
1294 u32 id;
1295 };
1296
1297 struct ocrdma_dealloc_pd_rsp {
1298 struct ocrdma_mqe_hdr hdr;
1299 struct ocrdma_mbx_rsp rsp;
1300 };
1301
1302 enum {
1303 OCRDMA_ADDR_CHECK_ENABLE = 1,
1304 OCRDMA_ADDR_CHECK_DISABLE = 0
1305 };
1306
1307 enum {
1308 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0,
1309 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF,
1310
1311 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0,
1312 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0),
1313 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1,
1314 OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1),
1315 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2,
1316 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2),
1317 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3,
1318 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3),
1319 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4,
1320 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4),
1321 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5,
1322 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5),
1323 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6),
1324 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6,
1325 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,
1326 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF <<
1327 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1328 };
1329
1330 struct ocrdma_alloc_lkey {
1331 struct ocrdma_mqe_hdr hdr;
1332 struct ocrdma_mbx_hdr req;
1333
1334 u32 pdid;
1335 u32 pbl_sz_flags;
1336 };
1337
1338 struct ocrdma_alloc_lkey_rsp {
1339 struct ocrdma_mqe_hdr hdr;
1340 struct ocrdma_mbx_rsp rsp;
1341
1342 u32 lrkey;
1343 u32 num_pbl_rsvd;
1344 };
1345
1346 struct ocrdma_dealloc_lkey {
1347 struct ocrdma_mqe_hdr hdr;
1348 struct ocrdma_mbx_hdr req;
1349
1350 u32 lkey;
1351 u32 rsvd_frmr;
1352 };
1353
1354 struct ocrdma_dealloc_lkey_rsp {
1355 struct ocrdma_mqe_hdr hdr;
1356 struct ocrdma_mbx_rsp rsp;
1357 };
1358
1359 #define MAX_OCRDMA_NSMR_PBL (u32)22
1360 #define MAX_OCRDMA_PBL_SIZE 65536
1361 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1362
1363 enum {
1364 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0,
1365 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF,
1366 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24,
1367 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF <<
1368 OCRDMA_REG_NSMR_LRKEY_SHIFT,
1369
1370 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0,
1371 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF,
1372 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16,
1373 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF <<
1374 OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1375
1376 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0,
1377 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF,
1378 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16,
1379 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF <<
1380 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1381 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24,
1382 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24),
1383 OCRDMA_REG_NSMR_ZB_SHIFT = 25,
1384 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25),
1385 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26,
1386 OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26),
1387 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27,
1388 OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27),
1389 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28,
1390 OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28),
1391 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29,
1392 OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29),
1393 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30,
1394 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30),
1395 OCRDMA_REG_NSMR_LAST_SHIFT = 31,
1396 OCRDMA_REG_NSMR_LAST_MASK = Bit(31)
1397 };
1398
1399 struct ocrdma_reg_nsmr {
1400 struct ocrdma_mqe_hdr hdr;
1401 struct ocrdma_mbx_hdr cmd;
1402
1403 u32 fr_mr;
1404 u32 num_pbl_pdid;
1405 u32 flags_hpage_pbe_sz;
1406 u32 totlen_low;
1407 u32 totlen_high;
1408 u32 fbo_low;
1409 u32 fbo_high;
1410 u32 va_loaddr;
1411 u32 va_hiaddr;
1412 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1413 };
1414
1415 enum {
1416 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0,
1417 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF,
1418 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16,
1419 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF <<
1420 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1421
1422 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31,
1423 OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31)
1424 };
1425
1426 struct ocrdma_reg_nsmr_cont {
1427 struct ocrdma_mqe_hdr hdr;
1428 struct ocrdma_mbx_hdr cmd;
1429
1430 u32 lrkey;
1431 u32 num_pbl_offset;
1432 u32 last;
1433
1434 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1435 };
1436
1437 struct ocrdma_pbe {
1438 u32 pa_hi;
1439 u32 pa_lo;
1440 };
1441
1442 enum {
1443 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16,
1444 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000
1445 };
1446 struct ocrdma_reg_nsmr_rsp {
1447 struct ocrdma_mqe_hdr hdr;
1448 struct ocrdma_mbx_rsp rsp;
1449
1450 u32 lrkey;
1451 u32 num_pbl;
1452 };
1453
1454 enum {
1455 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0,
1456 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF,
1457 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24,
1458 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF <<
1459 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1460
1461 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16,
1462 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF <<
1463 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1464 };
1465
1466 struct ocrdma_reg_nsmr_cont_rsp {
1467 struct ocrdma_mqe_hdr hdr;
1468 struct ocrdma_mbx_rsp rsp;
1469
1470 u32 lrkey_key_index;
1471 u32 num_pbl;
1472 };
1473
1474 enum {
1475 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0,
1476 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF
1477 };
1478
1479 struct ocrdma_alloc_mw {
1480 struct ocrdma_mqe_hdr hdr;
1481 struct ocrdma_mbx_hdr req;
1482
1483 u32 pdid;
1484 };
1485
1486 enum {
1487 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0,
1488 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF
1489 };
1490
1491 struct ocrdma_alloc_mw_rsp {
1492 struct ocrdma_mqe_hdr hdr;
1493 struct ocrdma_mbx_rsp rsp;
1494
1495 u32 lrkey_index;
1496 };
1497
1498 struct ocrdma_attach_mcast {
1499 struct ocrdma_mqe_hdr hdr;
1500 struct ocrdma_mbx_hdr req;
1501 u32 qp_id;
1502 u8 mgid[16];
1503 u32 mac_b0_to_b3;
1504 u32 vlan_mac_b4_to_b5;
1505 };
1506
1507 struct ocrdma_attach_mcast_rsp {
1508 struct ocrdma_mqe_hdr hdr;
1509 struct ocrdma_mbx_rsp rsp;
1510 };
1511
1512 struct ocrdma_detach_mcast {
1513 struct ocrdma_mqe_hdr hdr;
1514 struct ocrdma_mbx_hdr req;
1515 u32 qp_id;
1516 u8 mgid[16];
1517 u32 mac_b0_to_b3;
1518 u32 vlan_mac_b4_to_b5;
1519 };
1520
1521 struct ocrdma_detach_mcast_rsp {
1522 struct ocrdma_mqe_hdr hdr;
1523 struct ocrdma_mbx_rsp rsp;
1524 };
1525
1526 enum {
1527 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19,
1528 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF <<
1529 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1530
1531 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16,
1532 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 <<
1533 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1534
1535 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23,
1536 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF <<
1537 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1538 };
1539
1540 #define OCRDMA_AH_TBL_PAGES 8
1541
1542 struct ocrdma_create_ah_tbl {
1543 struct ocrdma_mqe_hdr hdr;
1544 struct ocrdma_mbx_hdr req;
1545
1546 u32 ah_conf;
1547 struct ocrdma_pa tbl_addr[8];
1548 };
1549
1550 struct ocrdma_create_ah_tbl_rsp {
1551 struct ocrdma_mqe_hdr hdr;
1552 struct ocrdma_mbx_rsp rsp;
1553 u32 ahid;
1554 };
1555
1556 struct ocrdma_delete_ah_tbl {
1557 struct ocrdma_mqe_hdr hdr;
1558 struct ocrdma_mbx_hdr req;
1559 u32 ahid;
1560 };
1561
1562 struct ocrdma_delete_ah_tbl_rsp {
1563 struct ocrdma_mqe_hdr hdr;
1564 struct ocrdma_mbx_rsp rsp;
1565 };
1566
1567 enum {
1568 OCRDMA_EQE_VALID_SHIFT = 0,
1569 OCRDMA_EQE_VALID_MASK = Bit(0),
1570 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE,
1571 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,
1572 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF <<
1573 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1574 };
1575
1576 struct ocrdma_eqe {
1577 u32 id_valid;
1578 };
1579
1580 enum OCRDMA_CQE_STATUS {
1581 OCRDMA_CQE_SUCCESS = 0,
1582 OCRDMA_CQE_LOC_LEN_ERR,
1583 OCRDMA_CQE_LOC_QP_OP_ERR,
1584 OCRDMA_CQE_LOC_EEC_OP_ERR,
1585 OCRDMA_CQE_LOC_PROT_ERR,
1586 OCRDMA_CQE_WR_FLUSH_ERR,
1587 OCRDMA_CQE_MW_BIND_ERR,
1588 OCRDMA_CQE_BAD_RESP_ERR,
1589 OCRDMA_CQE_LOC_ACCESS_ERR,
1590 OCRDMA_CQE_REM_INV_REQ_ERR,
1591 OCRDMA_CQE_REM_ACCESS_ERR,
1592 OCRDMA_CQE_REM_OP_ERR,
1593 OCRDMA_CQE_RETRY_EXC_ERR,
1594 OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1595 OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1596 OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1597 OCRDMA_CQE_REM_ABORT_ERR,
1598 OCRDMA_CQE_INV_EECN_ERR,
1599 OCRDMA_CQE_INV_EEC_STATE_ERR,
1600 OCRDMA_CQE_FATAL_ERR,
1601 OCRDMA_CQE_RESP_TIMEOUT_ERR,
1602 OCRDMA_CQE_GENERAL_ERR
1603 };
1604
1605 enum {
1606 /* w0 */
1607 OCRDMA_CQE_WQEIDX_SHIFT = 0,
1608 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF,
1609
1610 /* w1 */
1611 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16,
1612 OCRDMA_CQE_PKEY_SHIFT = 0,
1613 OCRDMA_CQE_PKEY_MASK = 0xFFFF,
1614
1615 /* w2 */
1616 OCRDMA_CQE_QPN_SHIFT = 0,
1617 OCRDMA_CQE_QPN_MASK = 0x0000FFFF,
1618
1619 OCRDMA_CQE_BUFTAG_SHIFT = 16,
1620 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1621
1622 /* w3 */
1623 OCRDMA_CQE_UD_STATUS_SHIFT = 24,
1624 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1625 OCRDMA_CQE_STATUS_SHIFT = 16,
1626 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1627 OCRDMA_CQE_VALID = Bit(31),
1628 OCRDMA_CQE_INVALIDATE = Bit(30),
1629 OCRDMA_CQE_QTYPE = Bit(29),
1630 OCRDMA_CQE_IMM = Bit(28),
1631 OCRDMA_CQE_WRITE_IMM = Bit(27),
1632 OCRDMA_CQE_QTYPE_SQ = 0,
1633 OCRDMA_CQE_QTYPE_RQ = 1,
1634 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF
1635 };
1636
1637 struct ocrdma_cqe {
1638 union {
1639 /* w0 to w2 */
1640 struct {
1641 u32 wqeidx;
1642 u32 bytes_xfered;
1643 u32 qpn;
1644 } wq;
1645 struct {
1646 u32 lkey_immdt;
1647 u32 rxlen;
1648 u32 buftag_qpn;
1649 } rq;
1650 struct {
1651 u32 lkey_immdt;
1652 u32 rxlen_pkey;
1653 u32 buftag_qpn;
1654 } ud;
1655 struct {
1656 u32 word_0;
1657 u32 word_1;
1658 u32 qpn;
1659 } cmn;
1660 };
1661 u32 flags_status_srcqpn; /* w3 */
1662 };
1663
1664 struct ocrdma_sge {
1665 u32 addr_hi;
1666 u32 addr_lo;
1667 u32 lrkey;
1668 u32 len;
1669 };
1670
1671 enum {
1672 OCRDMA_FLAG_SIG = 0x1,
1673 OCRDMA_FLAG_INV = 0x2,
1674 OCRDMA_FLAG_FENCE_L = 0x4,
1675 OCRDMA_FLAG_FENCE_R = 0x8,
1676 OCRDMA_FLAG_SOLICIT = 0x10,
1677 OCRDMA_FLAG_IMM = 0x20,
1678
1679 /* Stag flags */
1680 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1,
1681 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2,
1682 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4,
1683 OCRDMA_LKEY_FLAG_VATO = 0x8,
1684 };
1685
1686 enum OCRDMA_WQE_OPCODE {
1687 OCRDMA_WRITE = 0x06,
1688 OCRDMA_READ = 0x0C,
1689 OCRDMA_RESV0 = 0x02,
1690 OCRDMA_SEND = 0x00,
1691 OCRDMA_CMP_SWP = 0x14,
1692 OCRDMA_BIND_MW = 0x10,
1693 OCRDMA_FR_MR = 0x11,
1694 OCRDMA_RESV1 = 0x0A,
1695 OCRDMA_LKEY_INV = 0x15,
1696 OCRDMA_FETCH_ADD = 0x13,
1697 OCRDMA_POST_RQ = 0x12
1698 };
1699
1700 enum {
1701 OCRDMA_TYPE_INLINE = 0x0,
1702 OCRDMA_TYPE_LKEY = 0x1,
1703 };
1704
1705 enum {
1706 OCRDMA_WQE_OPCODE_SHIFT = 0,
1707 OCRDMA_WQE_OPCODE_MASK = 0x0000001F,
1708 OCRDMA_WQE_FLAGS_SHIFT = 5,
1709 OCRDMA_WQE_TYPE_SHIFT = 16,
1710 OCRDMA_WQE_TYPE_MASK = 0x00030000,
1711 OCRDMA_WQE_SIZE_SHIFT = 18,
1712 OCRDMA_WQE_SIZE_MASK = 0xFF,
1713 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25,
1714
1715 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0,
1716 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF
1717 };
1718
1719 /* header WQE for all the SQ and RQ operations */
1720 struct ocrdma_hdr_wqe {
1721 u32 cw;
1722 union {
1723 u32 rsvd_tag;
1724 u32 rsvd_lkey_flags;
1725 };
1726 union {
1727 u32 immdt;
1728 u32 lkey;
1729 };
1730 u32 total_len;
1731 };
1732
1733 struct ocrdma_ewqe_ud_hdr {
1734 u32 rsvd_dest_qpn;
1735 u32 qkey;
1736 u32 rsvd_ahid;
1737 u32 rsvd;
1738 };
1739
1740 /* extended wqe followed by hdr_wqe for Fast Memory register */
1741 struct ocrdma_ewqe_fr {
1742 u32 va_hi;
1743 u32 va_lo;
1744 u32 fbo_hi;
1745 u32 fbo_lo;
1746 u32 size_sge;
1747 u32 num_sges;
1748 u32 rsvd;
1749 u32 rsvd2;
1750 };
1751
1752 struct ocrdma_eth_basic {
1753 u8 dmac[6];
1754 u8 smac[6];
1755 __be16 eth_type;
1756 } __packed;
1757
1758 struct ocrdma_eth_vlan {
1759 u8 dmac[6];
1760 u8 smac[6];
1761 __be16 eth_type;
1762 __be16 vlan_tag;
1763 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1764 __be16 roce_eth_type;
1765 } __packed;
1766
1767 struct ocrdma_grh {
1768 __be32 tclass_flow;
1769 __be32 pdid_hoplimit;
1770 u8 sgid[16];
1771 u8 dgid[16];
1772 u16 rsvd;
1773 } __packed;
1774
1775 #define OCRDMA_AV_VALID Bit(7)
1776 #define OCRDMA_AV_VLAN_VALID Bit(1)
1777
1778 struct ocrdma_av {
1779 struct ocrdma_eth_vlan eth_hdr;
1780 struct ocrdma_grh grh;
1781 u32 valid;
1782 } __packed;
1783
1784 struct ocrdma_rsrc_stats {
1785 u32 dpp_pds;
1786 u32 non_dpp_pds;
1787 u32 rc_dpp_qps;
1788 u32 uc_dpp_qps;
1789 u32 ud_dpp_qps;
1790 u32 rc_non_dpp_qps;
1791 u32 rsvd;
1792 u32 uc_non_dpp_qps;
1793 u32 ud_non_dpp_qps;
1794 u32 rsvd1;
1795 u32 srqs;
1796 u32 rbqs;
1797 u32 r64K_nsmr;
1798 u32 r64K_to_2M_nsmr;
1799 u32 r2M_to_44M_nsmr;
1800 u32 r44M_to_1G_nsmr;
1801 u32 r1G_to_4G_nsmr;
1802 u32 nsmr_count_4G_to_32G;
1803 u32 r32G_to_64G_nsmr;
1804 u32 r64G_to_128G_nsmr;
1805 u32 r128G_to_higher_nsmr;
1806 u32 embedded_nsmr;
1807 u32 frmr;
1808 u32 prefetch_qps;
1809 u32 ondemand_qps;
1810 u32 phy_mr;
1811 u32 mw;
1812 u32 rsvd2[7];
1813 };
1814
1815 struct ocrdma_db_err_stats {
1816 u32 sq_doorbell_errors;
1817 u32 cq_doorbell_errors;
1818 u32 rq_srq_doorbell_errors;
1819 u32 cq_overflow_errors;
1820 u32 rsvd[4];
1821 };
1822
1823 struct ocrdma_wqe_stats {
1824 u32 large_send_rc_wqes_lo;
1825 u32 large_send_rc_wqes_hi;
1826 u32 large_write_rc_wqes_lo;
1827 u32 large_write_rc_wqes_hi;
1828 u32 rsvd[4];
1829 u32 read_wqes_lo;
1830 u32 read_wqes_hi;
1831 u32 frmr_wqes_lo;
1832 u32 frmr_wqes_hi;
1833 u32 mw_bind_wqes_lo;
1834 u32 mw_bind_wqes_hi;
1835 u32 invalidate_wqes_lo;
1836 u32 invalidate_wqes_hi;
1837 u32 rsvd1[2];
1838 u32 dpp_wqe_drops;
1839 u32 rsvd2[5];
1840 };
1841
1842 struct ocrdma_tx_stats {
1843 u32 send_pkts_lo;
1844 u32 send_pkts_hi;
1845 u32 write_pkts_lo;
1846 u32 write_pkts_hi;
1847 u32 read_pkts_lo;
1848 u32 read_pkts_hi;
1849 u32 read_rsp_pkts_lo;
1850 u32 read_rsp_pkts_hi;
1851 u32 ack_pkts_lo;
1852 u32 ack_pkts_hi;
1853 u32 send_bytes_lo;
1854 u32 send_bytes_hi;
1855 u32 write_bytes_lo;
1856 u32 write_bytes_hi;
1857 u32 read_req_bytes_lo;
1858 u32 read_req_bytes_hi;
1859 u32 read_rsp_bytes_lo;
1860 u32 read_rsp_bytes_hi;
1861 u32 ack_timeouts;
1862 u32 rsvd[5];
1863 };
1864
1865
1866 struct ocrdma_tx_qp_err_stats {
1867 u32 local_length_errors;
1868 u32 local_protection_errors;
1869 u32 local_qp_operation_errors;
1870 u32 retry_count_exceeded_errors;
1871 u32 rnr_retry_count_exceeded_errors;
1872 u32 rsvd[3];
1873 };
1874
1875 struct ocrdma_rx_stats {
1876 u32 roce_frame_bytes_lo;
1877 u32 roce_frame_bytes_hi;
1878 u32 roce_frame_icrc_drops;
1879 u32 roce_frame_payload_len_drops;
1880 u32 ud_drops;
1881 u32 qp1_drops;
1882 u32 psn_error_request_packets;
1883 u32 psn_error_resp_packets;
1884 u32 rnr_nak_timeouts;
1885 u32 rnr_nak_receives;
1886 u32 roce_frame_rxmt_drops;
1887 u32 nak_count_psn_sequence_errors;
1888 u32 rc_drop_count_lookup_errors;
1889 u32 rq_rnr_naks;
1890 u32 srq_rnr_naks;
1891 u32 roce_frames_lo;
1892 u32 roce_frames_hi;
1893 u32 rsvd;
1894 };
1895
1896 struct ocrdma_rx_qp_err_stats {
1897 u32 nak_invalid_requst_errors;
1898 u32 nak_remote_operation_errors;
1899 u32 nak_count_remote_access_errors;
1900 u32 local_length_errors;
1901 u32 local_protection_errors;
1902 u32 local_qp_operation_errors;
1903 u32 rsvd[2];
1904 };
1905
1906 struct ocrdma_tx_dbg_stats {
1907 u32 data[100];
1908 };
1909
1910 struct ocrdma_rx_dbg_stats {
1911 u32 data[200];
1912 };
1913
1914 struct ocrdma_rdma_stats_req {
1915 struct ocrdma_mbx_hdr hdr;
1916 u8 reset_stats;
1917 u8 rsvd[3];
1918 } __packed;
1919
1920 struct ocrdma_rdma_stats_resp {
1921 struct ocrdma_mbx_hdr hdr;
1922 struct ocrdma_rsrc_stats act_rsrc_stats;
1923 struct ocrdma_rsrc_stats th_rsrc_stats;
1924 struct ocrdma_db_err_stats db_err_stats;
1925 struct ocrdma_wqe_stats wqe_stats;
1926 struct ocrdma_tx_stats tx_stats;
1927 struct ocrdma_tx_qp_err_stats tx_qp_err_stats;
1928 struct ocrdma_rx_stats rx_stats;
1929 struct ocrdma_rx_qp_err_stats rx_qp_err_stats;
1930 struct ocrdma_tx_dbg_stats tx_dbg_stats;
1931 struct ocrdma_rx_dbg_stats rx_dbg_stats;
1932 } __packed;
1933
1934 enum {
1935 OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK = 0xFF,
1936 OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK = 0xFF00,
1937 OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT = 0x08,
1938 OCRDMA_HBA_ATTRB_CDBLEN_MASK = 0xFFFF,
1939 OCRDMA_HBA_ATTRB_ASIC_REV_MASK = 0xFF0000,
1940 OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT = 0x10,
1941 OCRDMA_HBA_ATTRB_GUID0_MASK = 0xFF000000,
1942 OCRDMA_HBA_ATTRB_GUID0_SHIFT = 0x18,
1943 OCRDMA_HBA_ATTRB_GUID13_MASK = 0xFF,
1944 OCRDMA_HBA_ATTRB_GUID14_MASK = 0xFF00,
1945 OCRDMA_HBA_ATTRB_GUID14_SHIFT = 0x08,
1946 OCRDMA_HBA_ATTRB_GUID15_MASK = 0xFF0000,
1947 OCRDMA_HBA_ATTRB_GUID15_SHIFT = 0x10,
1948 OCRDMA_HBA_ATTRB_PCNT_MASK = 0xFF000000,
1949 OCRDMA_HBA_ATTRB_PCNT_SHIFT = 0x18,
1950 OCRDMA_HBA_ATTRB_LDTOUT_MASK = 0xFFFF,
1951 OCRDMA_HBA_ATTRB_ISCSI_VER_MASK = 0xFF0000,
1952 OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT = 0x10,
1953 OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK = 0xFF000000,
1954 OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT = 0x18,
1955 OCRDMA_HBA_ATTRB_CV_MASK = 0xFF,
1956 OCRDMA_HBA_ATTRB_HBA_ST_MASK = 0xFF00,
1957 OCRDMA_HBA_ATTRB_HBA_ST_SHIFT = 0x08,
1958 OCRDMA_HBA_ATTRB_MAX_DOMS_MASK = 0xFF0000,
1959 OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT = 0x10,
1960 OCRDMA_HBA_ATTRB_PTNUM_MASK = 0x3F000000,
1961 OCRDMA_HBA_ATTRB_PTNUM_SHIFT = 0x18,
1962 OCRDMA_HBA_ATTRB_PT_MASK = 0xC0000000,
1963 OCRDMA_HBA_ATTRB_PT_SHIFT = 0x1E,
1964 OCRDMA_HBA_ATTRB_ISCSI_FET_MASK = 0xFF,
1965 OCRDMA_HBA_ATTRB_ASIC_GEN_MASK = 0xFF00,
1966 OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT = 0x08,
1967 OCRDMA_HBA_ATTRB_PCI_VID_MASK = 0xFFFF,
1968 OCRDMA_HBA_ATTRB_PCI_DID_MASK = 0xFFFF0000,
1969 OCRDMA_HBA_ATTRB_PCI_DID_SHIFT = 0x10,
1970 OCRDMA_HBA_ATTRB_PCI_SVID_MASK = 0xFFFF,
1971 OCRDMA_HBA_ATTRB_PCI_SSID_MASK = 0xFFFF0000,
1972 OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT = 0x10,
1973 OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK = 0xFF,
1974 OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK = 0xFF00,
1975 OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT = 0x08,
1976 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK = 0xFF0000,
1977 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT = 0x10,
1978 OCRDMA_HBA_ATTRB_IF_TYPE_MASK = 0xFF000000,
1979 OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT = 0x18,
1980 OCRDMA_HBA_ATTRB_NETFIL_MASK =0xFF
1981 };
1982
1983 struct mgmt_hba_attribs {
1984 u8 flashrom_version_string[32];
1985 u8 manufacturer_name[32];
1986 u32 supported_modes;
1987 u32 rsvd_eprom_verhi_verlo;
1988 u32 mbx_ds_ver;
1989 u32 epfw_ds_ver;
1990 u8 ncsi_ver_string[12];
1991 u32 default_extended_timeout;
1992 u8 controller_model_number[32];
1993 u8 controller_description[64];
1994 u8 controller_serial_number[32];
1995 u8 ip_version_string[32];
1996 u8 firmware_version_string[32];
1997 u8 bios_version_string[32];
1998 u8 redboot_version_string[32];
1999 u8 driver_version_string[32];
2000 u8 fw_on_flash_version_string[32];
2001 u32 functionalities_supported;
2002 u32 guid0_asicrev_cdblen;
2003 u8 generational_guid[12];
2004 u32 portcnt_guid15;
2005 u32 mfuncdev_iscsi_ldtout;
2006 u32 ptpnum_maxdoms_hbast_cv;
2007 u32 firmware_post_status;
2008 u32 hba_mtu[8];
2009 u32 res_asicgen_iscsi_feaures;
2010 u32 rsvd1[3];
2011 };
2012
2013 struct mgmt_controller_attrib {
2014 struct mgmt_hba_attribs hba_attribs;
2015 u32 pci_did_vid;
2016 u32 pci_ssid_svid;
2017 u32 ityp_fnum_devnum_bnum;
2018 u32 uid_hi;
2019 u32 uid_lo;
2020 u32 res_nnetfil;
2021 u32 rsvd0[4];
2022 };
2023
2024 struct ocrdma_get_ctrl_attribs_rsp {
2025 struct ocrdma_mbx_hdr hdr;
2026 struct mgmt_controller_attrib ctrl_attribs;
2027 };
2028
2029 #define OCRDMA_SUBSYS_DCBX 0x10
2030
2031 enum OCRDMA_DCBX_OPCODE {
2032 OCRDMA_CMD_GET_DCBX_CONFIG = 0x01
2033 };
2034
2035 enum OCRDMA_DCBX_PARAM_TYPE {
2036 OCRDMA_PARAMETER_TYPE_ADMIN = 0x00,
2037 OCRDMA_PARAMETER_TYPE_OPER = 0x01,
2038 OCRDMA_PARAMETER_TYPE_PEER = 0x02
2039 };
2040
2041 enum OCRDMA_DCBX_APP_PROTO {
2042 OCRDMA_APP_PROTO_ROCE = 0x8915
2043 };
2044
2045 enum OCRDMA_DCBX_PROTO {
2046 OCRDMA_PROTO_SELECT_L2 = 0x00,
2047 OCRDMA_PROTO_SELECT_L4 = 0x01
2048 };
2049
2050 enum OCRDMA_DCBX_APP_PARAM {
2051 OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,
2052 OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,
2053 OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,
2054 OCRDMA_APP_PARAM_VALID_MASK = 0xFF,
2055 OCRDMA_APP_PARAM_VALID_SHIFT = 0x18
2056 };
2057
2058 enum OCRDMA_DCBX_STATE_FLAGS {
2059 OCRDMA_STATE_FLAG_ENABLED = 0x01,
2060 OCRDMA_STATE_FLAG_ADDVERTISED = 0x02,
2061 OCRDMA_STATE_FLAG_WILLING = 0x04,
2062 OCRDMA_STATE_FLAG_SYNC = 0x08,
2063 OCRDMA_STATE_FLAG_UNSUPPORTED = 0x40000000,
2064 OCRDMA_STATE_FLAG_NEG_FAILD = 0x80000000
2065 };
2066
2067 enum OCRDMA_TCV_AEV_OPV_ST {
2068 OCRDMA_DCBX_TC_SUPPORT_MASK = 0xFF,
2069 OCRDMA_DCBX_TC_SUPPORT_SHIFT = 0x18,
2070 OCRDMA_DCBX_APP_ENTRY_SHIFT = 0x10,
2071 OCRDMA_DCBX_OP_PARAM_SHIFT = 0x08,
2072 OCRDMA_DCBX_STATE_MASK = 0xFF
2073 };
2074
2075 struct ocrdma_app_parameter {
2076 u32 valid_proto_app;
2077 u32 oui;
2078 u32 app_prio[2];
2079 };
2080
2081 struct ocrdma_dcbx_cfg {
2082 u32 tcv_aev_opv_st;
2083 u32 tc_state;
2084 u32 pfc_state;
2085 u32 qcn_state;
2086 u32 appl_state;
2087 u32 ll_state;
2088 u32 tc_bw[2];
2089 u32 tc_prio[8];
2090 u32 pfc_prio[2];
2091 struct ocrdma_app_parameter app_param[15];
2092 };
2093
2094 struct ocrdma_get_dcbx_cfg_req {
2095 struct ocrdma_mbx_hdr hdr;
2096 u32 param_type;
2097 } __packed;
2098
2099 struct ocrdma_get_dcbx_cfg_rsp {
2100 struct ocrdma_mbx_rsp hdr;
2101 struct ocrdma_dcbx_cfg cfg;
2102 } __packed;
2103
2104 #endif /* __OCRDMA_SLI_H__ */
Linux kernel - Deliverables
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