drivers/infiniband/hw/qib/qib_twsi.c

   1 /*
   2  * Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/pci.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include "qib.h"
  39
  40 /*
  41  * QLogic_IB "Two Wire Serial Interface" driver.
  42  * Originally written for a not-quite-i2c serial eeprom, which is
  43  * still used on some supported boards. Later boards have added a
  44  * variety of other uses, most board-specific, so teh bit-boffing
  45  * part has been split off to this file, while the other parts
  46  * have been moved to chip-specific files.
  47  *
  48  * We have also dropped all pretense of fully generic (e.g. pretend
  49  * we don't know whether '1' is the higher voltage) interface, as
  50  * the restrictions of the generic i2c interface (e.g. no access from
  51  * driver itself) make it unsuitable for this use.
  52  */
  53
  54 #define READ_CMD 1
  55 #define WRITE_CMD 0
  56
  57 /**
  58  * i2c_wait_for_writes - wait for a write
  59  * @dd: the qlogic_ib device
  60  *
  61  * We use this instead of udelay directly, so we can make sure
  62  * that previous register writes have been flushed all the way
  63  * to the chip.  Since we are delaying anyway, the cost doesn't
  64  * hurt, and makes the bit twiddling more regular
  65  */
  66 static void i2c_wait_for_writes(struct qib_devdata *dd)
  67 {
  68         /*
  69          * implicit read of EXTStatus is as good as explicit
  70          * read of scratch, if all we want to do is flush
  71          * writes.
  72          */
  73         dd->f_gpio_mod(dd, 0, 0, 0);
  74         rmb(); /* inlined, so prevent compiler reordering */
  75 }
  76
  77 /*
  78  * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
  79  * for "almost compliant" modules
  80  */
  81 #define SCL_WAIT_USEC 1000
  82
  83 /* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
  84  * Should be 20, but some chips need more.
  85  */
  86 #define TWSI_BUF_WAIT_USEC 60
  87
  88 static void scl_out(struct qib_devdata *dd, u8 bit)
  89 {
  90         u32 mask;
  91
  92         udelay(1);
  93
  94         mask = 1UL << dd->gpio_scl_num;
  95
  96         /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
  97         dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
  98
  99         /*
 100          * Allow for slow slaves by simple
 101          * delay for falling edge, sampling on rise.
 102          */
 103         if (!bit)
 104                 udelay(2);
 105         else {
 106                 int rise_usec;
 107                 for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
 108                         if (mask & dd->f_gpio_mod(dd, 0, 0, 0))
 109                                 break;
 110                         udelay(2);
 111                 }
 112                 if (rise_usec <= 0)
 113                         qib_dev_err(dd, "SCL interface stuck low > %d uSec\n",
 114                                     SCL_WAIT_USEC);
 115         }
 116         i2c_wait_for_writes(dd);
 117 }
 118
 119 static void sda_out(struct qib_devdata *dd, u8 bit)
 120 {
 121         u32 mask;
 122
 123         mask = 1UL << dd->gpio_sda_num;
 124
 125         /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
 126         dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
 127
 128         i2c_wait_for_writes(dd);
 129         udelay(2);
 130 }
 131
 132 static u8 sda_in(struct qib_devdata *dd, int wait)
 133 {
 134         int bnum;
 135         u32 read_val, mask;
 136
 137         bnum = dd->gpio_sda_num;
 138         mask = (1UL << bnum);
 139         /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
 140         dd->f_gpio_mod(dd, 0, 0, mask);
 141         read_val = dd->f_gpio_mod(dd, 0, 0, 0);
 142         if (wait)
 143                 i2c_wait_for_writes(dd);
 144         return (read_val & mask) >> bnum;
 145 }
 146
 147 /**
 148  * i2c_ackrcv - see if ack following write is true
 149  * @dd: the qlogic_ib device
 150  */
 151 static int i2c_ackrcv(struct qib_devdata *dd)
 152 {
 153         u8 ack_received;
 154
 155         /* AT ENTRY SCL = LOW */
 156         /* change direction, ignore data */
 157         ack_received = sda_in(dd, 1);
 158         scl_out(dd, 1);
 159         ack_received = sda_in(dd, 1) == 0;
 160         scl_out(dd, 0);
 161         return ack_received;
 162 }
 163
 164 static void stop_cmd(struct qib_devdata *dd);
 165
 166 /**
 167  * rd_byte - read a byte, sending STOP on last, else ACK
 168  * @dd: the qlogic_ib device
 169  *
 170  * Returns byte shifted out of device
 171  */
 172 static int rd_byte(struct qib_devdata *dd, int last)
 173 {
 174         int bit_cntr, data;
 175
 176         data = 0;
 177
 178         for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
 179                 data <<= 1;
 180                 scl_out(dd, 1);
 181                 data |= sda_in(dd, 0);
 182                 scl_out(dd, 0);
 183         }
 184         if (last) {
 185                 scl_out(dd, 1);
 186                 stop_cmd(dd);
 187         } else {
 188                 sda_out(dd, 0);
 189                 scl_out(dd, 1);
 190                 scl_out(dd, 0);
 191                 sda_out(dd, 1);
 192         }
 193         return data;
 194 }
 195
 196 /**
 197  * wr_byte - write a byte, one bit at a time
 198  * @dd: the qlogic_ib device
 199  * @data: the byte to write
 200  *
 201  * Returns 0 if we got the following ack, otherwise 1
 202  */
 203 static int wr_byte(struct qib_devdata *dd, u8 data)
 204 {
 205         int bit_cntr;
 206         u8 bit;
 207
 208         for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
 209                 bit = (data >> bit_cntr) & 1;
 210                 sda_out(dd, bit);
 211                 scl_out(dd, 1);
 212                 scl_out(dd, 0);
 213         }
 214         return (!i2c_ackrcv(dd)) ? 1 : 0;
 215 }
 216
 217 /*
 218  * issue TWSI start sequence:
 219  * (both clock/data high, clock high, data low while clock is high)
 220  */
 221 static void start_seq(struct qib_devdata *dd)
 222 {
 223         sda_out(dd, 1);
 224         scl_out(dd, 1);
 225         sda_out(dd, 0);
 226         udelay(1);
 227         scl_out(dd, 0);
 228 }
 229
 230 /**
 231  * stop_seq - transmit the stop sequence
 232  * @dd: the qlogic_ib device
 233  *
 234  * (both clock/data low, clock high, data high while clock is high)
 235  */
 236 static void stop_seq(struct qib_devdata *dd)
 237 {
 238         scl_out(dd, 0);
 239         sda_out(dd, 0);
 240         scl_out(dd, 1);
 241         sda_out(dd, 1);
 242 }
 243
 244 /**
 245  * stop_cmd - transmit the stop condition
 246  * @dd: the qlogic_ib device
 247  *
 248  * (both clock/data low, clock high, data high while clock is high)
 249  */
 250 static void stop_cmd(struct qib_devdata *dd)
 251 {
 252         stop_seq(dd);
 253         udelay(TWSI_BUF_WAIT_USEC);
 254 }
 255
 256 /**
 257  * qib_twsi_reset - reset I2C communication
 258  * @dd: the qlogic_ib device
 259  */
 260
 261 int qib_twsi_reset(struct qib_devdata *dd)
 262 {
 263         int clock_cycles_left = 9;
 264         int was_high = 0;
 265         u32 pins, mask;
 266
 267         /* Both SCL and SDA should be high. If not, there
 268          * is something wrong.
 269          */
 270         mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num);
 271
 272         /*
 273          * Force pins to desired innocuous state.
 274          * This is the default power-on state with out=0 and dir=0,
 275          * So tri-stated and should be floating high (barring HW problems)
 276          */
 277         dd->f_gpio_mod(dd, 0, 0, mask);
 278
 279         /*
 280          * Clock nine times to get all listeners into a sane state.
 281          * If SDA does not go high at any point, we are wedged.
 282          * One vendor recommends then issuing START followed by STOP.
 283          * we cannot use our "normal" functions to do that, because
 284          * if SCL drops between them, another vendor's part will
 285          * wedge, dropping SDA and keeping it low forever, at the end of
 286          * the next transaction (even if it was not the device addressed).
 287          * So our START and STOP take place with SCL held high.
 288          */
 289         while (clock_cycles_left--) {
 290                 scl_out(dd, 0);
 291                 scl_out(dd, 1);
 292                 /* Note if SDA is high, but keep clocking to sync slave */
 293                 was_high |= sda_in(dd, 0);
 294         }
 295
 296         if (was_high) {
 297                 /*
 298                  * We saw a high, which we hope means the slave is sync'd.
 299                  * Issue START, STOP, pause for T_BUF.
 300                  */
 301
 302                 pins = dd->f_gpio_mod(dd, 0, 0, 0);
 303                 if ((pins & mask) != mask)
 304                         qib_dev_err(dd, "GPIO pins not at rest: %d\n",
 305                                     pins & mask);
 306                 /* Drop SDA to issue START */
 307                 udelay(1); /* Guarantee .6 uSec setup */
 308                 sda_out(dd, 0);
 309                 udelay(1); /* Guarantee .6 uSec hold */
 310                 /* At this point, SCL is high, SDA low. Raise SDA for STOP */
 311                 sda_out(dd, 1);
 312                 udelay(TWSI_BUF_WAIT_USEC);
 313         }
 314
 315         return !was_high;
 316 }
 317
 318 #define QIB_TWSI_START 0x100
 319 #define QIB_TWSI_STOP 0x200
 320
 321 /* Write byte to TWSI, optionally prefixed with START or suffixed with
 322  * STOP.
 323  * returns 0 if OK (ACK received), else != 0
 324  */
 325 static int qib_twsi_wr(struct qib_devdata *dd, int data, int flags)
 326 {
 327         int ret = 1;
 328         if (flags & QIB_TWSI_START)
 329                 start_seq(dd);
 330
 331         ret = wr_byte(dd, data); /* Leaves SCL low (from i2c_ackrcv()) */
 332
 333         if (flags & QIB_TWSI_STOP)
 334                 stop_cmd(dd);
 335         return ret;
 336 }
 337
 338 /* Added functionality for IBA7220-based cards */
 339 #define QIB_TEMP_DEV 0x98
 340
 341 /*
 342  * qib_twsi_blk_rd
 343  * Formerly called qib_eeprom_internal_read, and only used for eeprom,
 344  * but now the general interface for data transfer from twsi devices.
 345  * One vestige of its former role is that it recognizes a device
 346  * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
 347  * which responded to all TWSI device codes, interpreting them as
 348  * address within device. On all other devices found on board handled by
 349  * this driver, the device is followed by a one-byte "address" which selects
 350  * the "register" or "offset" within the device from which data should
 351  * be read.
 352  */
 353 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr,
 354                     void *buffer, int len)
 355 {
 356         int ret;
 357         u8 *bp = buffer;
 358
 359         ret = 1;
 360
 361         if (dev == QIB_TWSI_NO_DEV) {
 362                 /* legacy not-really-I2C */
 363                 addr = (addr << 1) | READ_CMD;
 364                 ret = qib_twsi_wr(dd, addr, QIB_TWSI_START);
 365         } else {
 366                 /* Actual I2C */
 367                 ret = qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START);
 368                 if (ret) {
 369                         stop_cmd(dd);
 370                         ret = 1;
 371                         goto bail;
 372                 }
 373                 /*
 374                  * SFF spec claims we do _not_ stop after the addr
 375                  * but simply issue a start with the "read" dev-addr.
 376                  * Since we are implicitely waiting for ACK here,
 377                  * we need t_buf (nominally 20uSec) before that start,
 378                  * and cannot rely on the delay built in to the STOP
 379                  */
 380                 ret = qib_twsi_wr(dd, addr, 0);
 381                 udelay(TWSI_BUF_WAIT_USEC);
 382
 383                 if (ret) {
 384                         qib_dev_err(dd,
 385                                 "Failed to write interface read addr %02X\n",
 386                                 addr);
 387                         ret = 1;
 388                         goto bail;
 389                 }
 390                 ret = qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START);
 391         }
 392         if (ret) {
 393                 stop_cmd(dd);
 394                 ret = 1;
 395                 goto bail;
 396         }
 397
 398         /*
 399          * block devices keeps clocking data out as long as we ack,
 400          * automatically incrementing the address. Some have "pages"
 401          * whose boundaries will not be crossed, but the handling
 402          * of these is left to the caller, who is in a better
 403          * position to know.
 404          */
 405         while (len-- > 0) {
 406                 /*
 407                  * Get and store data, sending ACK if length remaining,
 408                  * else STOP
 409                  */
 410                 *bp++ = rd_byte(dd, !len);
 411         }
 412
 413         ret = 0;
 414
 415 bail:
 416         return ret;
 417 }
 418
 419 /*
 420  * qib_twsi_blk_wr
 421  * Formerly called qib_eeprom_internal_write, and only used for eeprom,
 422  * but now the general interface for data transfer to twsi devices.
 423  * One vestige of its former role is that it recognizes a device
 424  * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
 425  * which responded to all TWSI device codes, interpreting them as
 426  * address within device. On all other devices found on board handled by
 427  * this driver, the device is followed by a one-byte "address" which selects
 428  * the "register" or "offset" within the device to which data should
 429  * be written.
 430  */
 431 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
 432                     const void *buffer, int len)
 433 {
 434         int sub_len;
 435         const u8 *bp = buffer;
 436         int max_wait_time, i;
 437         int ret;
 438         ret = 1;
 439
 440         while (len > 0) {
 441                 if (dev == QIB_TWSI_NO_DEV) {
 442                         if (qib_twsi_wr(dd, (addr << 1) | WRITE_CMD,
 443                                         QIB_TWSI_START)) {
 444                                 goto failed_write;
 445                         }
 446                 } else {
 447                         /* Real I2C */
 448                         if (qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START))
 449                                 goto failed_write;
 450                         ret = qib_twsi_wr(dd, addr, 0);
 451                         if (ret) {
 452                                 qib_dev_err(dd, "Failed to write interface"
 453                                             " write addr %02X\n", addr);
 454                                 goto failed_write;
 455                         }
 456                 }
 457
 458                 sub_len = min(len, 4);
 459                 addr += sub_len;
 460                 len -= sub_len;
 461
 462                 for (i = 0; i < sub_len; i++)
 463                         if (qib_twsi_wr(dd, *bp++, 0))
 464                                 goto failed_write;
 465
 466                 stop_cmd(dd);
 467
 468                 /*
 469                  * Wait for write complete by waiting for a successful
 470                  * read (the chip replies with a zero after the write
 471                  * cmd completes, and before it writes to the eeprom.
 472                  * The startcmd for the read will fail the ack until
 473                  * the writes have completed.   We do this inline to avoid
 474                  * the debug prints that are in the real read routine
 475                  * if the startcmd fails.
 476                  * We also use the proper device address, so it doesn't matter
 477                  * whether we have real eeprom_dev. Legacy likes any address.
 478                  */
 479                 max_wait_time = 100;
 480                 while (qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START)) {
 481                         stop_cmd(dd);
 482                         if (!--max_wait_time)
 483                                 goto failed_write;
 484                 }
 485                 /* now read (and ignore) the resulting byte */
 486                 rd_byte(dd, 1);
 487         }
 488
 489         ret = 0;
 490         goto bail;
 491
 492 failed_write:
 493         stop_cmd(dd);
 494         ret = 1;
 495
 496 bail:
 497         return ret;
 498 }